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authorDhananjay Phadke <dhananjay@netxen.com>2008-07-21 22:44:03 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-07-22 17:51:44 -0400
commit3ce06a320f8d5a3f16960e63021cc372283efffb (patch)
treecea5b02fc44b8c2367c57d7c249592683edffcc9 /drivers/net/netxen
parente4c93c817ce650401db42db6c869cf7688217ff4 (diff)
netxen: add 2MB PCI memory support
New revision of netxen chip has 2MB PCI memory. Older chips had 128MB addressable PCI memory. To retain compatibility, this patch adds function pointers based on pci bar0 size. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/netxen')
-rw-r--r--drivers/net/netxen/netxen_nic.h70
-rw-r--r--drivers/net/netxen/netxen_nic_ethtool.c31
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c1359
-rw-r--r--drivers/net/netxen/netxen_nic_hw.h21
-rw-r--r--drivers/net/netxen/netxen_nic_init.c54
-rw-r--r--drivers/net/netxen/netxen_nic_isr.c4
-rw-r--r--drivers/net/netxen/netxen_nic_main.c138
-rw-r--r--drivers/net/netxen/netxen_nic_niu.c87
8 files changed, 1492 insertions, 272 deletions
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index acc7d79457d6..29ab2ce30d6e 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -799,6 +799,12 @@ struct netxen_hardware_context {
799 unsigned long first_page_group_start; 799 unsigned long first_page_group_start;
800 void __iomem *db_base; 800 void __iomem *db_base;
801 unsigned long db_len; 801 unsigned long db_len;
802 unsigned long pci_len0;
803
804 int qdr_sn_window;
805 int ddr_mn_window;
806 unsigned long mn_win_crb;
807 unsigned long ms_win_crb;
802 808
803 u8 revision_id; 809 u8 revision_id;
804 u16 board_type; 810 u16 board_type;
@@ -894,6 +900,8 @@ struct netxen_adapter {
894 struct work_struct tx_timeout_task; 900 struct work_struct tx_timeout_task;
895 901
896 u32 curr_window; 902 u32 curr_window;
903 u32 crb_win;
904 rwlock_t adapter_lock;
897 905
898 u32 cmd_producer; 906 u32 cmd_producer;
899 __le32 *cmd_consumer; 907 __le32 *cmd_consumer;
@@ -947,6 +955,17 @@ struct netxen_adapter {
947 int (*init_port) (struct netxen_adapter *, int); 955 int (*init_port) (struct netxen_adapter *, int);
948 void (*init_niu) (struct netxen_adapter *); 956 void (*init_niu) (struct netxen_adapter *);
949 int (*stop_port) (struct netxen_adapter *); 957 int (*stop_port) (struct netxen_adapter *);
958
959 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
960 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
961 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
962 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
963 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
964 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
965 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
966 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
967 unsigned long (*pci_set_window)(struct netxen_adapter *,
968 unsigned long long);
950}; /* netxen_adapter structure */ 969}; /* netxen_adapter structure */
951 970
952/* 971/*
@@ -1022,19 +1041,52 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1022int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); 1041int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1023int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); 1042int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1024void netxen_nic_init_niu_gb(struct netxen_adapter *adapter); 1043void netxen_nic_init_niu_gb(struct netxen_adapter *adapter);
1025void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw);
1026void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); 1044void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1027int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); 1045int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1028void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); 1046void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1029void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value); 1047void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1048void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1049void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1030 1050
1031int netxen_nic_get_board_info(struct netxen_adapter *adapter); 1051int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1032int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, 1052
1033 int len); 1053int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1034int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, 1054 ulong off, void *data, int len);
1035 int len); 1055int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1056 ulong off, void *data, int len);
1057int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1058 u64 off, void *data, int size);
1059int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1060 u64 off, void *data, int size);
1061int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1062 u64 off, u32 data);
1063u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1064void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1065 u64 off, u32 data);
1066u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1067unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1068 unsigned long long addr);
1069void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1070 u32 wndw);
1071
1072int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1073 ulong off, void *data, int len);
1074int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1075 ulong off, void *data, int len);
1076int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1077 u64 off, void *data, int size);
1078int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1079 u64 off, void *data, int size);
1036void netxen_crb_writelit_adapter(struct netxen_adapter *adapter, 1080void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1037 unsigned long off, int data); 1081 unsigned long off, int data);
1082int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1083 u64 off, u32 data);
1084u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1085void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1086 u64 off, u32 data);
1087u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1088unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1089 unsigned long long addr);
1038 1090
1039/* Functions from netxen_nic_init.c */ 1091/* Functions from netxen_nic_init.c */
1040void netxen_free_adapter_offload(struct netxen_adapter *adapter); 1092void netxen_free_adapter_offload(struct netxen_adapter *adapter);
@@ -1129,7 +1181,7 @@ dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1129 u32 ctrl; 1181 u32 ctrl;
1130 1182
1131 /* check if already inactive */ 1183 /* check if already inactive */
1132 if (netxen_nic_hw_read_wx(adapter, 1184 if (adapter->hw_read_wx(adapter,
1133 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) 1185 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1134 printk(KERN_ERR "failed to read dma watchdog status\n"); 1186 printk(KERN_ERR "failed to read dma watchdog status\n");
1135 1187
@@ -1149,7 +1201,7 @@ dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1149{ 1201{
1150 u32 ctrl; 1202 u32 ctrl;
1151 1203
1152 if (netxen_nic_hw_read_wx(adapter, 1204 if (adapter->hw_read_wx(adapter,
1153 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) 1205 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1154 printk(KERN_ERR "failed to read dma watchdog status\n"); 1206 printk(KERN_ERR "failed to read dma watchdog status\n");
1155 1207
@@ -1161,7 +1213,7 @@ dma_watchdog_wakeup(struct netxen_adapter *adapter)
1161{ 1213{
1162 u32 ctrl; 1214 u32 ctrl;
1163 1215
1164 if (netxen_nic_hw_read_wx(adapter, 1216 if (adapter->hw_read_wx(adapter,
1165 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4)) 1217 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1166 printk(KERN_ERR "failed to read dma watchdog status\n"); 1218 printk(KERN_ERR "failed to read dma watchdog status\n");
1167 1219
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
index cacc5280605e..7e49e6106073 100644
--- a/drivers/net/netxen/netxen_nic_ethtool.c
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -93,17 +93,21 @@ static void
93netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) 93netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
94{ 94{
95 struct netxen_adapter *adapter = netdev_priv(dev); 95 struct netxen_adapter *adapter = netdev_priv(dev);
96 unsigned long flags;
96 u32 fw_major = 0; 97 u32 fw_major = 0;
97 u32 fw_minor = 0; 98 u32 fw_minor = 0;
98 u32 fw_build = 0; 99 u32 fw_build = 0;
99 100
100 strncpy(drvinfo->driver, netxen_nic_driver_name, 32); 101 strncpy(drvinfo->driver, netxen_nic_driver_name, 32);
101 strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32); 102 strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32);
102 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter, 103 write_lock_irqsave(&adapter->adapter_lock, flags);
103 NETXEN_FW_VERSION_MAJOR)); 104 fw_major = adapter->pci_read_normalize(adapter,
104 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter, 105 NETXEN_FW_VERSION_MAJOR);
105 NETXEN_FW_VERSION_MINOR)); 106 fw_minor = adapter->pci_read_normalize(adapter,
106 fw_build = readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB)); 107 NETXEN_FW_VERSION_MINOR);
108 fw_build = adapter->pci_read_normalize(adapter,
109 NETXEN_FW_VERSION_SUB);
110 write_unlock_irqrestore(&adapter->adapter_lock, flags);
107 sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build); 111 sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
108 112
109 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); 113 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
@@ -361,19 +365,18 @@ netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
361{ 365{
362 struct netxen_adapter *adapter = netdev_priv(dev); 366 struct netxen_adapter *adapter = netdev_priv(dev);
363 __u32 mode, *regs_buff = p; 367 __u32 mode, *regs_buff = p;
364 void __iomem *addr;
365 int i, window; 368 int i, window;
366 369
367 memset(p, 0, NETXEN_NIC_REGS_LEN); 370 memset(p, 0, NETXEN_NIC_REGS_LEN);
368 regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) | 371 regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
369 (adapter->pdev)->device; 372 (adapter->pdev)->device;
370 /* which mode */ 373 /* which mode */
371 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_MODE, &regs_buff[0]); 374 adapter->hw_read_wx(adapter, NETXEN_NIU_MODE, &regs_buff[0], 4);
372 mode = regs_buff[0]; 375 mode = regs_buff[0];
373 376
374 /* Common registers to all the modes */ 377 /* Common registers to all the modes */
375 NETXEN_NIC_LOCKED_READ_REG(NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER, 378 adapter->hw_read_wx(adapter,
376 &regs_buff[2]); 379 NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER, &regs_buff[2], 4);
377 /* GB/XGB Mode */ 380 /* GB/XGB Mode */
378 mode = (mode / 2) - 1; 381 mode = (mode / 2) - 1;
379 window = 0; 382 window = 0;
@@ -384,9 +387,9 @@ netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
384 window = adapter->physical_port * 387 window = adapter->physical_port *
385 NETXEN_NIC_PORT_WINDOW; 388 NETXEN_NIC_PORT_WINDOW;
386 389
387 NETXEN_NIC_LOCKED_READ_REG(niu_registers[mode]. 390 adapter->hw_read_wx(adapter,
388 reg[i - 3] + window, 391 niu_registers[mode].reg[i - 3] + window,
389 &regs_buff[i]); 392 &regs_buff[i], 4);
390 } 393 }
391 394
392 } 395 }
@@ -410,7 +413,7 @@ static u32 netxen_nic_test_link(struct net_device *dev)
410 return !val; 413 return !val;
411 } 414 }
412 } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) { 415 } else if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
413 val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE)); 416 val = adapter->pci_read_normalize(adapter, CRB_XG_STATE);
414 return (val == XG_LINK_UP) ? 0 : 1; 417 return (val == XG_LINK_UP) ? 0 : 1;
415 } 418 }
416 return -EIO; 419 return -EIO;
@@ -668,7 +671,7 @@ static int netxen_nic_reg_test(struct net_device *dev)
668 data_written = (u32)0xa5a5a5a5; 671 data_written = (u32)0xa5a5a5a5;
669 672
670 netxen_nic_reg_write(adapter, CRB_SCRATCHPAD_TEST, data_written); 673 netxen_nic_reg_write(adapter, CRB_SCRATCHPAD_TEST, data_written);
671 data_read = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_SCRATCHPAD_TEST)); 674 data_read = adapter->pci_read_normalize(adapter, CRB_SCRATCHPAD_TEST);
672 if (data_written != data_read) 675 if (data_written != data_read)
673 return 1; 676 return 1;
674 677
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index a472873f48bd..defbeeac5dbe 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -38,6 +38,248 @@
38 38
39#include <net/ip.h> 39#include <net/ip.h>
40 40
41#define MASK(n) ((1ULL<<(n))-1)
42#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44#define MS_WIN(addr) (addr & 0x0ffc0000)
45
46#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
47
48#define CRB_BLK(off) ((off >> 20) & 0x3f)
49#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50#define CRB_WINDOW_2M (0x130060)
51#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52#define CRB_INDIRECT_2M (0x1e0000UL)
53
54#define CRB_WIN_LOCK_TIMEOUT 100000000
55static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
181 {{{0} } }, /* 35: */
182 {{{0} } }, /* 36: */
183 {{{0} } }, /* 37: */
184 {{{0} } }, /* 38: */
185 {{{0} } }, /* 39: */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
198 {{{0} } }, /* 52: */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210};
211
212/*
213 * top 12 bits of crb internal address (hub, agent)
214 */
215static unsigned crb_hub_agt[64] =
216{
217 0,
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
221 0,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
249 0,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
252 0,
253 0,
254 0,
255 0,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
278 0,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
280 0,
281};
282
41struct netxen_recv_crb recv_crb_registers[] = { 283struct netxen_recv_crb recv_crb_registers[] = {
42 /* 284 /*
43 * Instance 0. 285 * Instance 0.
@@ -123,7 +365,7 @@ static u64 ctx_addr_sig_regs[][3] = {
123#define NETXEN_MIN_MTU 64 365#define NETXEN_MIN_MTU 64
124#define NETXEN_ETH_FCS_SIZE 4 366#define NETXEN_ETH_FCS_SIZE 4
125#define NETXEN_ENET_HEADER_SIZE 14 367#define NETXEN_ENET_HEADER_SIZE 14
126#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ 368#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
127#define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4) 369#define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
128#define NETXEN_NIU_HDRSIZE (0x1 << 6) 370#define NETXEN_NIU_HDRSIZE (0x1 << 6)
129#define NETXEN_NIU_TLRSIZE (0x1 << 5) 371#define NETXEN_NIU_TLRSIZE (0x1 << 5)
@@ -139,8 +381,6 @@ static u64 ctx_addr_sig_regs[][3] = {
139 381
140#define NETXEN_NIC_WINDOW_MARGIN 0x100000 382#define NETXEN_NIC_WINDOW_MARGIN 0x100000
141 383
142static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
143 unsigned long long addr);
144void netxen_free_hw_resources(struct netxen_adapter *adapter); 384void netxen_free_hw_resources(struct netxen_adapter *adapter);
145 385
146int netxen_nic_set_mac(struct net_device *netdev, void *p) 386int netxen_nic_set_mac(struct net_device *netdev, void *p)
@@ -181,9 +421,9 @@ netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
181 if (adapter->mc_enabled) 421 if (adapter->mc_enabled)
182 return 0; 422 return 0;
183 423
184 netxen_nic_hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 424 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
185 val |= (1UL << (28+port)); 425 val |= (1UL << (28+port));
186 netxen_nic_hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 426 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
187 427
188 /* add broadcast addr to filter */ 428 /* add broadcast addr to filter */
189 val = 0xffffff; 429 val = 0xffffff;
@@ -212,9 +452,9 @@ netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
212 if (!adapter->mc_enabled) 452 if (!adapter->mc_enabled)
213 return 0; 453 return 0;
214 454
215 netxen_nic_hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 455 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
216 val &= ~(1UL << (28+port)); 456 val &= ~(1UL << (28+port));
217 netxen_nic_hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); 457 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
218 458
219 val = MAC_HI(addr); 459 val = MAC_HI(addr);
220 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 460 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
@@ -344,18 +584,15 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
344 584
345 585
346 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { 586 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
347 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
348 loops = 0; 587 loops = 0;
349 state = 0; 588 state = 0;
350 /* Window 1 call */ 589 do {
351 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_RCVPEG_STATE));
352 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
353 msleep(1);
354 /* Window 1 call */ 590 /* Window 1 call */
355 state = readl(NETXEN_CRB_NORMALIZE(adapter, 591 state = adapter->pci_read_normalize(adapter,
356 CRB_RCVPEG_STATE)); 592 CRB_RCVPEG_STATE);
593 msleep(1);
357 loops++; 594 loops++;
358 } 595 } while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20);
359 if (loops >= 20) { 596 if (loops >= 20) {
360 printk(KERN_ERR "Rcv Peg initialization not complete:" 597 printk(KERN_ERR "Rcv Peg initialization not complete:"
361 "%x.\n", state); 598 "%x.\n", state);
@@ -363,10 +600,10 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
363 return err; 600 return err;
364 } 601 }
365 } 602 }
366 adapter->intr_scheme = readl( 603 adapter->intr_scheme = adapter->pci_read_normalize(adapter,
367 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW)); 604 CRB_NIC_CAPABILITIES_FW);
368 adapter->msi_mode = readl( 605 adapter->msi_mode = adapter->pci_read_normalize(adapter,
369 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW)); 606 CRB_NIC_MSI_MODE_FW);
370 607
371 addr = pci_alloc_consistent(adapter->pdev, 608 addr = pci_alloc_consistent(adapter->pdev,
372 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), 609 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
@@ -449,12 +686,12 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
449 } 686 }
450 /* Window = 1 */ 687 /* Window = 1 */
451 688
452 writel(lower32(adapter->ctx_desc_phys_addr), 689 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id),
453 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id))); 690 lower32(adapter->ctx_desc_phys_addr));
454 writel(upper32(adapter->ctx_desc_phys_addr), 691 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id),
455 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id))); 692 upper32(adapter->ctx_desc_phys_addr));
456 writel(NETXEN_CTX_SIGNATURE | func_id, 693 adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id),
457 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id))); 694 NETXEN_CTX_SIGNATURE | func_id);
458 return err; 695 return err;
459} 696}
460 697
@@ -601,10 +838,41 @@ int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
601 return 0; 838 return 0;
602} 839}
603 840
841#define CRB_WIN_LOCK_TIMEOUT 100000000
842
843static int crb_win_lock(struct netxen_adapter *adapter)
844{
845 int done = 0, timeout = 0;
846
847 while (!done) {
848 /* acquire semaphore3 from PCI HW block */
849 adapter->hw_read_wx(adapter,
850 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
851 if (done == 1)
852 break;
853 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
854 return -1;
855 timeout++;
856 udelay(1);
857 }
858 netxen_crb_writelit_adapter(adapter,
859 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
860 return 0;
861}
862
863static void crb_win_unlock(struct netxen_adapter *adapter)
864{
865 int val;
866
867 adapter->hw_read_wx(adapter,
868 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
869}
870
604/* 871/*
605 * Changes the CRB window to the specified window. 872 * Changes the CRB window to the specified window.
606 */ 873 */
607void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw) 874void
875netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
608{ 876{
609 void __iomem *offset; 877 void __iomem *offset;
610 u32 tmp; 878 u32 tmp;
@@ -633,7 +901,7 @@ void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
633 while ((tmp = readl(offset)) != wndw) { 901 while ((tmp = readl(offset)) != wndw) {
634 printk(KERN_WARNING "%s: %s WARNING: CRB window value not " 902 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
635 "registered properly: 0x%08x.\n", 903 "registered properly: 0x%08x.\n",
636 netxen_nic_driver_name, __FUNCTION__, tmp); 904 netxen_nic_driver_name, __func__, tmp);
637 mdelay(1); 905 mdelay(1);
638 if (count >= 10) 906 if (count >= 10)
639 break; 907 break;
@@ -646,51 +914,112 @@ void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
646 adapter->curr_window = 0; 914 adapter->curr_window = 0;
647} 915}
648 916
917/*
918 * Return -1 if off is not valid,
919 * 1 if window access is needed. 'off' is set to offset from
920 * CRB space in 128M pci map
921 * 0 if no window access is needed. 'off' is set to 2M addr
922 * In: 'off' is offset from base in 128M pci map
923 */
924static int
925netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
926 ulong *off, int len)
927{
928 unsigned long end = *off + len;
929 crb_128M_2M_sub_block_map_t *m;
930
931
932 if (*off >= NETXEN_CRB_MAX)
933 return -1;
934
935 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
936 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
937 (ulong)adapter->ahw.pci_base0;
938 return 0;
939 }
940
941 if (*off < NETXEN_PCI_CRBSPACE)
942 return -1;
943
944 *off -= NETXEN_PCI_CRBSPACE;
945 end = *off + len;
946
947 /*
948 * Try direct map
949 */
950 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
951
952 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
953 *off = *off + m->start_2M - m->start_128M +
954 (ulong)adapter->ahw.pci_base0;
955 return 0;
956 }
957
958 /*
959 * Not in direct map, use crb window
960 */
961 return 1;
962}
963
964/*
965 * In: 'off' is offset from CRB space in 128M pci map
966 * Out: 'off' is 2M pci map addr
967 * side effect: lock crb window
968 */
969static void
970netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
971{
972 u32 win_read;
973
974 adapter->crb_win = CRB_HI(*off);
975 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
976 adapter->ahw.pci_base0));
977 /*
978 * Read back value to make sure write has gone through before trying
979 * to use it.
980 */
981 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
982 if (win_read != adapter->crb_win) {
983 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
984 "Read crbwin (0x%x), off=0x%lx\n",
985 __func__, adapter->crb_win, win_read, *off);
986 }
987 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
988 (ulong)adapter->ahw.pci_base0;
989}
990
649int netxen_load_firmware(struct netxen_adapter *adapter) 991int netxen_load_firmware(struct netxen_adapter *adapter)
650{ 992{
651 int i; 993 int i;
652 u32 data, size = 0; 994 u32 data, size = 0;
653 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE; 995 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
654 u64 off;
655 void __iomem *addr;
656 996
657 size = NETXEN_FIRMWARE_LEN; 997 size = NETXEN_FIRMWARE_LEN;
658 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); 998 adapter->pci_write_normalize(adapter,
999 NETXEN_ROMUSB_GLB_CAS_RST, 1);
659 1000
660 for (i = 0; i < size; i++) { 1001 for (i = 0; i < size; i++) {
661 int retries = 10;
662 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) 1002 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
663 return -EIO; 1003 return -EIO;
664 1004
665 off = netxen_nic_pci_set_window(adapter, memaddr); 1005 adapter->pci_mem_write(adapter, memaddr, &data, 4);
666 addr = pci_base_offset(adapter, off);
667 writel(data, addr);
668 do {
669 if (readl(addr) == data)
670 break;
671 msleep(100);
672 writel(data, addr);
673 } while (--retries);
674 if (!retries) {
675 printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n",
676 netxen_nic_driver_name, memaddr);
677 return -EIO;
678 }
679 flashaddr += 4; 1006 flashaddr += 4;
680 memaddr += 4; 1007 memaddr += 4;
1008 cond_resched();
681 } 1009 }
682 udelay(100); 1010 udelay(100);
683 /* make sure Casper is powered on */ 1011 /* make sure Casper is powered on */
684 writel(0x3fff, 1012 adapter->pci_write_normalize(adapter,
685 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL)); 1013 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
686 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST)); 1014 adapter->pci_write_normalize(adapter,
1015 NETXEN_ROMUSB_GLB_CAS_RST, 0);
687 1016
688 return 0; 1017 return 0;
689} 1018}
690 1019
691int 1020int
692netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data, 1021netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
693 int len) 1022 ulong off, void *data, int len)
694{ 1023{
695 void __iomem *addr; 1024 void __iomem *addr;
696 1025
@@ -698,7 +1027,7 @@ netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
698 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1027 addr = NETXEN_CRB_NORMALIZE(adapter, off);
699 } else { /* Window 0 */ 1028 } else { /* Window 0 */
700 addr = pci_base_offset(adapter, off); 1029 addr = pci_base_offset(adapter, off);
701 netxen_nic_pci_change_crbwindow(adapter, 0); 1030 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
702 } 1031 }
703 1032
704 DPRINTK(INFO, "writing to base %lx offset %llx addr %p" 1033 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
@@ -706,7 +1035,7 @@ netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
706 pci_base(adapter, off), off, addr, 1035 pci_base(adapter, off), off, addr,
707 *(unsigned long long *)data, len); 1036 *(unsigned long long *)data, len);
708 if (!addr) { 1037 if (!addr) {
709 netxen_nic_pci_change_crbwindow(adapter, 1); 1038 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
710 return 1; 1039 return 1;
711 } 1040 }
712 1041
@@ -733,14 +1062,14 @@ netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
733 break; 1062 break;
734 } 1063 }
735 if (!ADDR_IN_WINDOW1(off)) 1064 if (!ADDR_IN_WINDOW1(off))
736 netxen_nic_pci_change_crbwindow(adapter, 1); 1065 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
737 1066
738 return 0; 1067 return 0;
739} 1068}
740 1069
741int 1070int
742netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data, 1071netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
743 int len) 1072 ulong off, void *data, int len)
744{ 1073{
745 void __iomem *addr; 1074 void __iomem *addr;
746 1075
@@ -748,13 +1077,13 @@ netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
748 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1077 addr = NETXEN_CRB_NORMALIZE(adapter, off);
749 } else { /* Window 0 */ 1078 } else { /* Window 0 */
750 addr = pci_base_offset(adapter, off); 1079 addr = pci_base_offset(adapter, off);
751 netxen_nic_pci_change_crbwindow(adapter, 0); 1080 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
752 } 1081 }
753 1082
754 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", 1083 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
755 pci_base(adapter, off), off, addr); 1084 pci_base(adapter, off), off, addr);
756 if (!addr) { 1085 if (!addr) {
757 netxen_nic_pci_change_crbwindow(adapter, 1); 1086 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
758 return 1; 1087 return 1;
759 } 1088 }
760 switch (len) { 1089 switch (len) {
@@ -778,76 +1107,190 @@ netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
778 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data); 1107 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
779 1108
780 if (!ADDR_IN_WINDOW1(off)) 1109 if (!ADDR_IN_WINDOW1(off))
781 netxen_nic_pci_change_crbwindow(adapter, 1); 1110 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
782 1111
783 return 0; 1112 return 0;
784} 1113}
785 1114
786void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val) 1115int
787{ /* Only for window 1 */ 1116netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
788 void __iomem *addr; 1117 ulong off, void *data, int len)
1118{
1119 unsigned long flags = 0;
1120 int rv;
789 1121
790 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1122 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
791 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
792 pci_base(adapter, off), off, addr, val);
793 writel(val, addr);
794 1123
1124 if (rv == -1) {
1125 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1126 __func__, off);
1127 dump_stack();
1128 return -1;
1129 }
1130
1131 if (rv == 1) {
1132 write_lock_irqsave(&adapter->adapter_lock, flags);
1133 crb_win_lock(adapter);
1134 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1135 }
1136
1137 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1138 *(unsigned long *)data, off, len);
1139
1140 switch (len) {
1141 case 1:
1142 writeb(*(uint8_t *)data, (void *)off);
1143 break;
1144 case 2:
1145 writew(*(uint16_t *)data, (void *)off);
1146 break;
1147 case 4:
1148 writel(*(uint32_t *)data, (void *)off);
1149 break;
1150 case 8:
1151 writeq(*(uint64_t *)data, (void *)off);
1152 break;
1153 default:
1154 DPRINTK(1, INFO,
1155 "writing data %lx to offset %llx, num words=%d\n",
1156 *(unsigned long *)data, off, (len>>3));
1157 break;
1158 }
1159 if (rv == 1) {
1160 crb_win_unlock(adapter);
1161 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1162 }
1163
1164 return 0;
795} 1165}
796 1166
797int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off) 1167int
798{ /* Only for window 1 */ 1168netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
799 void __iomem *addr; 1169 ulong off, void *data, int len)
800 int val; 1170{
1171 unsigned long flags = 0;
1172 int rv;
801 1173
802 addr = NETXEN_CRB_NORMALIZE(adapter, off); 1174 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
803 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", 1175
804 pci_base(adapter, off), off, addr); 1176 if (rv == -1) {
805 val = readl(addr); 1177 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
806 writel(val, addr); 1178 __func__, off);
1179 dump_stack();
1180 return -1;
1181 }
1182
1183 if (rv == 1) {
1184 write_lock_irqsave(&adapter->adapter_lock, flags);
1185 crb_win_lock(adapter);
1186 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1187 }
1188
1189 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1190
1191 switch (len) {
1192 case 1:
1193 *(uint8_t *)data = readb((void *)off);
1194 break;
1195 case 2:
1196 *(uint16_t *)data = readw((void *)off);
1197 break;
1198 case 4:
1199 *(uint32_t *)data = readl((void *)off);
1200 break;
1201 case 8:
1202 *(uint64_t *)data = readq((void *)off);
1203 break;
1204 default:
1205 break;
1206 }
1207
1208 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
807 1209
1210 if (rv == 1) {
1211 crb_win_unlock(adapter);
1212 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1213 }
1214
1215 return 0;
1216}
1217
1218void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1219{
1220 adapter->hw_write_wx(adapter, off, &val, 4);
1221}
1222
1223int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1224{
1225 int val;
1226 adapter->hw_read_wx(adapter, off, &val, 4);
808 return val; 1227 return val;
809} 1228}
810 1229
811/* Change the window to 0, write and change back to window 1. */ 1230/* Change the window to 0, write and change back to window 1. */
812void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value) 1231void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
813{ 1232{
814 void __iomem *addr; 1233 adapter->hw_write_wx(adapter, index, &value, 4);
815
816 netxen_nic_pci_change_crbwindow(adapter, 0);
817 addr = pci_base_offset(adapter, index);
818 writel(value, addr);
819 netxen_nic_pci_change_crbwindow(adapter, 1);
820} 1234}
821 1235
822/* Change the window to 0, read and change back to window 1. */ 1236/* Change the window to 0, read and change back to window 1. */
823void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value) 1237void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
824{ 1238{
825 void __iomem *addr; 1239 adapter->hw_read_wx(adapter, index, value, 4);
1240}
826 1241
827 addr = pci_base_offset(adapter, index); 1242void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1243{
1244 adapter->hw_write_wx(adapter, index, &value, 4);
1245}
1246
1247void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1248{
1249 adapter->hw_read_wx(adapter, index, value, 4);
1250}
1251
1252/*
1253 * check memory access boundary.
1254 * used by test agent. support ddr access only for now
1255 */
1256static unsigned long
1257netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1258 unsigned long long addr, int size)
1259{
1260 if (!ADDR_IN_RANGE(addr,
1261 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1262 !ADDR_IN_RANGE(addr+size-1,
1263 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1264 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1265 return 0;
1266 }
828 1267
829 netxen_nic_pci_change_crbwindow(adapter, 0); 1268 return 1;
830 *value = readl(addr);
831 netxen_nic_pci_change_crbwindow(adapter, 1);
832} 1269}
833 1270
834static int netxen_pci_set_window_warning_count; 1271static int netxen_pci_set_window_warning_count;
835 1272
836static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter, 1273unsigned long
837 unsigned long long addr) 1274netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1275 unsigned long long addr)
838{ 1276{
839 void __iomem *offset; 1277 void __iomem *offset;
840 static int ddr_mn_window = -1;
841 static int qdr_sn_window = -1;
842 int window; 1278 int window;
1279 unsigned long long qdr_max;
843 uint8_t func = adapter->ahw.pci_func; 1280 uint8_t func = adapter->ahw.pci_func;
844 1281
1282 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1283 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1284 } else {
1285 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1286 }
1287
845 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 1288 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
846 /* DDR network side */ 1289 /* DDR network side */
847 addr -= NETXEN_ADDR_DDR_NET; 1290 addr -= NETXEN_ADDR_DDR_NET;
848 window = (addr >> 25) & 0x3ff; 1291 window = (addr >> 25) & 0x3ff;
849 if (ddr_mn_window != window) { 1292 if (adapter->ahw.ddr_mn_window != window) {
850 ddr_mn_window = window; 1293 adapter->ahw.ddr_mn_window = window;
851 offset = PCI_OFFSET_SECOND_RANGE(adapter, 1294 offset = PCI_OFFSET_SECOND_RANGE(adapter,
852 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func))); 1295 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
853 writel(window, offset); 1296 writel(window, offset);
@@ -862,14 +1305,12 @@ static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
862 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { 1305 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
863 addr -= NETXEN_ADDR_OCM1; 1306 addr -= NETXEN_ADDR_OCM1;
864 addr += NETXEN_PCI_OCM1; 1307 addr += NETXEN_PCI_OCM1;
865 } else 1308 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
866 if (ADDR_IN_RANGE
867 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P2)) {
868 /* QDR network side */ 1309 /* QDR network side */
869 addr -= NETXEN_ADDR_QDR_NET; 1310 addr -= NETXEN_ADDR_QDR_NET;
870 window = (addr >> 22) & 0x3f; 1311 window = (addr >> 22) & 0x3f;
871 if (qdr_sn_window != window) { 1312 if (adapter->ahw.qdr_sn_window != window) {
872 qdr_sn_window = window; 1313 adapter->ahw.qdr_sn_window = window;
873 offset = PCI_OFFSET_SECOND_RANGE(adapter, 1314 offset = PCI_OFFSET_SECOND_RANGE(adapter,
874 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func))); 1315 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
875 writel((window << 22), offset); 1316 writel((window << 22), offset);
@@ -888,11 +1329,711 @@ static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
888 printk("%s: Warning:netxen_nic_pci_set_window()" 1329 printk("%s: Warning:netxen_nic_pci_set_window()"
889 " Unknown address range!\n", 1330 " Unknown address range!\n",
890 netxen_nic_driver_name); 1331 netxen_nic_driver_name);
1332 addr = -1UL;
1333 }
1334 return addr;
1335}
1336
1337/*
1338 * Note : only 32-bit writes!
1339 */
1340int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1341 u64 off, u32 data)
1342{
1343 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1344 return 0;
1345}
1346
1347u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1348{
1349 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1350}
1351
1352void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1353 u64 off, u32 data)
1354{
1355 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1356}
1357
1358u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1359{
1360 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1361}
1362
1363unsigned long
1364netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1365 unsigned long long addr)
1366{
1367 int window;
1368 u32 win_read;
891 1369
1370 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1371 /* DDR network side */
1372 window = MN_WIN(addr);
1373 adapter->ahw.ddr_mn_window = window;
1374 adapter->hw_write_wx(adapter,
1375 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1376 &window, 4);
1377 adapter->hw_read_wx(adapter,
1378 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1379 &win_read, 4);
1380 if ((win_read << 17) != window) {
1381 printk(KERN_INFO "Written MNwin (0x%x) != "
1382 "Read MNwin (0x%x)\n", window, win_read);
1383 }
1384 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1385 } else if (ADDR_IN_RANGE(addr,
1386 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1387 if ((addr & 0x00ff800) == 0xff800) {
1388 printk("%s: QM access not handled.\n", __func__);
1389 addr = -1UL;
1390 }
1391
1392 window = OCM_WIN(addr);
1393 adapter->ahw.ddr_mn_window = window;
1394 adapter->hw_write_wx(adapter,
1395 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1396 &window, 4);
1397 adapter->hw_read_wx(adapter,
1398 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1399 &win_read, 4);
1400 if ((win_read >> 7) != window) {
1401 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1402 "Read OCMwin (0x%x)\n",
1403 __func__, window, win_read);
1404 }
1405 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1406
1407 } else if (ADDR_IN_RANGE(addr,
1408 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1409 /* QDR network side */
1410 window = MS_WIN(addr);
1411 adapter->ahw.qdr_sn_window = window;
1412 adapter->hw_write_wx(adapter,
1413 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1414 &window, 4);
1415 adapter->hw_read_wx(adapter,
1416 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1417 &win_read, 4);
1418 if (win_read != window) {
1419 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1420 "Read MSwin (0x%x)\n",
1421 __func__, window, win_read);
1422 }
1423 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1424
1425 } else {
1426 /*
1427 * peg gdb frequently accesses memory that doesn't exist,
1428 * this limits the chit chat so debugging isn't slowed down.
1429 */
1430 if ((netxen_pci_set_window_warning_count++ < 8)
1431 || (netxen_pci_set_window_warning_count%64 == 0)) {
1432 printk("%s: Warning:%s Unknown address range!\n",
1433 __func__, netxen_nic_driver_name);
1434}
1435 addr = -1UL;
892 } 1436 }
893 return addr; 1437 return addr;
894} 1438}
895 1439
1440static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1441 unsigned long long addr)
1442{
1443 int window;
1444 unsigned long long qdr_max;
1445
1446 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1447 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1448 else
1449 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1450
1451 if (ADDR_IN_RANGE(addr,
1452 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1453 /* DDR network side */
1454 BUG(); /* MN access can not come here */
1455 } else if (ADDR_IN_RANGE(addr,
1456 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1457 return 1;
1458 } else if (ADDR_IN_RANGE(addr,
1459 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1460 return 1;
1461 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1462 /* QDR network side */
1463 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1464 if (adapter->ahw.qdr_sn_window == window)
1465 return 1;
1466 }
1467
1468 return 0;
1469}
1470
1471static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1472 u64 off, void *data, int size)
1473{
1474 unsigned long flags;
1475 void *addr;
1476 int ret = 0;
1477 u64 start;
1478 uint8_t *mem_ptr = NULL;
1479 unsigned long mem_base;
1480 unsigned long mem_page;
1481
1482 write_lock_irqsave(&adapter->adapter_lock, flags);
1483
1484 /*
1485 * If attempting to access unknown address or straddle hw windows,
1486 * do not access.
1487 */
1488 start = adapter->pci_set_window(adapter, off);
1489 if ((start == -1UL) ||
1490 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1491 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1492 printk(KERN_ERR "%s out of bound pci memory access. "
1493 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1494 return -1;
1495 }
1496
1497 addr = (void *)(pci_base_offset(adapter, start));
1498 if (!addr) {
1499 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1500 mem_base = pci_resource_start(adapter->pdev, 0);
1501 mem_page = start & PAGE_MASK;
1502 /* Map two pages whenever user tries to access addresses in two
1503 consecutive pages.
1504 */
1505 if (mem_page != ((start + size - 1) & PAGE_MASK))
1506 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1507 else
1508 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1509 if (mem_ptr == 0UL) {
1510 *(uint8_t *)data = 0;
1511 return -1;
1512 }
1513 addr = mem_ptr;
1514 addr += start & (PAGE_SIZE - 1);
1515 write_lock_irqsave(&adapter->adapter_lock, flags);
1516 }
1517
1518 switch (size) {
1519 case 1:
1520 *(uint8_t *)data = readb(addr);
1521 break;
1522 case 2:
1523 *(uint16_t *)data = readw(addr);
1524 break;
1525 case 4:
1526 *(uint32_t *)data = readl(addr);
1527 break;
1528 case 8:
1529 *(uint64_t *)data = readq(addr);
1530 break;
1531 default:
1532 ret = -1;
1533 break;
1534 }
1535 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1536 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1537
1538 if (mem_ptr)
1539 iounmap(mem_ptr);
1540 return ret;
1541}
1542
1543static int
1544netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1545 void *data, int size)
1546{
1547 unsigned long flags;
1548 void *addr;
1549 int ret = 0;
1550 u64 start;
1551 uint8_t *mem_ptr = NULL;
1552 unsigned long mem_base;
1553 unsigned long mem_page;
1554
1555 write_lock_irqsave(&adapter->adapter_lock, flags);
1556
1557 /*
1558 * If attempting to access unknown address or straddle hw windows,
1559 * do not access.
1560 */
1561 start = adapter->pci_set_window(adapter, off);
1562 if ((start == -1UL) ||
1563 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1564 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1565 printk(KERN_ERR "%s out of bound pci memory access. "
1566 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1567 return -1;
1568 }
1569
1570 addr = (void *)(pci_base_offset(adapter, start));
1571 if (!addr) {
1572 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1573 mem_base = pci_resource_start(adapter->pdev, 0);
1574 mem_page = start & PAGE_MASK;
1575 /* Map two pages whenever user tries to access addresses in two
1576 * consecutive pages.
1577 */
1578 if (mem_page != ((start + size - 1) & PAGE_MASK))
1579 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1580 else
1581 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1582 if (mem_ptr == 0UL)
1583 return -1;
1584 addr = mem_ptr;
1585 addr += start & (PAGE_SIZE - 1);
1586 write_lock_irqsave(&adapter->adapter_lock, flags);
1587 }
1588
1589 switch (size) {
1590 case 1:
1591 writeb(*(uint8_t *)data, addr);
1592 break;
1593 case 2:
1594 writew(*(uint16_t *)data, addr);
1595 break;
1596 case 4:
1597 writel(*(uint32_t *)data, addr);
1598 break;
1599 case 8:
1600 writeq(*(uint64_t *)data, addr);
1601 break;
1602 default:
1603 ret = -1;
1604 break;
1605 }
1606 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1607 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1608 *(unsigned long long *)data, start);
1609 if (mem_ptr)
1610 iounmap(mem_ptr);
1611 return ret;
1612}
1613
1614#define MAX_CTL_CHECK 1000
1615
1616int
1617netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1618 u64 off, void *data, int size)
1619{
1620 unsigned long flags, mem_crb;
1621 int i, j, ret = 0, loop, sz[2], off0;
1622 uint32_t temp;
1623 uint64_t off8, tmpw, word[2] = {0, 0};
1624
1625 /*
1626 * If not MN, go check for MS or invalid.
1627 */
1628 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1629 return netxen_nic_pci_mem_write_direct(adapter,
1630 off, data, size);
1631
1632 off8 = off & 0xfffffff8;
1633 off0 = off & 0x7;
1634 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1635 sz[1] = size - sz[0];
1636 loop = ((off0 + size - 1) >> 3) + 1;
1637 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1638
1639 if ((size != 8) || (off0 != 0)) {
1640 for (i = 0; i < loop; i++) {
1641 if (adapter->pci_mem_read(adapter,
1642 off8 + (i << 3), &word[i], 8))
1643 return -1;
1644 }
1645 }
1646
1647 switch (size) {
1648 case 1:
1649 tmpw = *((uint8_t *)data);
1650 break;
1651 case 2:
1652 tmpw = *((uint16_t *)data);
1653 break;
1654 case 4:
1655 tmpw = *((uint32_t *)data);
1656 break;
1657 case 8:
1658 default:
1659 tmpw = *((uint64_t *)data);
1660 break;
1661 }
1662 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1663 word[0] |= tmpw << (off0 * 8);
1664
1665 if (loop == 2) {
1666 word[1] &= ~(~0ULL << (sz[1] * 8));
1667 word[1] |= tmpw >> (sz[0] * 8);
1668 }
1669
1670 write_lock_irqsave(&adapter->adapter_lock, flags);
1671 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1672
1673 for (i = 0; i < loop; i++) {
1674 writel((uint32_t)(off8 + (i << 3)),
1675 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1676 writel(0,
1677 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1678 writel(word[i] & 0xffffffff,
1679 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1680 writel((word[i] >> 32) & 0xffffffff,
1681 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1682 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1683 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1684 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1685 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1686
1687 for (j = 0; j < MAX_CTL_CHECK; j++) {
1688 temp = readl(
1689 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1690 if ((temp & MIU_TA_CTL_BUSY) == 0)
1691 break;
1692 }
1693
1694 if (j >= MAX_CTL_CHECK) {
1695 printk("%s: %s Fail to write through agent\n",
1696 __func__, netxen_nic_driver_name);
1697 ret = -1;
1698 break;
1699 }
1700 }
1701
1702 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1703 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1704 return ret;
1705}
1706
1707int
1708netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1709 u64 off, void *data, int size)
1710{
1711 unsigned long flags, mem_crb;
1712 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1713 uint32_t temp;
1714 uint64_t off8, val, word[2] = {0, 0};
1715
1716
1717 /*
1718 * If not MN, go check for MS or invalid.
1719 */
1720 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1721 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1722
1723 off8 = off & 0xfffffff8;
1724 off0[0] = off & 0x7;
1725 off0[1] = 0;
1726 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1727 sz[1] = size - sz[0];
1728 loop = ((off0[0] + size - 1) >> 3) + 1;
1729 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1730
1731 write_lock_irqsave(&adapter->adapter_lock, flags);
1732 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1733
1734 for (i = 0; i < loop; i++) {
1735 writel((uint32_t)(off8 + (i << 3)),
1736 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1737 writel(0,
1738 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1739 writel(MIU_TA_CTL_ENABLE,
1740 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1741 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1742 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1743
1744 for (j = 0; j < MAX_CTL_CHECK; j++) {
1745 temp = readl(
1746 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1747 if ((temp & MIU_TA_CTL_BUSY) == 0)
1748 break;
1749 }
1750
1751 if (j >= MAX_CTL_CHECK) {
1752 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1753 __func__, netxen_nic_driver_name);
1754 break;
1755 }
1756
1757 start = off0[i] >> 2;
1758 end = (off0[i] + sz[i] - 1) >> 2;
1759 for (k = start; k <= end; k++) {
1760 word[i] |= ((uint64_t) readl(
1761 (void *)(mem_crb +
1762 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1763 }
1764 }
1765
1766 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1767 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1768
1769 if (j >= MAX_CTL_CHECK)
1770 return -1;
1771
1772 if (sz[0] == 8) {
1773 val = word[0];
1774 } else {
1775 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1776 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1777 }
1778
1779 switch (size) {
1780 case 1:
1781 *(uint8_t *)data = val;
1782 break;
1783 case 2:
1784 *(uint16_t *)data = val;
1785 break;
1786 case 4:
1787 *(uint32_t *)data = val;
1788 break;
1789 case 8:
1790 *(uint64_t *)data = val;
1791 break;
1792 }
1793 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1794 return 0;
1795}
1796
1797int
1798netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1799 u64 off, void *data, int size)
1800{
1801 int i, j, ret = 0, loop, sz[2], off0;
1802 uint32_t temp;
1803 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1804
1805 /*
1806 * If not MN, go check for MS or invalid.
1807 */
1808 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1809 mem_crb = NETXEN_CRB_QDR_NET;
1810 else {
1811 mem_crb = NETXEN_CRB_DDR_NET;
1812 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1813 return netxen_nic_pci_mem_write_direct(adapter,
1814 off, data, size);
1815 }
1816
1817 off8 = off & 0xfffffff8;
1818 off0 = off & 0x7;
1819 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1820 sz[1] = size - sz[0];
1821 loop = ((off0 + size - 1) >> 3) + 1;
1822
1823 if ((size != 8) || (off0 != 0)) {
1824 for (i = 0; i < loop; i++) {
1825 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1826 &word[i], 8))
1827 return -1;
1828 }
1829 }
1830
1831 switch (size) {
1832 case 1:
1833 tmpw = *((uint8_t *)data);
1834 break;
1835 case 2:
1836 tmpw = *((uint16_t *)data);
1837 break;
1838 case 4:
1839 tmpw = *((uint32_t *)data);
1840 break;
1841 case 8:
1842 default:
1843 tmpw = *((uint64_t *)data);
1844 break;
1845 }
1846
1847 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1848 word[0] |= tmpw << (off0 * 8);
1849
1850 if (loop == 2) {
1851 word[1] &= ~(~0ULL << (sz[1] * 8));
1852 word[1] |= tmpw >> (sz[0] * 8);
1853 }
1854
1855 /*
1856 * don't lock here - write_wx gets the lock if each time
1857 * write_lock_irqsave(&adapter->adapter_lock, flags);
1858 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1859 */
1860
1861 for (i = 0; i < loop; i++) {
1862 temp = off8 + (i << 3);
1863 adapter->hw_write_wx(adapter,
1864 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1865 temp = 0;
1866 adapter->hw_write_wx(adapter,
1867 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1868 temp = word[i] & 0xffffffff;
1869 adapter->hw_write_wx(adapter,
1870 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1871 temp = (word[i] >> 32) & 0xffffffff;
1872 adapter->hw_write_wx(adapter,
1873 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1874 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1875 adapter->hw_write_wx(adapter,
1876 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1877 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1878 adapter->hw_write_wx(adapter,
1879 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1880
1881 for (j = 0; j < MAX_CTL_CHECK; j++) {
1882 adapter->hw_read_wx(adapter,
1883 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1884 if ((temp & MIU_TA_CTL_BUSY) == 0)
1885 break;
1886 }
1887
1888 if (j >= MAX_CTL_CHECK) {
1889 printk(KERN_ERR "%s: Fail to write through agent\n",
1890 netxen_nic_driver_name);
1891 ret = -1;
1892 break;
1893 }
1894 }
1895
1896 /*
1897 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1898 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1899 */
1900 return ret;
1901}
1902
1903int
1904netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1905 u64 off, void *data, int size)
1906{
1907 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1908 uint32_t temp;
1909 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1910
1911 /*
1912 * If not MN, go check for MS or invalid.
1913 */
1914
1915 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1916 mem_crb = NETXEN_CRB_QDR_NET;
1917 else {
1918 mem_crb = NETXEN_CRB_DDR_NET;
1919 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1920 return netxen_nic_pci_mem_read_direct(adapter,
1921 off, data, size);
1922 }
1923
1924 off8 = off & 0xfffffff8;
1925 off0[0] = off & 0x7;
1926 off0[1] = 0;
1927 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1928 sz[1] = size - sz[0];
1929 loop = ((off0[0] + size - 1) >> 3) + 1;
1930
1931 /*
1932 * don't lock here - write_wx gets the lock if each time
1933 * write_lock_irqsave(&adapter->adapter_lock, flags);
1934 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1935 */
1936
1937 for (i = 0; i < loop; i++) {
1938 temp = off8 + (i << 3);
1939 adapter->hw_write_wx(adapter,
1940 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1941 temp = 0;
1942 adapter->hw_write_wx(adapter,
1943 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1944 temp = MIU_TA_CTL_ENABLE;
1945 adapter->hw_write_wx(adapter,
1946 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1947 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1948 adapter->hw_write_wx(adapter,
1949 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1950
1951 for (j = 0; j < MAX_CTL_CHECK; j++) {
1952 adapter->hw_read_wx(adapter,
1953 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1954 if ((temp & MIU_TA_CTL_BUSY) == 0)
1955 break;
1956 }
1957
1958 if (j >= MAX_CTL_CHECK) {
1959 printk(KERN_ERR "%s: Fail to read through agent\n",
1960 netxen_nic_driver_name);
1961 break;
1962 }
1963
1964 start = off0[i] >> 2;
1965 end = (off0[i] + sz[i] - 1) >> 2;
1966 for (k = start; k <= end; k++) {
1967 adapter->hw_read_wx(adapter,
1968 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1969 word[i] |= ((uint64_t)temp << (32 * k));
1970 }
1971 }
1972
1973 /*
1974 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1975 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1976 */
1977
1978 if (j >= MAX_CTL_CHECK)
1979 return -1;
1980
1981 if (sz[0] == 8) {
1982 val = word[0];
1983 } else {
1984 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1985 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1986 }
1987
1988 switch (size) {
1989 case 1:
1990 *(uint8_t *)data = val;
1991 break;
1992 case 2:
1993 *(uint16_t *)data = val;
1994 break;
1995 case 4:
1996 *(uint32_t *)data = val;
1997 break;
1998 case 8:
1999 *(uint64_t *)data = val;
2000 break;
2001 }
2002 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
2003 return 0;
2004}
2005
2006/*
2007 * Note : only 32-bit writes!
2008 */
2009int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2010 u64 off, u32 data)
2011{
2012 adapter->hw_write_wx(adapter, off, &data, 4);
2013
2014 return 0;
2015}
2016
2017u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2018{
2019 u32 temp;
2020 adapter->hw_read_wx(adapter, off, &temp, 4);
2021 return temp;
2022}
2023
2024void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
2025 u64 off, u32 data)
2026{
2027 adapter->hw_write_wx(adapter, off, &data, 4);
2028}
2029
2030u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2031{
2032 u32 temp;
2033 adapter->hw_read_wx(adapter, off, &temp, 4);
2034 return temp;
2035}
2036
896#if 0 2037#if 0
897int 2038int
898netxen_nic_erase_pxe(struct netxen_adapter *adapter) 2039netxen_nic_erase_pxe(struct netxen_adapter *adapter)
@@ -1006,19 +2147,10 @@ void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
1006} 2147}
1007 2148
1008void 2149void
1009netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off, 2150netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1010 int data) 2151 unsigned long off, int data)
1011{ 2152{
1012 void __iomem *addr; 2153 adapter->hw_write_wx(adapter, off, &data, 4);
1013
1014 if (ADDR_IN_WINDOW1(off)) {
1015 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1016 } else {
1017 netxen_nic_pci_change_crbwindow(adapter, 0);
1018 addr = pci_base_offset(adapter, off);
1019 writel(data, addr);
1020 netxen_nic_pci_change_crbwindow(adapter, 1);
1021 }
1022} 2154}
1023 2155
1024void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) 2156void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
@@ -1105,12 +2237,9 @@ void netxen_nic_flash_print(struct netxen_adapter *adapter)
1105 addr += sizeof(u32); 2237 addr += sizeof(u32);
1106 } 2238 }
1107 2239
1108 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter, 2240 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
1109 NETXEN_FW_VERSION_MAJOR)); 2241 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
1110 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter, 2242 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
1111 NETXEN_FW_VERSION_MINOR));
1112 fw_build =
1113 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1114 2243
1115 if (adapter->portnum == 0) { 2244 if (adapter->portnum == 0) {
1116 get_brd_name_by_type(board_info->board_type, brd_name); 2245 get_brd_name_by_type(board_info->board_type, brd_name);
diff --git a/drivers/net/netxen/netxen_nic_hw.h b/drivers/net/netxen/netxen_nic_hw.h
index 90dd05796438..b8e0030f03d7 100644
--- a/drivers/net/netxen/netxen_nic_hw.h
+++ b/drivers/net/netxen/netxen_nic_hw.h
@@ -82,19 +82,9 @@ struct netxen_adapter;
82 82
83#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20) 83#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20)
84 84
85#define NETXEN_NIC_LOCKED_READ_REG(X, Y) \
86 addr = pci_base_offset(adapter, X); \
87 *(u32 *)Y = readl((void __iomem*) addr);
88
89struct netxen_port; 85struct netxen_port;
90void netxen_nic_set_link_parameters(struct netxen_adapter *adapter); 86void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
91void netxen_nic_flash_print(struct netxen_adapter *adapter); 87void netxen_nic_flash_print(struct netxen_adapter *adapter);
92int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off,
93 void *data, int len);
94void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
95 unsigned long off, int data);
96int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off,
97 void *data, int len);
98 88
99typedef u8 netxen_ethernet_macaddr_t[6]; 89typedef u8 netxen_ethernet_macaddr_t[6];
100 90
@@ -503,4 +493,15 @@ int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter);
503 493
504int netxen_niu_disable_xg_port(struct netxen_adapter *adapter); 494int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
505 495
496typedef struct {
497 unsigned valid;
498 unsigned start_128M;
499 unsigned end_128M;
500 unsigned start_2M;
501} crb_128M_2M_sub_block_map_t;
502
503typedef struct {
504 crb_128M_2M_sub_block_map_t sub_block[16];
505} crb_128M_2M_block_map_t;
506
506#endif /* __NETXEN_NIC_HW_H_ */ 507#endif /* __NETXEN_NIC_HW_H_ */
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
index dfde59082096..7323cd7b544a 100644
--- a/drivers/net/netxen/netxen_nic_init.c
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -124,7 +124,7 @@ int netxen_init_firmware(struct netxen_adapter *adapter)
124 u32 state = 0, loops = 0, err = 0; 124 u32 state = 0, loops = 0, err = 0;
125 125
126 /* Window 1 call */ 126 /* Window 1 call */
127 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)); 127 state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
128 128
129 if (state == PHAN_INITIALIZE_ACK) 129 if (state == PHAN_INITIALIZE_ACK)
130 return 0; 130 return 0;
@@ -132,7 +132,7 @@ int netxen_init_firmware(struct netxen_adapter *adapter)
132 while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) { 132 while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
133 udelay(100); 133 udelay(100);
134 /* Window 1 call */ 134 /* Window 1 call */
135 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)); 135 state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
136 136
137 loops++; 137 loops++;
138 } 138 }
@@ -143,14 +143,14 @@ int netxen_init_firmware(struct netxen_adapter *adapter)
143 return err; 143 return err;
144 } 144 }
145 /* Window 1 call */ 145 /* Window 1 call */
146 writel(INTR_SCHEME_PERPORT, 146 adapter->pci_write_normalize(adapter,
147 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_HOST)); 147 CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
148 writel(MSI_MODE_MULTIFUNC, 148 adapter->pci_write_normalize(adapter,
149 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_HOST)); 149 CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
150 writel(MPORT_MULTI_FUNCTION_MODE, 150 adapter->pci_write_normalize(adapter,
151 NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE)); 151 CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
152 writel(PHAN_INITIALIZE_ACK, 152 adapter->pci_write_normalize(adapter,
153 NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE)); 153 CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
154 154
155 return err; 155 return err;
156} 156}
@@ -811,7 +811,7 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
811 buf[i].data = NETXEN_NIC_XDMA_RESET; 811 buf[i].data = NETXEN_NIC_XDMA_RESET;
812 } 812 }
813 813
814 netxen_nic_hw_write_wx(adapter, off, &buf[i].data, 4); 814 adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
815 815
816 if (init_delay == 1) { 816 if (init_delay == 1) {
817 msleep(1000); 817 msleep(1000);
@@ -824,7 +824,7 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
824 /* disable_peg_cache_all */ 824 /* disable_peg_cache_all */
825 825
826 /* unreset_net_cache */ 826 /* unreset_net_cache */
827 netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val, 827 adapter->hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
828 4); 828 4);
829 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 829 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
830 (val & 0xffffff0f)); 830 (val & 0xffffff0f));
@@ -884,8 +884,8 @@ int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
884 hi = (addr >> 32) & 0xffffffff; 884 hi = (addr >> 32) & 0xffffffff;
885 lo = addr & 0xffffffff; 885 lo = addr & 0xffffffff;
886 886
887 writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI)); 887 adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
888 writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO)); 888 adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
889 889
890 return 0; 890 return 0;
891} 891}
@@ -924,10 +924,10 @@ int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
924 924
925 if (!pegtune_val) { 925 if (!pegtune_val) {
926 do { 926 do {
927 val = readl(NETXEN_CRB_NORMALIZE 927 val = adapter->pci_read_normalize(adapter,
928 (adapter, CRB_CMDPEG_STATE)); 928 CRB_CMDPEG_STATE);
929 pegtune_val = readl(NETXEN_CRB_NORMALIZE 929 pegtune_val = adapter->pci_read_normalize(adapter,
930 (adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE)); 930 NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
931 931
932 if (val == PHAN_INITIALIZE_COMPLETE || 932 if (val == PHAN_INITIALIZE_COMPLETE ||
933 val == PHAN_INITIALIZE_ACK) 933 val == PHAN_INITIALIZE_ACK)
@@ -951,7 +951,7 @@ static int netxen_nic_check_temp(struct netxen_adapter *adapter)
951 uint32_t temp, temp_state, temp_val; 951 uint32_t temp, temp_state, temp_val;
952 int rv = 0; 952 int rv = 0;
953 953
954 temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE)); 954 temp = adapter->pci_read_normalize(adapter, CRB_TEMP_STATE);
955 955
956 temp_state = nx_get_temp_state(temp); 956 temp_state = nx_get_temp_state(temp);
957 temp_val = nx_get_temp_val(temp); 957 temp_val = nx_get_temp_val(temp);
@@ -1119,8 +1119,8 @@ u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
1119 recv_ctx->status_rx_consumer = consumer; 1119 recv_ctx->status_rx_consumer = consumer;
1120 1120
1121 /* Window = 1 */ 1121 /* Window = 1 */
1122 writel(consumer, NETXEN_CRB_NORMALIZE(adapter, 1122 adapter->pci_write_normalize(adapter,
1123 recv_ctx->crb_sts_consumer)); 1123 recv_ctx->crb_sts_consumer, consumer);
1124 } 1124 }
1125 1125
1126 return count; 1126 return count;
@@ -1264,9 +1264,9 @@ void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
1264 rcv_desc->begin_alloc = index; 1264 rcv_desc->begin_alloc = index;
1265 rcv_desc->producer = producer; 1265 rcv_desc->producer = producer;
1266 /* Window = 1 */ 1266 /* Window = 1 */
1267 writel((producer - 1) & (rcv_desc->max_rx_desc_count - 1), 1267 adapter->pci_write_normalize(adapter,
1268 NETXEN_CRB_NORMALIZE(adapter, 1268 rcv_desc->crb_rcv_producer,
1269 rcv_desc->crb_rcv_producer)); 1269 (producer-1) & (rcv_desc->max_rx_desc_count-1));
1270 /* 1270 /*
1271 * Write a doorbell msg to tell phanmon of change in 1271 * Write a doorbell msg to tell phanmon of change in
1272 * receive ring producer 1272 * receive ring producer
@@ -1344,9 +1344,9 @@ static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1344 rcv_desc->begin_alloc = index; 1344 rcv_desc->begin_alloc = index;
1345 rcv_desc->producer = producer; 1345 rcv_desc->producer = producer;
1346 /* Window = 1 */ 1346 /* Window = 1 */
1347 writel((producer - 1) & (rcv_desc->max_rx_desc_count - 1), 1347 adapter->pci_write_normalize(adapter,
1348 NETXEN_CRB_NORMALIZE(adapter, 1348 rcv_desc->crb_rcv_producer,
1349 rcv_desc->crb_rcv_producer)); 1349 (producer-1) & (rcv_desc->max_rx_desc_count-1));
1350 wmb(); 1350 wmb();
1351 } 1351 }
1352} 1352}
diff --git a/drivers/net/netxen/netxen_nic_isr.c b/drivers/net/netxen/netxen_nic_isr.c
index 96cec41f9019..104c287d77ac 100644
--- a/drivers/net/netxen/netxen_nic_isr.c
+++ b/drivers/net/netxen/netxen_nic_isr.c
@@ -144,7 +144,7 @@ static void netxen_nic_isr_other(struct netxen_adapter *adapter)
144 u32 val, linkup, qg_linksup; 144 u32 val, linkup, qg_linksup;
145 145
146 /* verify the offset */ 146 /* verify the offset */
147 val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE)); 147 val = adapter->pci_read_normalize(adapter, CRB_XG_STATE);
148 val = val >> adapter->physical_port; 148 val = val >> adapter->physical_port;
149 if (val == adapter->ahw.qg_linksup) 149 if (val == adapter->ahw.qg_linksup)
150 return; 150 return;
@@ -198,7 +198,7 @@ void netxen_nic_xgbe_handle_phy_intr(struct netxen_adapter *adapter)
198 u32 val; 198 u32 val;
199 199
200 /* WINDOW = 1 */ 200 /* WINDOW = 1 */
201 val = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_XG_STATE)); 201 val = adapter->pci_read_normalize(adapter, CRB_XG_STATE);
202 val >>= (adapter->physical_port * 8); 202 val >>= (adapter->physical_port * 8);
203 val &= 0xff; 203 val &= 0xff;
204 204
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index 192a22f89570..72d9f48b80dc 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -114,11 +114,12 @@ static uint32_t crb_cmd_producer[4] = {
114 CRB_CMD_PRODUCER_OFFSET_2, CRB_CMD_PRODUCER_OFFSET_3 114 CRB_CMD_PRODUCER_OFFSET_2, CRB_CMD_PRODUCER_OFFSET_3
115}; 115};
116 116
117static void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, 117static inline void
118 uint32_t crb_producer) 118netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
119 uint32_t crb_producer)
119{ 120{
120 writel(crb_producer, NETXEN_CRB_NORMALIZE(adapter, 121 adapter->pci_write_normalize(adapter,
121 adapter->crb_addr_cmd_producer)); 122 adapter->crb_addr_cmd_producer, crb_producer);
122} 123}
123 124
124static uint32_t crb_cmd_consumer[4] = { 125static uint32_t crb_cmd_consumer[4] = {
@@ -126,11 +127,12 @@ static uint32_t crb_cmd_consumer[4] = {
126 CRB_CMD_CONSUMER_OFFSET_2, CRB_CMD_CONSUMER_OFFSET_3 127 CRB_CMD_CONSUMER_OFFSET_2, CRB_CMD_CONSUMER_OFFSET_3
127}; 128};
128 129
129static void netxen_nic_update_cmd_consumer(struct netxen_adapter *adapter, 130static inline void
130 u32 crb_consumer) 131netxen_nic_update_cmd_consumer(struct netxen_adapter *adapter,
132 u32 crb_consumer)
131{ 133{
132 writel(crb_consumer, NETXEN_CRB_NORMALIZE(adapter, 134 adapter->pci_write_normalize(adapter,
133 adapter->crb_addr_cmd_consumer)); 135 adapter->crb_addr_cmd_consumer, crb_consumer);
134} 136}
135 137
136static uint32_t msi_tgt_status[4] = { 138static uint32_t msi_tgt_status[4] = {
@@ -151,17 +153,18 @@ static void netxen_nic_disable_int(struct netxen_adapter *adapter)
151 int pci_fn = adapter->ahw.pci_func; 153 int pci_fn = adapter->ahw.pci_func;
152 154
153 if (adapter->msi_mode != MSI_MODE_MULTIFUNC) 155 if (adapter->msi_mode != MSI_MODE_MULTIFUNC)
154 writel(0x0, NETXEN_CRB_NORMALIZE(adapter, sw_int_mask[port])); 156 adapter->pci_write_normalize(adapter, sw_int_mask[port], 0);
155 157
156 if (adapter->intr_scheme != -1 && 158 if (adapter->intr_scheme != -1 &&
157 adapter->intr_scheme != INTR_SCHEME_PERPORT) 159 adapter->intr_scheme != INTR_SCHEME_PERPORT)
158 writel(mask,PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)); 160 adapter->pci_write_immediate(adapter, ISR_INT_MASK, mask);
159 161
160 if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) { 162 if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
161 do { 163 do {
162 writel(0xffffffff, 164 adapter->pci_write_immediate(adapter,
163 PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_TARGET_STATUS)); 165 ISR_INT_TARGET_STATUS, 0xffffffff);
164 mask = readl(pci_base_offset(adapter, ISR_INT_VECTOR)); 166 mask = adapter->pci_read_immediate(adapter,
167 ISR_INT_VECTOR);
165 if (!(mask & 0x80)) 168 if (!(mask & 0x80))
166 break; 169 break;
167 udelay(10); 170 udelay(10);
@@ -173,8 +176,8 @@ static void netxen_nic_disable_int(struct netxen_adapter *adapter)
173 } 176 }
174 } else { 177 } else {
175 if (adapter->msi_mode == MSI_MODE_MULTIFUNC) { 178 if (adapter->msi_mode == MSI_MODE_MULTIFUNC) {
176 writel(0xffffffff, PCI_OFFSET_SECOND_RANGE(adapter, 179 adapter->pci_write_immediate(adapter,
177 msi_tgt_status[pci_fn])); 180 msi_tgt_status[pci_fn], 0xffffffff);
178 } 181 }
179 } 182 }
180} 183}
@@ -200,19 +203,20 @@ static void netxen_nic_enable_int(struct netxen_adapter *adapter)
200 break; 203 break;
201 } 204 }
202 205
203 writel(mask, PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_MASK)); 206 adapter->pci_write_immediate(adapter, ISR_INT_MASK, mask);
204 } 207 }
205 208
206 writel(0x1, NETXEN_CRB_NORMALIZE(adapter, sw_int_mask[port])); 209 adapter->pci_write_normalize(adapter, sw_int_mask[port], 0x1);
207 210
208 if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) { 211 if (!(adapter->flags & NETXEN_NIC_MSI_ENABLED)) {
209 mask = 0xbff; 212 mask = 0xbff;
210 if (adapter->intr_scheme != -1 && 213 if (adapter->intr_scheme != -1 &&
211 adapter->intr_scheme != INTR_SCHEME_PERPORT) { 214 adapter->intr_scheme != INTR_SCHEME_PERPORT) {
212 writel(0X0, NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR)); 215 adapter->pci_write_normalize(adapter,
216 CRB_INT_VECTOR, 0);
213 } 217 }
214 writel(mask, 218 adapter->pci_write_immediate(adapter,
215 PCI_OFFSET_SECOND_RANGE(adapter, ISR_INT_TARGET_MASK)); 219 ISR_INT_TARGET_MASK, mask);
216 } 220 }
217 221
218 DPRINTK(1, INFO, "Done with enable Int\n"); 222 DPRINTK(1, INFO, "Done with enable Int\n");
@@ -243,7 +247,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
243 247
244 248
245 u8 __iomem *db_ptr = NULL; 249 u8 __iomem *db_ptr = NULL;
246 unsigned long mem_base, mem_len, db_base, db_len; 250 unsigned long mem_base, mem_len, db_base, db_len, pci_len0;
247 int pci_using_dac, i = 0, err; 251 int pci_using_dac, i = 0, err;
248 int ring; 252 int ring;
249 struct netxen_recv_context *recv_ctx = NULL; 253 struct netxen_recv_context *recv_ctx = NULL;
@@ -300,10 +304,24 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
300 adapter = netdev->priv; 304 adapter = netdev->priv;
301 305
302 adapter->ahw.pci_func = pci_func_id; 306 adapter->ahw.pci_func = pci_func_id;
307 rwlock_init(&adapter->adapter_lock);
308 adapter->ahw.qdr_sn_window = -1;
309 adapter->ahw.ddr_mn_window = -1;
303 310
304 /* remap phys address */ 311 /* remap phys address */
305 mem_base = pci_resource_start(pdev, 0); /* 0 is for BAR 0 */ 312 mem_base = pci_resource_start(pdev, 0); /* 0 is for BAR 0 */
306 mem_len = pci_resource_len(pdev, 0); 313 mem_len = pci_resource_len(pdev, 0);
314 pci_len0 = 0;
315
316 adapter->hw_write_wx = netxen_nic_hw_write_wx_128M;
317 adapter->hw_read_wx = netxen_nic_hw_read_wx_128M;
318 adapter->pci_read_immediate = netxen_nic_pci_read_immediate_128M;
319 adapter->pci_write_immediate = netxen_nic_pci_write_immediate_128M;
320 adapter->pci_read_normalize = netxen_nic_pci_read_normalize_128M;
321 adapter->pci_write_normalize = netxen_nic_pci_write_normalize_128M;
322 adapter->pci_set_window = netxen_nic_pci_set_window_128M;
323 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M;
324 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M;
307 325
308 /* 128 Meg of memory */ 326 /* 128 Meg of memory */
309 if (mem_len == NETXEN_PCI_128MB_SIZE) { 327 if (mem_len == NETXEN_PCI_128MB_SIZE) {
@@ -320,21 +338,42 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
320 SECOND_PAGE_GROUP_START, THIRD_PAGE_GROUP_SIZE); 338 SECOND_PAGE_GROUP_START, THIRD_PAGE_GROUP_SIZE);
321 first_page_group_start = 0; 339 first_page_group_start = 0;
322 first_page_group_end = 0; 340 first_page_group_end = 0;
341 } else if (mem_len == NETXEN_PCI_2MB_SIZE) {
342 adapter->hw_write_wx = netxen_nic_hw_write_wx_2M;
343 adapter->hw_read_wx = netxen_nic_hw_read_wx_2M;
344 adapter->pci_read_immediate = netxen_nic_pci_read_immediate_2M;
345 adapter->pci_write_immediate =
346 netxen_nic_pci_write_immediate_2M;
347 adapter->pci_read_normalize = netxen_nic_pci_read_normalize_2M;
348 adapter->pci_write_normalize =
349 netxen_nic_pci_write_normalize_2M;
350 adapter->pci_set_window = netxen_nic_pci_set_window_2M;
351 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M;
352 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M;
353
354 mem_ptr0 = ioremap(mem_base, mem_len);
355 pci_len0 = mem_len;
356 first_page_group_start = 0;
357 first_page_group_end = 0;
358
359 adapter->ahw.ddr_mn_window = 0;
360 adapter->ahw.qdr_sn_window = 0;
361
362 adapter->ahw.mn_win_crb = 0x100000 + PCIX_MN_WINDOW +
363 (pci_func_id * 0x20);
364 adapter->ahw.ms_win_crb = 0x100000 + PCIX_SN_WINDOW;
365 if (pci_func_id < 4)
366 adapter->ahw.ms_win_crb += (pci_func_id * 0x20);
367 else
368 adapter->ahw.ms_win_crb +=
369 0xA0 + ((pci_func_id - 4) * 0x10);
323 } else { 370 } else {
324 err = -EIO; 371 err = -EIO;
325 goto err_out_free_netdev; 372 goto err_out_free_netdev;
326 } 373 }
327 374
328 if ((!mem_ptr0 && mem_len == NETXEN_PCI_128MB_SIZE) || 375 dev_info(&pdev->dev, "%dMB memory map\n", (int)(mem_len>>20));
329 !mem_ptr1 || !mem_ptr2) {
330 DPRINTK(ERR,
331 "Cannot remap adapter memory aborting.:"
332 "0 -> %p, 1 -> %p, 2 -> %p\n",
333 mem_ptr0, mem_ptr1, mem_ptr2);
334 376
335 err = -EIO;
336 goto err_out_iounmap;
337 }
338 db_base = pci_resource_start(pdev, 4); /* doorbell is on bar 4 */ 377 db_base = pci_resource_start(pdev, 4); /* doorbell is on bar 4 */
339 db_len = pci_resource_len(pdev, 4); 378 db_len = pci_resource_len(pdev, 4);
340 379
@@ -357,6 +396,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
357 DPRINTK(INFO, "doorbell ioremaped at %p\n", db_ptr); 396 DPRINTK(INFO, "doorbell ioremaped at %p\n", db_ptr);
358 397
359 adapter->ahw.pci_base0 = mem_ptr0; 398 adapter->ahw.pci_base0 = mem_ptr0;
399 adapter->ahw.pci_len0 = pci_len0;
360 adapter->ahw.first_page_group_start = first_page_group_start; 400 adapter->ahw.first_page_group_start = first_page_group_start;
361 adapter->ahw.first_page_group_end = first_page_group_end; 401 adapter->ahw.first_page_group_end = first_page_group_end;
362 adapter->ahw.pci_base1 = mem_ptr1; 402 adapter->ahw.pci_base1 = mem_ptr1;
@@ -520,9 +560,6 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
520 INIT_WORK(&adapter->watchdog_task, netxen_watchdog_task); 560 INIT_WORK(&adapter->watchdog_task, netxen_watchdog_task);
521 adapter->ahw.revision_id = pdev->revision; 561 adapter->ahw.revision_id = pdev->revision;
522 562
523 /* make sure Window == 1 */
524 netxen_nic_pci_change_crbwindow(adapter, 1);
525
526 adapter->crb_addr_cmd_producer = crb_cmd_producer[adapter->portnum]; 563 adapter->crb_addr_cmd_producer = crb_cmd_producer[adapter->portnum];
527 adapter->crb_addr_cmd_consumer = crb_cmd_consumer[adapter->portnum]; 564 adapter->crb_addr_cmd_consumer = crb_cmd_consumer[adapter->portnum];
528 netxen_nic_update_cmd_producer(adapter, 0); 565 netxen_nic_update_cmd_producer(adapter, 0);
@@ -560,8 +597,8 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
560 err = netxen_initialize_adapter_offload(adapter); 597 err = netxen_initialize_adapter_offload(adapter);
561 if (err) 598 if (err)
562 goto err_out_free_rx_buffer; 599 goto err_out_free_rx_buffer;
563 val = readl(NETXEN_CRB_NORMALIZE(adapter, 600 val = adapter->pci_read_normalize(adapter,
564 NETXEN_CAM_RAM(0x1fc))); 601 NETXEN_CAM_RAM(0x1fc));
565 if (val == 0x55555555) { 602 if (val == 0x55555555) {
566 /* This is the first boot after power up */ 603 /* This is the first boot after power up */
567 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(0x4), &val); 604 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(0x4), &val);
@@ -573,20 +610,20 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
573 printk(KERN_ERR "%s: failed to set MSI bit in PCI-e reg\n", 610 printk(KERN_ERR "%s: failed to set MSI bit in PCI-e reg\n",
574 netxen_nic_driver_name); 611 netxen_nic_driver_name);
575 } 612 }
576 val = readl(NETXEN_CRB_NORMALIZE(adapter, 613 val = adapter->pci_read_normalize(adapter,
577 NETXEN_ROMUSB_GLB_SW_RESET)); 614 NETXEN_ROMUSB_GLB_SW_RESET);
578 printk(KERN_INFO"NetXen: read 0x%08x for reset reg.\n",val); 615 printk(KERN_INFO"NetXen: read 0x%08x for reset reg.\n",val);
579 if (val != 0x80000f) { 616 if (val != 0x80000f) {
580 /* clear the register for future unloads/loads */ 617 /* clear the register for future unloads/loads */
581 writel(0, NETXEN_CRB_NORMALIZE(adapter, 618 adapter->pci_write_normalize(adapter,
582 NETXEN_CAM_RAM(0x1fc))); 619 NETXEN_CAM_RAM(0x1fc), 0);
583 printk(KERN_ERR "ERROR in NetXen HW init sequence.\n"); 620 printk(KERN_ERR "ERROR in NetXen HW init sequence.\n");
584 err = -ENODEV; 621 err = -ENODEV;
585 goto err_out_free_dev; 622 goto err_out_free_dev;
586 } 623 }
587 } else { 624 } else {
588 writel(0, NETXEN_CRB_NORMALIZE(adapter, 625 adapter->pci_write_normalize(adapter,
589 CRB_CMDPEG_STATE)); 626 CRB_CMDPEG_STATE, 0);
590 netxen_pinit_from_rom(adapter, 0); 627 netxen_pinit_from_rom(adapter, 0);
591 msleep(1); 628 msleep(1);
592 netxen_load_firmware(adapter); 629 netxen_load_firmware(adapter);
@@ -602,9 +639,9 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
602 } 639 }
603 640
604 /* clear the register for future unloads/loads */ 641 /* clear the register for future unloads/loads */
605 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_CAM_RAM(0x1fc))); 642 adapter->pci_write_normalize(adapter, NETXEN_CAM_RAM(0x1fc), 0);
606 dev_info(&pdev->dev, "cmdpeg state: 0x%0x\n", 643 dev_info(&pdev->dev, "cmdpeg state: 0x%0x\n",
607 readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE))); 644 adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE));
608 645
609 /* 646 /*
610 * Tell the hardware our version number. 647 * Tell the hardware our version number.
@@ -612,12 +649,11 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
612 i = (_NETXEN_NIC_LINUX_MAJOR << 16) 649 i = (_NETXEN_NIC_LINUX_MAJOR << 16)
613 | ((_NETXEN_NIC_LINUX_MINOR << 8)) 650 | ((_NETXEN_NIC_LINUX_MINOR << 8))
614 | (_NETXEN_NIC_LINUX_SUBVERSION); 651 | (_NETXEN_NIC_LINUX_SUBVERSION);
615 writel(i, NETXEN_CRB_NORMALIZE(adapter, CRB_DRIVER_VERSION)); 652 adapter->pci_write_normalize(adapter, CRB_DRIVER_VERSION, i);
616 653
617 /* Unlock the HW, prompting the boot sequence */ 654 /* Unlock the HW, prompting the boot sequence */
618 writel(1, 655 adapter->pci_write_normalize(adapter,
619 NETXEN_CRB_NORMALIZE(adapter, 656 NETXEN_ROMUSB_GLB_PEGTUNE_DONE, 1);
620 NETXEN_ROMUSB_GLB_PEGTUNE_DONE));
621 /* Handshake with the card before we register the devices. */ 657 /* Handshake with the card before we register the devices. */
622 netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE); 658 netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
623 } 659 }
@@ -626,7 +662,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
626 * See if the firmware gave us a virtual-physical port mapping. 662 * See if the firmware gave us a virtual-physical port mapping.
627 */ 663 */
628 adapter->physical_port = adapter->portnum; 664 adapter->physical_port = adapter->portnum;
629 i = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_V2P(adapter->portnum))); 665 i = adapter->pci_read_normalize(adapter, CRB_V2P(adapter->portnum));
630 if (i != 0x55555555) 666 if (i != 0x55555555)
631 adapter->physical_port = i; 667 adapter->physical_port = i;
632 668
@@ -1104,15 +1140,15 @@ static irqreturn_t netxen_intr(int irq, void *data)
1104 struct netxen_adapter *adapter = data; 1140 struct netxen_adapter *adapter = data;
1105 u32 our_int = 0; 1141 u32 our_int = 0;
1106 1142
1107 our_int = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR)); 1143 our_int = adapter->pci_read_normalize(adapter, CRB_INT_VECTOR);
1108 /* not our interrupt */ 1144 /* not our interrupt */
1109 if ((our_int & (0x80 << adapter->portnum)) == 0) 1145 if ((our_int & (0x80 << adapter->portnum)) == 0)
1110 return IRQ_NONE; 1146 return IRQ_NONE;
1111 1147
1112 if (adapter->intr_scheme == INTR_SCHEME_PERPORT) { 1148 if (adapter->intr_scheme == INTR_SCHEME_PERPORT) {
1113 /* claim interrupt */ 1149 /* claim interrupt */
1114 writel(our_int & ~((u32)(0x80 << adapter->portnum)), 1150 adapter->pci_write_normalize(adapter, CRB_INT_VECTOR,
1115 NETXEN_CRB_NORMALIZE(adapter, CRB_INT_VECTOR)); 1151 our_int & ~((u32)(0x80 << adapter->portnum)));
1116 } 1152 }
1117 1153
1118 netxen_handle_int(adapter); 1154 netxen_handle_int(adapter);
diff --git a/drivers/net/netxen/netxen_nic_niu.c b/drivers/net/netxen/netxen_nic_niu.c
index d9664a0e08bc..78905d9dd4ba 100644
--- a/drivers/net/netxen/netxen_nic_niu.c
+++ b/drivers/net/netxen/netxen_nic_niu.c
@@ -46,9 +46,8 @@ static int phy_lock(struct netxen_adapter *adapter)
46 int done = 0, timeout = 0; 46 int done = 0, timeout = 0;
47 47
48 while (!done) { 48 while (!done) {
49 done = 49 done = netxen_nic_reg_read(adapter,
50 readl(pci_base_offset 50 NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
51 (adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK)));
52 if (done == 1) 51 if (done == 1)
53 break; 52 break;
54 if (timeout >= phy_lock_timeout) { 53 if (timeout >= phy_lock_timeout) {
@@ -63,14 +62,14 @@ static int phy_lock(struct netxen_adapter *adapter)
63 } 62 }
64 } 63 }
65 64
66 writel(PHY_LOCK_DRIVER, 65 netxen_crb_writelit_adapter(adapter,
67 NETXEN_CRB_NORMALIZE(adapter, NETXEN_PHY_LOCK_ID)); 66 NETXEN_PHY_LOCK_ID, PHY_LOCK_DRIVER);
68 return 0; 67 return 0;
69} 68}
70 69
71static int phy_unlock(struct netxen_adapter *adapter) 70static int phy_unlock(struct netxen_adapter *adapter)
72{ 71{
73 readl(pci_base_offset(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK))); 72 adapter->pci_read_immediate(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK));
74 73
75 return 0; 74 return 0;
76} 75}
@@ -109,7 +108,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
109 * so it cannot be in reset 108 * so it cannot be in reset
110 */ 109 */
111 110
112 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), 111 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
113 &mac_cfg0, 4)) 112 &mac_cfg0, 4))
114 return -EIO; 113 return -EIO;
115 if (netxen_gb_get_soft_reset(mac_cfg0)) { 114 if (netxen_gb_get_soft_reset(mac_cfg0)) {
@@ -119,7 +118,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
119 netxen_gb_rx_reset_pb(temp); 118 netxen_gb_rx_reset_pb(temp);
120 netxen_gb_tx_reset_mac(temp); 119 netxen_gb_tx_reset_mac(temp);
121 netxen_gb_rx_reset_mac(temp); 120 netxen_gb_rx_reset_mac(temp);
122 if (netxen_nic_hw_write_wx(adapter, 121 if (adapter->hw_write_wx(adapter,
123 NETXEN_NIU_GB_MAC_CONFIG_0(0), 122 NETXEN_NIU_GB_MAC_CONFIG_0(0),
124 &temp, 4)) 123 &temp, 4))
125 return -EIO; 124 return -EIO;
@@ -129,22 +128,22 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
129 address = 0; 128 address = 0;
130 netxen_gb_mii_mgmt_reg_addr(address, reg); 129 netxen_gb_mii_mgmt_reg_addr(address, reg);
131 netxen_gb_mii_mgmt_phy_addr(address, phy); 130 netxen_gb_mii_mgmt_phy_addr(address, phy);
132 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), 131 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
133 &address, 4)) 132 &address, 4))
134 return -EIO; 133 return -EIO;
135 command = 0; /* turn off any prior activity */ 134 command = 0; /* turn off any prior activity */
136 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), 135 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
137 &command, 4)) 136 &command, 4))
138 return -EIO; 137 return -EIO;
139 /* send read command */ 138 /* send read command */
140 netxen_gb_mii_mgmt_set_read_cycle(command); 139 netxen_gb_mii_mgmt_set_read_cycle(command);
141 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), 140 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
142 &command, 4)) 141 &command, 4))
143 return -EIO; 142 return -EIO;
144 143
145 status = 0; 144 status = 0;
146 do { 145 do {
147 if (netxen_nic_hw_read_wx(adapter, 146 if (adapter->hw_read_wx(adapter,
148 NETXEN_NIU_GB_MII_MGMT_INDICATE(0), 147 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
149 &status, 4)) 148 &status, 4))
150 return -EIO; 149 return -EIO;
@@ -154,7 +153,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
154 && (timeout++ < NETXEN_NIU_PHY_WAITMAX)); 153 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
155 154
156 if (timeout < NETXEN_NIU_PHY_WAITMAX) { 155 if (timeout < NETXEN_NIU_PHY_WAITMAX) {
157 if (netxen_nic_hw_read_wx(adapter, 156 if (adapter->hw_read_wx(adapter,
158 NETXEN_NIU_GB_MII_MGMT_STATUS(0), 157 NETXEN_NIU_GB_MII_MGMT_STATUS(0),
159 readval, 4)) 158 readval, 4))
160 return -EIO; 159 return -EIO;
@@ -163,7 +162,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
163 result = -1; 162 result = -1;
164 163
165 if (restore) 164 if (restore)
166 if (netxen_nic_hw_write_wx(adapter, 165 if (adapter->hw_write_wx(adapter,
167 NETXEN_NIU_GB_MAC_CONFIG_0(0), 166 NETXEN_NIU_GB_MAC_CONFIG_0(0),
168 &mac_cfg0, 4)) 167 &mac_cfg0, 4))
169 return -EIO; 168 return -EIO;
@@ -201,7 +200,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
201 * cannot be in reset 200 * cannot be in reset
202 */ 201 */
203 202
204 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), 203 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
205 &mac_cfg0, 4)) 204 &mac_cfg0, 4))
206 return -EIO; 205 return -EIO;
207 if (netxen_gb_get_soft_reset(mac_cfg0)) { 206 if (netxen_gb_get_soft_reset(mac_cfg0)) {
@@ -212,7 +211,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
212 netxen_gb_tx_reset_mac(temp); 211 netxen_gb_tx_reset_mac(temp);
213 netxen_gb_rx_reset_mac(temp); 212 netxen_gb_rx_reset_mac(temp);
214 213
215 if (netxen_nic_hw_write_wx(adapter, 214 if (adapter->hw_write_wx(adapter,
216 NETXEN_NIU_GB_MAC_CONFIG_0(0), 215 NETXEN_NIU_GB_MAC_CONFIG_0(0),
217 &temp, 4)) 216 &temp, 4))
218 return -EIO; 217 return -EIO;
@@ -220,24 +219,24 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
220 } 219 }
221 220
222 command = 0; /* turn off any prior activity */ 221 command = 0; /* turn off any prior activity */
223 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), 222 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
224 &command, 4)) 223 &command, 4))
225 return -EIO; 224 return -EIO;
226 225
227 address = 0; 226 address = 0;
228 netxen_gb_mii_mgmt_reg_addr(address, reg); 227 netxen_gb_mii_mgmt_reg_addr(address, reg);
229 netxen_gb_mii_mgmt_phy_addr(address, phy); 228 netxen_gb_mii_mgmt_phy_addr(address, phy);
230 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), 229 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
231 &address, 4)) 230 &address, 4))
232 return -EIO; 231 return -EIO;
233 232
234 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0), 233 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0),
235 &val, 4)) 234 &val, 4))
236 return -EIO; 235 return -EIO;
237 236
238 status = 0; 237 status = 0;
239 do { 238 do {
240 if (netxen_nic_hw_read_wx(adapter, 239 if (adapter->hw_read_wx(adapter,
241 NETXEN_NIU_GB_MII_MGMT_INDICATE(0), 240 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
242 &status, 4)) 241 &status, 4))
243 return -EIO; 242 return -EIO;
@@ -252,7 +251,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
252 251
253 /* restore the state of port 0 MAC in case we tampered with it */ 252 /* restore the state of port 0 MAC in case we tampered with it */
254 if (restore) 253 if (restore)
255 if (netxen_nic_hw_write_wx(adapter, 254 if (adapter->hw_write_wx(adapter,
256 NETXEN_NIU_GB_MAC_CONFIG_0(0), 255 NETXEN_NIU_GB_MAC_CONFIG_0(0),
257 &mac_cfg0, 4)) 256 &mac_cfg0, 4))
258 return -EIO; 257 return -EIO;
@@ -581,10 +580,10 @@ static int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
581 if ((phy < 0) || (phy > 3)) 580 if ((phy < 0) || (phy > 3))
582 return -EINVAL; 581 return -EINVAL;
583 582
584 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), 583 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy),
585 &stationhigh, 4)) 584 &stationhigh, 4))
586 return -EIO; 585 return -EIO;
587 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), 586 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy),
588 &stationlow, 4)) 587 &stationlow, 4))
589 return -EIO; 588 return -EIO;
590 ((__le32 *)val)[1] = cpu_to_le32(stationhigh); 589 ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
@@ -613,14 +612,14 @@ int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
613 temp[0] = temp[1] = 0; 612 temp[0] = temp[1] = 0;
614 memcpy(temp + 2, addr, 2); 613 memcpy(temp + 2, addr, 2);
615 val = le32_to_cpu(*(__le32 *)temp); 614 val = le32_to_cpu(*(__le32 *)temp);
616 if (netxen_nic_hw_write_wx 615 if (adapter->hw_write_wx(adapter,
617 (adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), &val, 4)) 616 NETXEN_NIU_GB_STATION_ADDR_1(phy), &val, 4))
618 return -EIO; 617 return -EIO;
619 618
620 memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32)); 619 memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32));
621 val = le32_to_cpu(*(__le32 *)temp); 620 val = le32_to_cpu(*(__le32 *)temp);
622 if (netxen_nic_hw_write_wx 621 if (adapter->hw_write_wx(adapter,
623 (adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), &val, 4)) 622 NETXEN_NIU_GB_STATION_ADDR_0(phy), &val, 4))
624 return -2; 623 return -2;
625 624
626 netxen_niu_macaddr_get(adapter, 625 netxen_niu_macaddr_get(adapter,
@@ -654,7 +653,7 @@ int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
654 653
655 mac_cfg0 = 0; 654 mac_cfg0 = 0;
656 netxen_gb_soft_reset(mac_cfg0); 655 netxen_gb_soft_reset(mac_cfg0);
657 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 656 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
658 &mac_cfg0, 4)) 657 &mac_cfg0, 4))
659 return -EIO; 658 return -EIO;
660 mac_cfg0 = 0; 659 mac_cfg0 = 0;
@@ -666,7 +665,7 @@ int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
666 netxen_gb_tx_reset_mac(mac_cfg0); 665 netxen_gb_tx_reset_mac(mac_cfg0);
667 netxen_gb_rx_reset_mac(mac_cfg0); 666 netxen_gb_rx_reset_mac(mac_cfg0);
668 667
669 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 668 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
670 &mac_cfg0, 4)) 669 &mac_cfg0, 4))
671 return -EIO; 670 return -EIO;
672 mac_cfg1 = 0; 671 mac_cfg1 = 0;
@@ -679,7 +678,7 @@ int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
679 678
680 if (mode == NETXEN_NIU_10_100_MB) { 679 if (mode == NETXEN_NIU_10_100_MB) {
681 netxen_gb_set_intfmode(mac_cfg1, 1); 680 netxen_gb_set_intfmode(mac_cfg1, 1);
682 if (netxen_nic_hw_write_wx(adapter, 681 if (adapter->hw_write_wx(adapter,
683 NETXEN_NIU_GB_MAC_CONFIG_1(port), 682 NETXEN_NIU_GB_MAC_CONFIG_1(port),
684 &mac_cfg1, 4)) 683 &mac_cfg1, 4))
685 return -EIO; 684 return -EIO;
@@ -692,7 +691,7 @@ int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
692 691
693 } else if (mode == NETXEN_NIU_1000_MB) { 692 } else if (mode == NETXEN_NIU_1000_MB) {
694 netxen_gb_set_intfmode(mac_cfg1, 2); 693 netxen_gb_set_intfmode(mac_cfg1, 2);
695 if (netxen_nic_hw_write_wx(adapter, 694 if (adapter->hw_write_wx(adapter,
696 NETXEN_NIU_GB_MAC_CONFIG_1(port), 695 NETXEN_NIU_GB_MAC_CONFIG_1(port),
697 &mac_cfg1, 4)) 696 &mac_cfg1, 4))
698 return -EIO; 697 return -EIO;
@@ -704,7 +703,7 @@ int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
704 } 703 }
705 mii_cfg = 0; 704 mii_cfg = 0;
706 netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7); 705 netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7);
707 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 706 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port),
708 &mii_cfg, 4)) 707 &mii_cfg, 4))
709 return -EIO; 708 return -EIO;
710 mac_cfg0 = 0; 709 mac_cfg0 = 0;
@@ -713,7 +712,7 @@ int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
713 netxen_gb_unset_rx_flowctl(mac_cfg0); 712 netxen_gb_unset_rx_flowctl(mac_cfg0);
714 netxen_gb_unset_tx_flowctl(mac_cfg0); 713 netxen_gb_unset_tx_flowctl(mac_cfg0);
715 714
716 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 715 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
717 &mac_cfg0, 4)) 716 &mac_cfg0, 4))
718 return -EIO; 717 return -EIO;
719 return 0; 718 return 0;
@@ -730,7 +729,7 @@ int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
730 return -EINVAL; 729 return -EINVAL;
731 mac_cfg0 = 0; 730 mac_cfg0 = 0;
732 netxen_gb_soft_reset(mac_cfg0); 731 netxen_gb_soft_reset(mac_cfg0);
733 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 732 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
734 &mac_cfg0, 4)) 733 &mac_cfg0, 4))
735 return -EIO; 734 return -EIO;
736 return 0; 735 return 0;
@@ -746,7 +745,7 @@ int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
746 return -EINVAL; 745 return -EINVAL;
747 746
748 mac_cfg = 0; 747 mac_cfg = 0;
749 if (netxen_nic_hw_write_wx(adapter, 748 if (adapter->hw_write_wx(adapter,
750 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), &mac_cfg, 4)) 749 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), &mac_cfg, 4))
751 return -EIO; 750 return -EIO;
752 return 0; 751 return 0;
@@ -763,7 +762,7 @@ int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
763 return -EINVAL; 762 return -EINVAL;
764 763
765 /* save previous contents */ 764 /* save previous contents */
766 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, 765 if (adapter->hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
767 &reg, 4)) 766 &reg, 4))
768 return -EIO; 767 return -EIO;
769 if (mode == NETXEN_NIU_PROMISC_MODE) { 768 if (mode == NETXEN_NIU_PROMISC_MODE) {
@@ -801,7 +800,7 @@ int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
801 return -EIO; 800 return -EIO;
802 } 801 }
803 } 802 }
804 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, 803 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
805 &reg, 4)) 804 &reg, 4))
806 return -EIO; 805 return -EIO;
807 return 0; 806 return 0;
@@ -826,13 +825,13 @@ int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
826 case 0: 825 case 0:
827 memcpy(temp + 2, addr, 2); 826 memcpy(temp + 2, addr, 2);
828 val = le32_to_cpu(*(__le32 *)temp); 827 val = le32_to_cpu(*(__le32 *)temp);
829 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1, 828 if (adapter->hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
830 &val, 4)) 829 &val, 4))
831 return -EIO; 830 return -EIO;
832 831
833 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32)); 832 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
834 val = le32_to_cpu(*(__le32 *)temp); 833 val = le32_to_cpu(*(__le32 *)temp);
835 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI, 834 if (adapter->hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
836 &val, 4)) 835 &val, 4))
837 return -EIO; 836 return -EIO;
838 break; 837 break;
@@ -840,13 +839,13 @@ int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
840 case 1: 839 case 1:
841 memcpy(temp + 2, addr, 2); 840 memcpy(temp + 2, addr, 2);
842 val = le32_to_cpu(*(__le32 *)temp); 841 val = le32_to_cpu(*(__le32 *)temp);
843 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_1, 842 if (adapter->hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_1,
844 &val, 4)) 843 &val, 4))
845 return -EIO; 844 return -EIO;
846 845
847 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32)); 846 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
848 val = le32_to_cpu(*(__le32 *)temp); 847 val = le32_to_cpu(*(__le32 *)temp);
849 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_HI, 848 if (adapter->hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_HI,
850 &val, 4)) 849 &val, 4))
851 return -EIO; 850 return -EIO;
852 break; 851 break;
@@ -877,10 +876,10 @@ int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter,
877 if (phy != 0) 876 if (phy != 0)
878 return -EINVAL; 877 return -EINVAL;
879 878
880 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI, 879 if (adapter->hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
881 &stationhigh, 4)) 880 &stationhigh, 4))
882 return -EIO; 881 return -EIO;
883 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1, 882 if (adapter->hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
884 &stationlow, 4)) 883 &stationlow, 4))
885 return -EIO; 884 return -EIO;
886 ((__le32 *)val)[1] = cpu_to_le32(stationhigh); 885 ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
@@ -901,7 +900,7 @@ int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
901 if (port > NETXEN_NIU_MAX_XG_PORTS) 900 if (port > NETXEN_NIU_MAX_XG_PORTS)
902 return -EINVAL; 901 return -EINVAL;
903 902
904 if (netxen_nic_hw_read_wx(adapter, 903 if (adapter->hw_read_wx(adapter,
905 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), &reg, 4)) 904 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), &reg, 4))
906 return -EIO; 905 return -EIO;
907 if (mode == NETXEN_NIU_PROMISC_MODE) 906 if (mode == NETXEN_NIU_PROMISC_MODE)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-08 23:27:57 -0400