diff options
| author | Dhananjay Phadke <dhananjay@netxen.com> | 2009-09-11 07:28:12 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-09-11 19:58:42 -0400 |
| commit | ea6828b8aa3a8ebae8d7740f32f212ba1d2f0742 (patch) | |
| tree | 6a783fc6ceb9de3edf2577af1ed5d6acc0deca74 /drivers/net/netxen | |
| parent | f78c0850d2ebe7a44a4b0263480a2f1a36a92218 (diff) | |
netxen: improve pci memory access
o Access on card memory through memory controller (agent)
rather than moving small pci window around. Clean up the
code for moving windows around.
o Restrict memory accesss to 64 bit, currently only firmware
download uses this.
Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/netxen')
| -rw-r--r-- | drivers/net/netxen/netxen_nic.h | 4 | ||||
| -rw-r--r-- | drivers/net/netxen/netxen_nic_hw.c | 348 | ||||
| -rw-r--r-- | drivers/net/netxen/netxen_nic_main.c | 7 |
3 files changed, 93 insertions, 266 deletions
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h index 23718887d02c..7e3d2b932790 100644 --- a/drivers/net/netxen/netxen_nic.h +++ b/drivers/net/netxen/netxen_nic.h | |||
| @@ -552,8 +552,8 @@ struct netxen_hardware_context { | |||
| 552 | 552 | ||
| 553 | int qdr_sn_window; | 553 | int qdr_sn_window; |
| 554 | int ddr_mn_window; | 554 | int ddr_mn_window; |
| 555 | unsigned long mn_win_crb; | 555 | u32 mn_win_crb; |
| 556 | unsigned long ms_win_crb; | 556 | u32 ms_win_crb; |
| 557 | 557 | ||
| 558 | u8 cut_through; | 558 | u8 cut_through; |
| 559 | u8 revision_id; | 559 | u8 revision_id; |
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c index 555bc4a7e888..018cf429c308 100644 --- a/drivers/net/netxen/netxen_nic_hw.c +++ b/drivers/net/netxen/netxen_nic_hw.c | |||
| @@ -1279,25 +1279,6 @@ netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off) | |||
| 1279 | return data; | 1279 | return data; |
| 1280 | } | 1280 | } |
| 1281 | 1281 | ||
| 1282 | /* | ||
| 1283 | * check memory access boundary. | ||
| 1284 | * used by test agent. support ddr access only for now | ||
| 1285 | */ | ||
| 1286 | static unsigned long | ||
| 1287 | netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter, | ||
| 1288 | unsigned long long addr, int size) | ||
| 1289 | { | ||
| 1290 | if (!ADDR_IN_RANGE(addr, | ||
| 1291 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || | ||
| 1292 | !ADDR_IN_RANGE(addr+size-1, | ||
| 1293 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || | ||
| 1294 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { | ||
| 1295 | return 0; | ||
| 1296 | } | ||
| 1297 | |||
| 1298 | return 1; | ||
| 1299 | } | ||
| 1300 | |||
| 1301 | static int netxen_pci_set_window_warning_count; | 1282 | static int netxen_pci_set_window_warning_count; |
| 1302 | 1283 | ||
| 1303 | static unsigned long | 1284 | static unsigned long |
| @@ -1424,10 +1405,8 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |||
| 1424 | /* DDR network side */ | 1405 | /* DDR network side */ |
| 1425 | window = MN_WIN(addr); | 1406 | window = MN_WIN(addr); |
| 1426 | adapter->ahw.ddr_mn_window = window; | 1407 | adapter->ahw.ddr_mn_window = window; |
| 1427 | NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, | 1408 | NXWR32(adapter, adapter->ahw.mn_win_crb, window); |
| 1428 | window); | 1409 | win_read = NXRD32(adapter, adapter->ahw.mn_win_crb); |
| 1429 | win_read = NXRD32(adapter, | ||
| 1430 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE); | ||
| 1431 | if ((win_read << 17) != window) { | 1410 | if ((win_read << 17) != window) { |
| 1432 | printk(KERN_INFO "Written MNwin (0x%x) != " | 1411 | printk(KERN_INFO "Written MNwin (0x%x) != " |
| 1433 | "Read MNwin (0x%x)\n", window, win_read); | 1412 | "Read MNwin (0x%x)\n", window, win_read); |
| @@ -1442,10 +1421,8 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |||
| 1442 | 1421 | ||
| 1443 | window = OCM_WIN(addr); | 1422 | window = OCM_WIN(addr); |
| 1444 | adapter->ahw.ddr_mn_window = window; | 1423 | adapter->ahw.ddr_mn_window = window; |
| 1445 | NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, | 1424 | NXWR32(adapter, adapter->ahw.mn_win_crb, window); |
| 1446 | window); | 1425 | win_read = NXRD32(adapter, adapter->ahw.mn_win_crb); |
| 1447 | win_read = NXRD32(adapter, | ||
| 1448 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE); | ||
| 1449 | if ((win_read >> 7) != window) { | 1426 | if ((win_read >> 7) != window) { |
| 1450 | printk(KERN_INFO "%s: Written OCMwin (0x%x) != " | 1427 | printk(KERN_INFO "%s: Written OCMwin (0x%x) != " |
| 1451 | "Read OCMwin (0x%x)\n", | 1428 | "Read OCMwin (0x%x)\n", |
| @@ -1458,10 +1435,8 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |||
| 1458 | /* QDR network side */ | 1435 | /* QDR network side */ |
| 1459 | window = MS_WIN(addr); | 1436 | window = MS_WIN(addr); |
| 1460 | adapter->ahw.qdr_sn_window = window; | 1437 | adapter->ahw.qdr_sn_window = window; |
| 1461 | NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE, | 1438 | NXWR32(adapter, adapter->ahw.ms_win_crb, window); |
| 1462 | window); | 1439 | win_read = NXRD32(adapter, adapter->ahw.ms_win_crb); |
| 1463 | win_read = NXRD32(adapter, | ||
| 1464 | adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE); | ||
| 1465 | if (win_read != window) { | 1440 | if (win_read != window) { |
| 1466 | printk(KERN_INFO "%s: Written MSwin (0x%x) != " | 1441 | printk(KERN_INFO "%s: Written MSwin (0x%x) != " |
| 1467 | "Read MSwin (0x%x)\n", | 1442 | "Read MSwin (0x%x)\n", |
| @@ -1484,177 +1459,6 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, | |||
| 1484 | return addr; | 1459 | return addr; |
| 1485 | } | 1460 | } |
| 1486 | 1461 | ||
| 1487 | static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter, | ||
| 1488 | unsigned long long addr) | ||
| 1489 | { | ||
| 1490 | int window; | ||
| 1491 | unsigned long long qdr_max; | ||
| 1492 | |||
| 1493 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | ||
| 1494 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2; | ||
| 1495 | else | ||
| 1496 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3; | ||
| 1497 | |||
| 1498 | if (ADDR_IN_RANGE(addr, | ||
| 1499 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | ||
| 1500 | /* DDR network side */ | ||
| 1501 | BUG(); /* MN access can not come here */ | ||
| 1502 | } else if (ADDR_IN_RANGE(addr, | ||
| 1503 | NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { | ||
| 1504 | return 1; | ||
| 1505 | } else if (ADDR_IN_RANGE(addr, | ||
| 1506 | NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { | ||
| 1507 | return 1; | ||
| 1508 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) { | ||
| 1509 | /* QDR network side */ | ||
| 1510 | window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f; | ||
| 1511 | if (adapter->ahw.qdr_sn_window == window) | ||
| 1512 | return 1; | ||
| 1513 | } | ||
| 1514 | |||
| 1515 | return 0; | ||
| 1516 | } | ||
| 1517 | |||
| 1518 | static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter, | ||
| 1519 | u64 off, void *data, int size) | ||
| 1520 | { | ||
| 1521 | unsigned long flags; | ||
| 1522 | void __iomem *addr, *mem_ptr = NULL; | ||
| 1523 | int ret = 0; | ||
| 1524 | u64 start; | ||
| 1525 | unsigned long mem_base; | ||
| 1526 | unsigned long mem_page; | ||
| 1527 | |||
| 1528 | write_lock_irqsave(&adapter->adapter_lock, flags); | ||
| 1529 | |||
| 1530 | /* | ||
| 1531 | * If attempting to access unknown address or straddle hw windows, | ||
| 1532 | * do not access. | ||
| 1533 | */ | ||
| 1534 | start = adapter->pci_set_window(adapter, off); | ||
| 1535 | if ((start == -1UL) || | ||
| 1536 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { | ||
| 1537 | write_unlock_irqrestore(&adapter->adapter_lock, flags); | ||
| 1538 | printk(KERN_ERR "%s out of bound pci memory access. " | ||
| 1539 | "offset is 0x%llx\n", netxen_nic_driver_name, | ||
| 1540 | (unsigned long long)off); | ||
| 1541 | return -1; | ||
| 1542 | } | ||
| 1543 | |||
| 1544 | addr = pci_base_offset(adapter, start); | ||
| 1545 | if (!addr) { | ||
| 1546 | write_unlock_irqrestore(&adapter->adapter_lock, flags); | ||
| 1547 | mem_base = pci_resource_start(adapter->pdev, 0); | ||
| 1548 | mem_page = start & PAGE_MASK; | ||
| 1549 | /* Map two pages whenever user tries to access addresses in two | ||
| 1550 | consecutive pages. | ||
| 1551 | */ | ||
| 1552 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | ||
| 1553 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); | ||
| 1554 | else | ||
| 1555 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | ||
| 1556 | if (mem_ptr == NULL) { | ||
| 1557 | *(uint8_t *)data = 0; | ||
| 1558 | return -1; | ||
| 1559 | } | ||
| 1560 | addr = mem_ptr; | ||
| 1561 | addr += start & (PAGE_SIZE - 1); | ||
| 1562 | write_lock_irqsave(&adapter->adapter_lock, flags); | ||
| 1563 | } | ||
| 1564 | |||
| 1565 | switch (size) { | ||
| 1566 | case 1: | ||
| 1567 | *(uint8_t *)data = readb(addr); | ||
| 1568 | break; | ||
| 1569 | case 2: | ||
| 1570 | *(uint16_t *)data = readw(addr); | ||
| 1571 | break; | ||
| 1572 | case 4: | ||
| 1573 | *(uint32_t *)data = readl(addr); | ||
| 1574 | break; | ||
| 1575 | case 8: | ||
| 1576 | *(uint64_t *)data = readq(addr); | ||
| 1577 | break; | ||
| 1578 | default: | ||
| 1579 | ret = -1; | ||
| 1580 | break; | ||
| 1581 | } | ||
| 1582 | write_unlock_irqrestore(&adapter->adapter_lock, flags); | ||
| 1583 | |||
| 1584 | if (mem_ptr) | ||
| 1585 | iounmap(mem_ptr); | ||
| 1586 | return ret; | ||
| 1587 | } | ||
| 1588 | |||
| 1589 | static int | ||
| 1590 | netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off, | ||
| 1591 | void *data, int size) | ||
| 1592 | { | ||
| 1593 | unsigned long flags; | ||
| 1594 | void __iomem *addr, *mem_ptr = NULL; | ||
| 1595 | int ret = 0; | ||
| 1596 | u64 start; | ||
| 1597 | unsigned long mem_base; | ||
| 1598 | unsigned long mem_page; | ||
| 1599 | |||
| 1600 | write_lock_irqsave(&adapter->adapter_lock, flags); | ||
| 1601 | |||
| 1602 | /* | ||
| 1603 | * If attempting to access unknown address or straddle hw windows, | ||
| 1604 | * do not access. | ||
| 1605 | */ | ||
| 1606 | start = adapter->pci_set_window(adapter, off); | ||
| 1607 | if ((start == -1UL) || | ||
| 1608 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { | ||
| 1609 | write_unlock_irqrestore(&adapter->adapter_lock, flags); | ||
| 1610 | printk(KERN_ERR "%s out of bound pci memory access. " | ||
| 1611 | "offset is 0x%llx\n", netxen_nic_driver_name, | ||
| 1612 | (unsigned long long)off); | ||
| 1613 | return -1; | ||
| 1614 | } | ||
| 1615 | |||
| 1616 | addr = pci_base_offset(adapter, start); | ||
| 1617 | if (!addr) { | ||
| 1618 | write_unlock_irqrestore(&adapter->adapter_lock, flags); | ||
| 1619 | mem_base = pci_resource_start(adapter->pdev, 0); | ||
| 1620 | mem_page = start & PAGE_MASK; | ||
| 1621 | /* Map two pages whenever user tries to access addresses in two | ||
| 1622 | * consecutive pages. | ||
| 1623 | */ | ||
| 1624 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | ||
| 1625 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); | ||
| 1626 | else | ||
| 1627 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | ||
| 1628 | if (mem_ptr == NULL) | ||
| 1629 | return -1; | ||
| 1630 | addr = mem_ptr; | ||
| 1631 | addr += start & (PAGE_SIZE - 1); | ||
| 1632 | write_lock_irqsave(&adapter->adapter_lock, flags); | ||
| 1633 | } | ||
| 1634 | |||
| 1635 | switch (size) { | ||
| 1636 | case 1: | ||
| 1637 | writeb(*(uint8_t *)data, addr); | ||
| 1638 | break; | ||
| 1639 | case 2: | ||
| 1640 | writew(*(uint16_t *)data, addr); | ||
| 1641 | break; | ||
| 1642 | case 4: | ||
| 1643 | writel(*(uint32_t *)data, addr); | ||
| 1644 | break; | ||
| 1645 | case 8: | ||
| 1646 | writeq(*(uint64_t *)data, addr); | ||
| 1647 | break; | ||
| 1648 | default: | ||
| 1649 | ret = -1; | ||
| 1650 | break; | ||
| 1651 | } | ||
| 1652 | write_unlock_irqrestore(&adapter->adapter_lock, flags); | ||
| 1653 | if (mem_ptr) | ||
| 1654 | iounmap(mem_ptr); | ||
| 1655 | return ret; | ||
| 1656 | } | ||
| 1657 | |||
| 1658 | #define MAX_CTL_CHECK 1000 | 1462 | #define MAX_CTL_CHECK 1000 |
| 1659 | 1463 | ||
| 1660 | static int | 1464 | static int |
| @@ -1667,19 +1471,28 @@ netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, | |||
| 1667 | uint64_t off8, tmpw, word[2] = {0, 0}; | 1471 | uint64_t off8, tmpw, word[2] = {0, 0}; |
| 1668 | void __iomem *mem_crb; | 1472 | void __iomem *mem_crb; |
| 1669 | 1473 | ||
| 1670 | /* | 1474 | if (size != 8) |
| 1671 | * If not MN, go check for MS or invalid. | 1475 | return -EIO; |
| 1672 | */ | 1476 | |
| 1673 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) | 1477 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
| 1674 | return netxen_nic_pci_mem_write_direct(adapter, | 1478 | NETXEN_ADDR_QDR_NET_MAX_P2)) { |
| 1675 | off, data, size); | 1479 | mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET); |
| 1480 | goto correct; | ||
| 1481 | } | ||
| 1482 | |||
| 1483 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | ||
| 1484 | mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET); | ||
| 1485 | goto correct; | ||
| 1486 | } | ||
| 1487 | |||
| 1488 | return -EIO; | ||
| 1676 | 1489 | ||
| 1490 | correct: | ||
| 1677 | off8 = off & 0xfffffff8; | 1491 | off8 = off & 0xfffffff8; |
| 1678 | off0 = off & 0x7; | 1492 | off0 = off & 0x7; |
| 1679 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); | 1493 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); |
| 1680 | sz[1] = size - sz[0]; | 1494 | sz[1] = size - sz[0]; |
| 1681 | loop = ((off0 + size - 1) >> 3) + 1; | 1495 | loop = ((off0 + size - 1) >> 3) + 1; |
| 1682 | mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET); | ||
| 1683 | 1496 | ||
| 1684 | if ((size != 8) || (off0 != 0)) { | 1497 | if ((size != 8) || (off0 != 0)) { |
| 1685 | for (i = 0; i < loop; i++) { | 1498 | for (i = 0; i < loop; i++) { |
| @@ -1760,20 +1573,29 @@ netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, | |||
| 1760 | uint64_t off8, val, word[2] = {0, 0}; | 1573 | uint64_t off8, val, word[2] = {0, 0}; |
| 1761 | void __iomem *mem_crb; | 1574 | void __iomem *mem_crb; |
| 1762 | 1575 | ||
| 1576 | if (size != 8) | ||
| 1577 | return -EIO; | ||
| 1763 | 1578 | ||
| 1764 | /* | 1579 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
| 1765 | * If not MN, go check for MS or invalid. | 1580 | NETXEN_ADDR_QDR_NET_MAX_P2)) { |
| 1766 | */ | 1581 | mem_crb = pci_base_offset(adapter, NETXEN_CRB_QDR_NET); |
| 1767 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) | 1582 | goto correct; |
| 1768 | return netxen_nic_pci_mem_read_direct(adapter, off, data, size); | 1583 | } |
| 1769 | 1584 | ||
| 1585 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | ||
| 1586 | mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET); | ||
| 1587 | goto correct; | ||
| 1588 | } | ||
| 1589 | |||
| 1590 | return -EIO; | ||
| 1591 | |||
| 1592 | correct: | ||
| 1770 | off8 = off & 0xfffffff8; | 1593 | off8 = off & 0xfffffff8; |
| 1771 | off0[0] = off & 0x7; | 1594 | off0[0] = off & 0x7; |
| 1772 | off0[1] = 0; | 1595 | off0[1] = 0; |
| 1773 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); | 1596 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); |
| 1774 | sz[1] = size - sz[0]; | 1597 | sz[1] = size - sz[0]; |
| 1775 | loop = ((off0[0] + size - 1) >> 3) + 1; | 1598 | loop = ((off0[0] + size - 1) >> 3) + 1; |
| 1776 | mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET); | ||
| 1777 | 1599 | ||
| 1778 | write_lock_irqsave(&adapter->adapter_lock, flags); | 1600 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1779 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); | 1601 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| @@ -1847,20 +1669,26 @@ netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, | |||
| 1847 | { | 1669 | { |
| 1848 | int i, j, ret = 0, loop, sz[2], off0; | 1670 | int i, j, ret = 0, loop, sz[2], off0; |
| 1849 | uint32_t temp; | 1671 | uint32_t temp; |
| 1850 | uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; | 1672 | uint64_t off8, tmpw, word[2] = {0, 0}; |
| 1673 | void __iomem *mem_crb; | ||
| 1851 | 1674 | ||
| 1852 | /* | 1675 | if (size != 8) |
| 1853 | * If not MN, go check for MS or invalid. | 1676 | return -EIO; |
| 1854 | */ | 1677 | |
| 1855 | if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) | 1678 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, |
| 1856 | mem_crb = NETXEN_CRB_QDR_NET; | 1679 | NETXEN_ADDR_QDR_NET_MAX_P3)) { |
| 1857 | else { | 1680 | mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET); |
| 1858 | mem_crb = NETXEN_CRB_DDR_NET; | 1681 | goto correct; |
| 1859 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) | ||
| 1860 | return netxen_nic_pci_mem_write_direct(adapter, | ||
| 1861 | off, data, size); | ||
| 1862 | } | 1682 | } |
| 1863 | 1683 | ||
| 1684 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { | ||
| 1685 | mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET); | ||
| 1686 | goto correct; | ||
| 1687 | } | ||
| 1688 | |||
| 1689 | return -EIO; | ||
| 1690 | |||
| 1691 | correct: | ||
| 1864 | off8 = off & 0xfffffff8; | 1692 | off8 = off & 0xfffffff8; |
| 1865 | off0 = off & 0x7; | 1693 | off0 = off & 0x7; |
| 1866 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); | 1694 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); |
| @@ -1906,21 +1734,18 @@ netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, | |||
| 1906 | */ | 1734 | */ |
| 1907 | 1735 | ||
| 1908 | for (i = 0; i < loop; i++) { | 1736 | for (i = 0; i < loop; i++) { |
| 1909 | temp = off8 + (i << 3); | 1737 | writel(off8 + (i << 3), mem_crb+MIU_TEST_AGT_ADDR_LO); |
| 1910 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); | 1738 | writel(0, mem_crb+MIU_TEST_AGT_ADDR_HI); |
| 1911 | temp = 0; | 1739 | writel(word[i] & 0xffffffff, mem_crb+MIU_TEST_AGT_WRDATA_LO); |
| 1912 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); | 1740 | writel((word[i] >> 32) & 0xffffffff, |
| 1913 | temp = word[i] & 0xffffffff; | 1741 | mem_crb+MIU_TEST_AGT_WRDATA_HI); |
| 1914 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); | 1742 | writel((MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE), |
| 1915 | temp = (word[i] >> 32) & 0xffffffff; | 1743 | mem_crb+MIU_TEST_AGT_CTRL); |
| 1916 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); | 1744 | writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE, |
| 1917 | temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | 1745 | mem_crb+MIU_TEST_AGT_CTRL); |
| 1918 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp); | ||
| 1919 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | ||
| 1920 | NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp); | ||
| 1921 | 1746 | ||
| 1922 | for (j = 0; j < MAX_CTL_CHECK; j++) { | 1747 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1923 | temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL); | 1748 | temp = readl(mem_crb + MIU_TEST_AGT_CTRL); |
| 1924 | if ((temp & MIU_TA_CTL_BUSY) == 0) | 1749 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1925 | break; | 1750 | break; |
| 1926 | } | 1751 | } |
| @@ -1947,21 +1772,26 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, | |||
| 1947 | { | 1772 | { |
| 1948 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; | 1773 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; |
| 1949 | uint32_t temp; | 1774 | uint32_t temp; |
| 1950 | uint64_t off8, val, mem_crb, word[2] = {0, 0}; | 1775 | uint64_t off8, val, word[2] = {0, 0}; |
| 1776 | void __iomem *mem_crb; | ||
| 1951 | 1777 | ||
| 1952 | /* | 1778 | if (size != 8) |
| 1953 | * If not MN, go check for MS or invalid. | 1779 | return -EIO; |
| 1954 | */ | 1780 | |
| 1781 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET, | ||
| 1782 | NETXEN_ADDR_QDR_NET_MAX_P3)) { | ||
| 1783 | mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_QDR_NET); | ||
| 1784 | goto correct; | ||
| 1785 | } | ||
| 1955 | 1786 | ||
| 1956 | if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) | 1787 | if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1957 | mem_crb = NETXEN_CRB_QDR_NET; | 1788 | mem_crb = netxen_get_ioaddr(adapter, NETXEN_CRB_DDR_NET); |
| 1958 | else { | 1789 | goto correct; |
| 1959 | mem_crb = NETXEN_CRB_DDR_NET; | ||
| 1960 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) | ||
| 1961 | return netxen_nic_pci_mem_read_direct(adapter, | ||
| 1962 | off, data, size); | ||
| 1963 | } | 1790 | } |
| 1964 | 1791 | ||
| 1792 | return -EIO; | ||
| 1793 | |||
| 1794 | correct: | ||
| 1965 | off8 = off & 0xfffffff8; | 1795 | off8 = off & 0xfffffff8; |
| 1966 | off0[0] = off & 0x7; | 1796 | off0[0] = off & 0x7; |
| 1967 | off0[1] = 0; | 1797 | off0[1] = 0; |
| @@ -1976,17 +1806,14 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, | |||
| 1976 | */ | 1806 | */ |
| 1977 | 1807 | ||
| 1978 | for (i = 0; i < loop; i++) { | 1808 | for (i = 0; i < loop; i++) { |
| 1979 | temp = off8 + (i << 3); | 1809 | writel(off8 + (i << 3), mem_crb + MIU_TEST_AGT_ADDR_LO); |
| 1980 | NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); | 1810 | writel(0, mem_crb + MIU_TEST_AGT_ADDR_HI); |
| 1981 | temp = 0; | 1811 | writel(MIU_TA_CTL_ENABLE, mem_crb + MIU_TEST_AGT_CTRL); |
| 1982 | NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); | 1812 | writel(MIU_TA_CTL_START | MIU_TA_CTL_ENABLE, |
| 1983 | temp = MIU_TA_CTL_ENABLE; | 1813 | mem_crb + MIU_TEST_AGT_CTRL); |
| 1984 | NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp); | ||
| 1985 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; | ||
| 1986 | NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp); | ||
| 1987 | 1814 | ||
| 1988 | for (j = 0; j < MAX_CTL_CHECK; j++) { | 1815 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1989 | temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL); | 1816 | temp = readl(mem_crb + MIU_TEST_AGT_CTRL); |
| 1990 | if ((temp & MIU_TA_CTL_BUSY) == 0) | 1817 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1991 | break; | 1818 | break; |
| 1992 | } | 1819 | } |
| @@ -2001,8 +1828,7 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, | |||
| 2001 | start = off0[i] >> 2; | 1828 | start = off0[i] >> 2; |
| 2002 | end = (off0[i] + sz[i] - 1) >> 2; | 1829 | end = (off0[i] + sz[i] - 1) >> 2; |
| 2003 | for (k = start; k <= end; k++) { | 1830 | for (k = start; k <= end; k++) { |
| 2004 | temp = NXRD32(adapter, | 1831 | temp = readl(mem_crb + MIU_TEST_AGT_RDDATA(k)); |
| 2005 | mem_crb + MIU_TEST_AGT_RDDATA(k)); | ||
| 2006 | word[i] |= ((uint64_t)temp << (32 * k)); | 1832 | word[i] |= ((uint64_t)temp << (32 * k)); |
| 2007 | } | 1833 | } |
| 2008 | } | 1834 | } |
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c index 1399102fa4bd..557e76c4c589 100644 --- a/drivers/net/netxen/netxen_nic_main.c +++ b/drivers/net/netxen/netxen_nic_main.c | |||
| @@ -643,9 +643,10 @@ netxen_setup_pci_map(struct netxen_adapter *adapter) | |||
| 643 | adapter->ahw.ddr_mn_window = 0; | 643 | adapter->ahw.ddr_mn_window = 0; |
| 644 | adapter->ahw.qdr_sn_window = 0; | 644 | adapter->ahw.qdr_sn_window = 0; |
| 645 | 645 | ||
| 646 | adapter->ahw.mn_win_crb = 0x100000 + PCIX_MN_WINDOW + | 646 | adapter->ahw.mn_win_crb = NETXEN_PCI_CRBSPACE + |
| 647 | (pci_func * 0x20); | 647 | 0x100000 + PCIX_MN_WINDOW + (pci_func * 0x20); |
| 648 | adapter->ahw.ms_win_crb = 0x100000 + PCIX_SN_WINDOW; | 648 | adapter->ahw.ms_win_crb = NETXEN_PCI_CRBSPACE + |
| 649 | 0x100000 + PCIX_SN_WINDOW; | ||
| 649 | if (pci_func < 4) | 650 | if (pci_func < 4) |
| 650 | adapter->ahw.ms_win_crb += (pci_func * 0x20); | 651 | adapter->ahw.ms_win_crb += (pci_func * 0x20); |
| 651 | else | 652 | else |
