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authorDhananjay Phadke <dhananjay@netxen.com>2009-04-07 18:50:45 -0400
committerDavid S. Miller <davem@davemloft.net>2009-04-08 18:58:29 -0400
commitf98a9f693b5f4919d9c4085a2fd8d67c7e152f3e (patch)
treeef0acb778f9bdb7fed66de7f099f772ef7af1175 /drivers/net/netxen/netxen_nic_hw.c
parent1fbe63235893e5dce28fe91d8465dd231b0cb3d9 (diff)
netxen: sanitize function names
Replace superfluous wrapper functions with two macros: NXWR32 replaces netxen_nic_reg_write, netxen_nic_write_w0, netxen_nic_read_w1, netxen_crb_writelit_adapter. NXRD32 replaces netxen_nic_reg_read, netxen_nic_read_w0, netxen_nic_read_w1. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/netxen/netxen_nic_hw.c')
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c187
1 files changed, 57 insertions, 130 deletions
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 87cda65ef66b..9439f89869de 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -361,22 +361,20 @@ netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
361 if (adapter->mc_enabled) 361 if (adapter->mc_enabled)
362 return 0; 362 return 0;
363 363
364 val = adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG); 364 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
365 val |= (1UL << (28+port)); 365 val |= (1UL << (28+port));
366 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); 366 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
367 367
368 /* add broadcast addr to filter */ 368 /* add broadcast addr to filter */
369 val = 0xffffff; 369 val = 0xffffff;
370 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 370 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
371 netxen_crb_writelit_adapter(adapter, 371 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
372 NETXEN_UNICAST_ADDR(port, 0)+4, val);
373 372
374 /* add station addr to filter */ 373 /* add station addr to filter */
375 val = MAC_HI(addr); 374 val = MAC_HI(addr);
376 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val); 375 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
377 val = MAC_LO(addr); 376 val = MAC_LO(addr);
378 netxen_crb_writelit_adapter(adapter, 377 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
379 NETXEN_UNICAST_ADDR(port, 1)+4, val);
380 378
381 adapter->mc_enabled = 1; 379 adapter->mc_enabled = 1;
382 return 0; 380 return 0;
@@ -392,18 +390,17 @@ netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
392 if (!adapter->mc_enabled) 390 if (!adapter->mc_enabled)
393 return 0; 391 return 0;
394 392
395 val = adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG); 393 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
396 val &= ~(1UL << (28+port)); 394 val &= ~(1UL << (28+port));
397 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); 395 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
398 396
399 val = MAC_HI(addr); 397 val = MAC_HI(addr);
400 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 398 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
401 val = MAC_LO(addr); 399 val = MAC_LO(addr);
402 netxen_crb_writelit_adapter(adapter, 400 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
403 NETXEN_UNICAST_ADDR(port, 0)+4, val);
404 401
405 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); 402 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
406 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); 403 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
407 404
408 adapter->mc_enabled = 0; 405 adapter->mc_enabled = 0;
409 return 0; 406 return 0;
@@ -419,10 +416,8 @@ netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
419 lo = MAC_LO(addr); 416 lo = MAC_LO(addr);
420 hi = MAC_HI(addr); 417 hi = MAC_HI(addr);
421 418
422 netxen_crb_writelit_adapter(adapter, 419 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
423 NETXEN_MCAST_ADDR(port, index), hi); 420 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
424 netxen_crb_writelit_adapter(adapter,
425 NETXEN_MCAST_ADDR(port, index)+4, lo);
426 421
427 return 0; 422 return 0;
428} 423}
@@ -863,8 +858,8 @@ int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
863 crbaddr = CRB_MAC_BLOCK_START + 858 crbaddr = CRB_MAC_BLOCK_START +
864 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); 859 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
865 860
866 mac_lo = adapter->hw_read_wx(adapter, crbaddr); 861 mac_lo = NXRD32(adapter, crbaddr);
867 mac_hi = adapter->hw_read_wx(adapter, crbaddr+4); 862 mac_hi = NXRD32(adapter, crbaddr+4);
868 863
869 if (pci_func & 1) 864 if (pci_func & 1)
870 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); 865 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
@@ -882,8 +877,7 @@ static int crb_win_lock(struct netxen_adapter *adapter)
882 877
883 while (!done) { 878 while (!done) {
884 /* acquire semaphore3 from PCI HW block */ 879 /* acquire semaphore3 from PCI HW block */
885 done = adapter->hw_read_wx(adapter, 880 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_LOCK));
886 NETXEN_PCIE_REG(PCIE_SEM7_LOCK));
887 if (done == 1) 881 if (done == 1)
888 break; 882 break;
889 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 883 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
@@ -891,8 +885,7 @@ static int crb_win_lock(struct netxen_adapter *adapter)
891 timeout++; 885 timeout++;
892 udelay(1); 886 udelay(1);
893 } 887 }
894 netxen_crb_writelit_adapter(adapter, 888 NXWR32(adapter, NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
895 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
896 return 0; 889 return 0;
897} 890}
898 891
@@ -900,8 +893,7 @@ static void crb_win_unlock(struct netxen_adapter *adapter)
900{ 893{
901 int val; 894 int val;
902 895
903 val = adapter->hw_read_wx(adapter, 896 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK));
904 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK));
905} 897}
906 898
907/* 899/*
@@ -1037,8 +1029,7 @@ netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
1037 dev_info(&pdev->dev, "loading firmware from flash\n"); 1029 dev_info(&pdev->dev, "loading firmware from flash\n");
1038 1030
1039 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 1031 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1040 adapter->hw_write_wx(adapter, 1032 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
1041 NETXEN_ROMUSB_GLB_CAS_RST, 1);
1042 1033
1043 if (fw) { 1034 if (fw) {
1044 __le64 data; 1035 __le64 data;
@@ -1090,13 +1081,10 @@ netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
1090 msleep(1); 1081 msleep(1);
1091 1082
1092 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) 1083 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1093 adapter->hw_write_wx(adapter, 1084 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1094 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1095 else { 1085 else {
1096 adapter->hw_write_wx(adapter, 1086 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1097 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); 1087 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
1098 adapter->hw_write_wx(adapter,
1099 NETXEN_ROMUSB_GLB_CAS_RST, 0);
1100 } 1088 }
1101 1089
1102 return 0; 1090 return 0;
@@ -1154,8 +1142,7 @@ netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname,
1154 if (NETXEN_VERSION_CODE(major, minor, build) > ver) 1142 if (NETXEN_VERSION_CODE(major, minor, build) > ver)
1155 return -EINVAL; 1143 return -EINVAL;
1156 1144
1157 netxen_nic_reg_write(adapter, NETXEN_CAM_RAM(0x1fc), 1145 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
1158 NETXEN_BDINFO_MAGIC);
1159 return 0; 1146 return 0;
1160} 1147}
1161 1148
@@ -1183,8 +1170,7 @@ request_mn:
1183 netxen_rom_fast_read(adapter, 1170 netxen_rom_fast_read(adapter,
1184 NX_FW_VERSION_OFFSET, (int *)&flashed_ver); 1171 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1185 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) { 1172 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1186 capability = adapter->hw_read_wx(adapter, 1173 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
1187 NX_PEG_TUNE_CAPABILITY);
1188 if (capability & NX_PEG_TUNE_MN_PRESENT) { 1174 if (capability & NX_PEG_TUNE_MN_PRESENT) {
1189 fw_type = NX_P3_MN_ROMIMAGE; 1175 fw_type = NX_P3_MN_ROMIMAGE;
1190 goto request_fw; 1176 goto request_fw;
@@ -1332,38 +1318,6 @@ netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1332 return data; 1318 return data;
1333} 1319}
1334 1320
1335void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1336{
1337 adapter->hw_write_wx(adapter, off, val);
1338}
1339
1340int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1341{
1342 return adapter->hw_read_wx(adapter, off);
1343}
1344
1345/* Change the window to 0, write and change back to window 1. */
1346void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1347{
1348 adapter->hw_write_wx(adapter, index, value);
1349}
1350
1351/* Change the window to 0, read and change back to window 1. */
1352u32 netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index)
1353{
1354 return adapter->hw_read_wx(adapter, index);
1355}
1356
1357void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1358{
1359 adapter->hw_write_wx(adapter, index, value);
1360}
1361
1362u32 netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index)
1363{
1364 return adapter->hw_read_wx(adapter, index);
1365}
1366
1367/* 1321/*
1368 * check memory access boundary. 1322 * check memory access boundary.
1369 * used by test agent. support ddr access only for now 1323 * used by test agent. support ddr access only for now
@@ -1475,10 +1429,9 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1475 /* DDR network side */ 1429 /* DDR network side */
1476 window = MN_WIN(addr); 1430 window = MN_WIN(addr);
1477 adapter->ahw.ddr_mn_window = window; 1431 adapter->ahw.ddr_mn_window = window;
1478 adapter->hw_write_wx(adapter, 1432 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1479 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1480 window); 1433 window);
1481 win_read = adapter->hw_read_wx(adapter, 1434 win_read = NXRD32(adapter,
1482 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE); 1435 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1483 if ((win_read << 17) != window) { 1436 if ((win_read << 17) != window) {
1484 printk(KERN_INFO "Written MNwin (0x%x) != " 1437 printk(KERN_INFO "Written MNwin (0x%x) != "
@@ -1494,10 +1447,9 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1494 1447
1495 window = OCM_WIN(addr); 1448 window = OCM_WIN(addr);
1496 adapter->ahw.ddr_mn_window = window; 1449 adapter->ahw.ddr_mn_window = window;
1497 adapter->hw_write_wx(adapter, 1450 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1498 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1499 window); 1451 window);
1500 win_read = adapter->hw_read_wx(adapter, 1452 win_read = NXRD32(adapter,
1501 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE); 1453 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1502 if ((win_read >> 7) != window) { 1454 if ((win_read >> 7) != window) {
1503 printk(KERN_INFO "%s: Written OCMwin (0x%x) != " 1455 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
@@ -1511,10 +1463,9 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1511 /* QDR network side */ 1463 /* QDR network side */
1512 window = MS_WIN(addr); 1464 window = MS_WIN(addr);
1513 adapter->ahw.qdr_sn_window = window; 1465 adapter->ahw.qdr_sn_window = window;
1514 adapter->hw_write_wx(adapter, 1466 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1515 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1516 window); 1467 window);
1517 win_read = adapter->hw_read_wx(adapter, 1468 win_read = NXRD32(adapter,
1518 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE); 1469 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
1519 if (win_read != window) { 1470 if (win_read != window) {
1520 printk(KERN_INFO "%s: Written MSwin (0x%x) != " 1471 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
@@ -1961,27 +1912,20 @@ netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1961 1912
1962 for (i = 0; i < loop; i++) { 1913 for (i = 0; i < loop; i++) {
1963 temp = off8 + (i << 3); 1914 temp = off8 + (i << 3);
1964 adapter->hw_write_wx(adapter, 1915 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1965 mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1966 temp = 0; 1916 temp = 0;
1967 adapter->hw_write_wx(adapter, 1917 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1968 mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1969 temp = word[i] & 0xffffffff; 1918 temp = word[i] & 0xffffffff;
1970 adapter->hw_write_wx(adapter, 1919 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1971 mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1972 temp = (word[i] >> 32) & 0xffffffff; 1920 temp = (word[i] >> 32) & 0xffffffff;
1973 adapter->hw_write_wx(adapter, 1921 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1974 mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1975 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1922 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1976 adapter->hw_write_wx(adapter, 1923 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1977 mem_crb+MIU_TEST_AGT_CTRL, temp);
1978 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1924 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1979 adapter->hw_write_wx(adapter, 1925 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1980 mem_crb+MIU_TEST_AGT_CTRL, temp);
1981 1926
1982 for (j = 0; j < MAX_CTL_CHECK; j++) { 1927 for (j = 0; j < MAX_CTL_CHECK; j++) {
1983 temp = adapter->hw_read_wx(adapter, 1928 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1984 mem_crb + MIU_TEST_AGT_CTRL);
1985 if ((temp & MIU_TA_CTL_BUSY) == 0) 1929 if ((temp & MIU_TA_CTL_BUSY) == 0)
1986 break; 1930 break;
1987 } 1931 }
@@ -2038,21 +1982,16 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2038 1982
2039 for (i = 0; i < loop; i++) { 1983 for (i = 0; i < loop; i++) {
2040 temp = off8 + (i << 3); 1984 temp = off8 + (i << 3);
2041 adapter->hw_write_wx(adapter, 1985 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
2042 mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
2043 temp = 0; 1986 temp = 0;
2044 adapter->hw_write_wx(adapter, 1987 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
2045 mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
2046 temp = MIU_TA_CTL_ENABLE; 1988 temp = MIU_TA_CTL_ENABLE;
2047 adapter->hw_write_wx(adapter, 1989 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
2048 mem_crb + MIU_TEST_AGT_CTRL, temp);
2049 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1990 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
2050 adapter->hw_write_wx(adapter, 1991 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
2051 mem_crb + MIU_TEST_AGT_CTRL, temp);
2052 1992
2053 for (j = 0; j < MAX_CTL_CHECK; j++) { 1993 for (j = 0; j < MAX_CTL_CHECK; j++) {
2054 temp = adapter->hw_read_wx(adapter, 1994 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
2055 mem_crb + MIU_TEST_AGT_CTRL);
2056 if ((temp & MIU_TA_CTL_BUSY) == 0) 1995 if ((temp & MIU_TA_CTL_BUSY) == 0)
2057 break; 1996 break;
2058 } 1997 }
@@ -2067,7 +2006,7 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2067 start = off0[i] >> 2; 2006 start = off0[i] >> 2;
2068 end = (off0[i] + sz[i] - 1) >> 2; 2007 end = (off0[i] + sz[i] - 1) >> 2;
2069 for (k = start; k <= end; k++) { 2008 for (k = start; k <= end; k++) {
2070 temp = adapter->hw_read_wx(adapter, 2009 temp = NXRD32(adapter,
2071 mem_crb + MIU_TEST_AGT_RDDATA(k)); 2010 mem_crb + MIU_TEST_AGT_RDDATA(k));
2072 word[i] |= ((uint64_t)temp << (32 * k)); 2011 word[i] |= ((uint64_t)temp << (32 * k));
2073 } 2012 }
@@ -2111,14 +2050,14 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2111int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, 2050int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2112 u64 off, u32 data) 2051 u64 off, u32 data)
2113{ 2052{
2114 adapter->hw_write_wx(adapter, off, data); 2053 NXWR32(adapter, off, data);
2115 2054
2116 return 0; 2055 return 0;
2117} 2056}
2118 2057
2119u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off) 2058u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2120{ 2059{
2121 return adapter->hw_read_wx(adapter, off); 2060 return NXRD32(adapter, off);
2122} 2061}
2123 2062
2124int netxen_nic_get_board_info(struct netxen_adapter *adapter) 2063int netxen_nic_get_board_info(struct netxen_adapter *adapter)
@@ -2152,8 +2091,7 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2152 adapter->ahw.board_type = board_type; 2091 adapter->ahw.board_type = board_type;
2153 2092
2154 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { 2093 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2155 u32 gpio = netxen_nic_reg_read(adapter, 2094 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2156 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2157 if ((gpio & 0x8000) == 0) 2095 if ((gpio & 0x8000) == 0)
2158 board_type = NETXEN_BRDTYPE_P3_10G_TP; 2096 board_type = NETXEN_BRDTYPE_P3_10G_TP;
2159 } 2097 }
@@ -2205,8 +2143,7 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2205int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) 2143int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2206{ 2144{
2207 new_mtu += MTU_FUDGE_FACTOR; 2145 new_mtu += MTU_FUDGE_FACTOR;
2208 netxen_nic_write_w0(adapter, 2146 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2209 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2210 new_mtu); 2147 new_mtu);
2211 return 0; 2148 return 0;
2212} 2149}
@@ -2215,21 +2152,12 @@ int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2215{ 2152{
2216 new_mtu += MTU_FUDGE_FACTOR; 2153 new_mtu += MTU_FUDGE_FACTOR;
2217 if (adapter->physical_port == 0) 2154 if (adapter->physical_port == 0)
2218 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, 2155 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
2219 new_mtu);
2220 else 2156 else
2221 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, 2157 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
2222 new_mtu);
2223 return 0; 2158 return 0;
2224} 2159}
2225 2160
2226void
2227netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2228 unsigned long off, int data)
2229{
2230 adapter->hw_write_wx(adapter, off, data);
2231}
2232
2233void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) 2161void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2234{ 2162{
2235 __u32 status; 2163 __u32 status;
@@ -2244,8 +2172,7 @@ void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2244 } 2172 }
2245 2173
2246 if (adapter->ahw.port_type == NETXEN_NIC_GBE) { 2174 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2247 port_mode = adapter->hw_read_wx(adapter, 2175 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2248 NETXEN_PORT_MODE_ADDR);
2249 if (port_mode == NETXEN_PORT_MODE_802_3_AP) { 2176 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2250 adapter->link_speed = SPEED_1000; 2177 adapter->link_speed = SPEED_1000;
2251 adapter->link_duplex = DUPLEX_FULL; 2178 adapter->link_duplex = DUPLEX_FULL;
@@ -2322,9 +2249,9 @@ void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2322 addr += sizeof(u32); 2249 addr += sizeof(u32);
2323 } 2250 }
2324 2251
2325 fw_major = adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR); 2252 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2326 fw_minor = adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR); 2253 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2327 fw_build = adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB); 2254 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
2328 2255
2329 adapter->fw_major = fw_major; 2256 adapter->fw_major = fw_major;
2330 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build); 2257 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
@@ -2347,7 +2274,7 @@ void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2347 fw_major, fw_minor, fw_build); 2274 fw_major, fw_minor, fw_build);
2348 2275
2349 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 2276 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2350 i = adapter->hw_read_wx(adapter, NETXEN_MIU_MN_CONTROL); 2277 i = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
2351 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0; 2278 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0;
2352 dev_info(&pdev->dev, "firmware running in %s mode\n", 2279 dev_info(&pdev->dev, "firmware running in %s mode\n",
2353 adapter->ahw.cut_through ? "cut-through" : "legacy"); 2280 adapter->ahw.cut_through ? "cut-through" : "legacy");
@@ -2362,9 +2289,9 @@ netxen_nic_wol_supported(struct netxen_adapter *adapter)
2362 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 2289 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2363 return 0; 2290 return 0;
2364 2291
2365 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV); 2292 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2366 if (wol_cfg & (1UL << adapter->portnum)) { 2293 if (wol_cfg & (1UL << adapter->portnum)) {
2367 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG); 2294 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2368 if (wol_cfg & (1 << adapter->portnum)) 2295 if (wol_cfg & (1 << adapter->portnum))
2369 return 1; 2296 return 1;
2370 } 2297 }