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authorDhananjay Phadke <dhananjay@netxen.com>2008-07-21 22:44:00 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-07-22 17:50:55 -0400
commit7830b22cbc5f5e804469b74a3fe0d3a8ed88ca31 (patch)
treee7779997b1a62f7a4e0003d51132ec710981c258 /drivers/net/netxen/netxen_nic_hw.c
parentf0084a36d4d799c024a5211555334d56c91d236d (diff)
netxen: cleanup unused variables/functions
o Reduce access to global arrays in data path. o Remove duplicate/unused variables, unecessary alignment constraints. o Use correct pci_dev instead of fallback device for consistent allocations. o Disable ethtool set_eeprom functionality for now, it was only used for flashing firmware. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/netxen/netxen_nic_hw.c')
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c270
1 files changed, 62 insertions, 208 deletions
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index c43d06b8de9b..fa6d034c242c 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -43,203 +43,61 @@ struct netxen_recv_crb recv_crb_registers[] = {
43 * Instance 0. 43 * Instance 0.
44 */ 44 */
45 { 45 {
46 /* rcv_desc_crb: */ 46 /* crb_rcv_producer: */
47 { 47 {
48 { 48 NETXEN_NIC_REG(0x100),
49 /* crb_rcv_producer_offset: */ 49 /* Jumbo frames */
50 NETXEN_NIC_REG(0x100), 50 NETXEN_NIC_REG(0x110),
51 /* crb_rcv_consumer_offset: */ 51 /* LRO */
52 NETXEN_NIC_REG(0x104), 52 NETXEN_NIC_REG(0x120)
53 /* crb_gloablrcv_ring: */ 53 },
54 NETXEN_NIC_REG(0x108), 54 /* crb_sts_consumer: */
55 /* crb_rcv_ring_size */ 55 NETXEN_NIC_REG(0x138),
56 NETXEN_NIC_REG(0x10c), 56 },
57
58 },
59 /* Jumbo frames */
60 {
61 /* crb_rcv_producer_offset: */
62 NETXEN_NIC_REG(0x110),
63 /* crb_rcv_consumer_offset: */
64 NETXEN_NIC_REG(0x114),
65 /* crb_gloablrcv_ring: */
66 NETXEN_NIC_REG(0x118),
67 /* crb_rcv_ring_size */
68 NETXEN_NIC_REG(0x11c),
69 },
70 /* LRO */
71 {
72 /* crb_rcv_producer_offset: */
73 NETXEN_NIC_REG(0x120),
74 /* crb_rcv_consumer_offset: */
75 NETXEN_NIC_REG(0x124),
76 /* crb_gloablrcv_ring: */
77 NETXEN_NIC_REG(0x128),
78 /* crb_rcv_ring_size */
79 NETXEN_NIC_REG(0x12c),
80 }
81 },
82 /* crb_rcvstatus_ring: */
83 NETXEN_NIC_REG(0x130),
84 /* crb_rcv_status_producer: */
85 NETXEN_NIC_REG(0x134),
86 /* crb_rcv_status_consumer: */
87 NETXEN_NIC_REG(0x138),
88 /* crb_rcvpeg_state: */
89 NETXEN_NIC_REG(0x13c),
90 /* crb_status_ring_size */
91 NETXEN_NIC_REG(0x140),
92
93 },
94 /* 57 /*
95 * Instance 1, 58 * Instance 1,
96 */ 59 */
97 { 60 {
98 /* rcv_desc_crb: */ 61 /* crb_rcv_producer: */
99 { 62 {
100 { 63 NETXEN_NIC_REG(0x144),
101 /* crb_rcv_producer_offset: */ 64 /* Jumbo frames */
102 NETXEN_NIC_REG(0x144), 65 NETXEN_NIC_REG(0x154),
103 /* crb_rcv_consumer_offset: */ 66 /* LRO */
104 NETXEN_NIC_REG(0x148), 67 NETXEN_NIC_REG(0x164)
105 /* crb_globalrcv_ring: */ 68 },
106 NETXEN_NIC_REG(0x14c), 69 /* crb_sts_consumer: */
107 /* crb_rcv_ring_size */ 70 NETXEN_NIC_REG(0x17c),
108 NETXEN_NIC_REG(0x150), 71 },
109
110 },
111 /* Jumbo frames */
112 {
113 /* crb_rcv_producer_offset: */
114 NETXEN_NIC_REG(0x154),
115 /* crb_rcv_consumer_offset: */
116 NETXEN_NIC_REG(0x158),
117 /* crb_globalrcv_ring: */
118 NETXEN_NIC_REG(0x15c),
119 /* crb_rcv_ring_size */
120 NETXEN_NIC_REG(0x160),
121 },
122 /* LRO */
123 {
124 /* crb_rcv_producer_offset: */
125 NETXEN_NIC_REG(0x164),
126 /* crb_rcv_consumer_offset: */
127 NETXEN_NIC_REG(0x168),
128 /* crb_globalrcv_ring: */
129 NETXEN_NIC_REG(0x16c),
130 /* crb_rcv_ring_size */
131 NETXEN_NIC_REG(0x170),
132 }
133
134 },
135 /* crb_rcvstatus_ring: */
136 NETXEN_NIC_REG(0x174),
137 /* crb_rcv_status_producer: */
138 NETXEN_NIC_REG(0x178),
139 /* crb_rcv_status_consumer: */
140 NETXEN_NIC_REG(0x17c),
141 /* crb_rcvpeg_state: */
142 NETXEN_NIC_REG(0x180),
143 /* crb_status_ring_size */
144 NETXEN_NIC_REG(0x184),
145 },
146 /* 72 /*
147 * Instance 2, 73 * Instance 2,
148 */ 74 */
149 { 75 {
150 { 76 /* crb_rcv_producer: */
151 { 77 {
152 /* crb_rcv_producer_offset: */ 78 NETXEN_NIC_REG(0x1d8),
153 NETXEN_NIC_REG(0x1d8), 79 /* Jumbo frames */
154 /* crb_rcv_consumer_offset: */ 80 NETXEN_NIC_REG(0x1f8),
155 NETXEN_NIC_REG(0x1dc), 81 /* LRO */
156 /* crb_gloablrcv_ring: */ 82 NETXEN_NIC_REG(0x208)
157 NETXEN_NIC_REG(0x1f0), 83 },
158 /* crb_rcv_ring_size */ 84 /* crb_sts_consumer: */
159 NETXEN_NIC_REG(0x1f4), 85 NETXEN_NIC_REG(0x220),
160 },
161 /* Jumbo frames */
162 {
163 /* crb_rcv_producer_offset: */
164 NETXEN_NIC_REG(0x1f8),
165 /* crb_rcv_consumer_offset: */
166 NETXEN_NIC_REG(0x1fc),
167 /* crb_gloablrcv_ring: */
168 NETXEN_NIC_REG(0x200),
169 /* crb_rcv_ring_size */
170 NETXEN_NIC_REG(0x204),
171 },
172 /* LRO */
173 {
174 /* crb_rcv_producer_offset: */
175 NETXEN_NIC_REG(0x208),
176 /* crb_rcv_consumer_offset: */
177 NETXEN_NIC_REG(0x20c),
178 /* crb_gloablrcv_ring: */
179 NETXEN_NIC_REG(0x210),
180 /* crb_rcv_ring_size */
181 NETXEN_NIC_REG(0x214),
182 }
183 },
184 /* crb_rcvstatus_ring: */
185 NETXEN_NIC_REG(0x218),
186 /* crb_rcv_status_producer: */
187 NETXEN_NIC_REG(0x21c),
188 /* crb_rcv_status_consumer: */
189 NETXEN_NIC_REG(0x220),
190 /* crb_rcvpeg_state: */
191 NETXEN_NIC_REG(0x224),
192 /* crb_status_ring_size */
193 NETXEN_NIC_REG(0x228),
194 }, 86 },
195 /* 87 /*
196 * Instance 3, 88 * Instance 3,
197 */ 89 */
198 { 90 {
199 { 91 /* crb_rcv_producer: */
200 { 92 {
201 /* crb_rcv_producer_offset: */ 93 NETXEN_NIC_REG(0x22c),
202 NETXEN_NIC_REG(0x22c), 94 /* Jumbo frames */
203 /* crb_rcv_consumer_offset: */ 95 NETXEN_NIC_REG(0x23c),
204 NETXEN_NIC_REG(0x230), 96 /* LRO */
205 /* crb_gloablrcv_ring: */ 97 NETXEN_NIC_REG(0x24c)
206 NETXEN_NIC_REG(0x234), 98 },
207 /* crb_rcv_ring_size */ 99 /* crb_sts_consumer: */
208 NETXEN_NIC_REG(0x238), 100 NETXEN_NIC_REG(0x264),
209 },
210 /* Jumbo frames */
211 {
212 /* crb_rcv_producer_offset: */
213 NETXEN_NIC_REG(0x23c),
214 /* crb_rcv_consumer_offset: */
215 NETXEN_NIC_REG(0x240),
216 /* crb_gloablrcv_ring: */
217 NETXEN_NIC_REG(0x244),
218 /* crb_rcv_ring_size */
219 NETXEN_NIC_REG(0x248),
220 },
221 /* LRO */
222 {
223 /* crb_rcv_producer_offset: */
224 NETXEN_NIC_REG(0x24c),
225 /* crb_rcv_consumer_offset: */
226 NETXEN_NIC_REG(0x250),
227 /* crb_gloablrcv_ring: */
228 NETXEN_NIC_REG(0x254),
229 /* crb_rcv_ring_size */
230 NETXEN_NIC_REG(0x258),
231 }
232 },
233 /* crb_rcvstatus_ring: */
234 NETXEN_NIC_REG(0x25c),
235 /* crb_rcv_status_producer: */
236 NETXEN_NIC_REG(0x260),
237 /* crb_rcv_status_consumer: */
238 NETXEN_NIC_REG(0x264),
239 /* crb_rcvpeg_state: */
240 NETXEN_NIC_REG(0x268),
241 /* crb_status_ring_size */
242 NETXEN_NIC_REG(0x26c),
243 }, 101 },
244}; 102};
245 103
@@ -375,16 +233,12 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
375 loops = 0; 233 loops = 0;
376 state = 0; 234 state = 0;
377 /* Window 1 call */ 235 /* Window 1 call */
378 state = readl(NETXEN_CRB_NORMALIZE(adapter, 236 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_RCVPEG_STATE));
379 recv_crb_registers[ctx].
380 crb_rcvpeg_state));
381 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) { 237 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
382 msleep(1); 238 msleep(1);
383 /* Window 1 call */ 239 /* Window 1 call */
384 state = readl(NETXEN_CRB_NORMALIZE(adapter, 240 state = readl(NETXEN_CRB_NORMALIZE(adapter,
385 recv_crb_registers 241 CRB_RCVPEG_STATE));
386 [ctx].
387 crb_rcvpeg_state));
388 loops++; 242 loops++;
389 } 243 }
390 if (loops >= 20) { 244 if (loops >= 20) {
@@ -399,11 +253,9 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
399 adapter->msi_mode = readl( 253 adapter->msi_mode = readl(
400 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW)); 254 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW));
401 255
402 addr = netxen_alloc(adapter->ahw.pdev, 256 addr = pci_alloc_consistent(adapter->pdev,
403 sizeof(struct netxen_ring_ctx) + 257 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
404 sizeof(uint32_t), 258 &adapter->ctx_desc_phys_addr);
405 (dma_addr_t *) & adapter->ctx_desc_phys_addr,
406 &adapter->ctx_desc_pdev);
407 259
408 if (addr == NULL) { 260 if (addr == NULL) {
409 DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); 261 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
@@ -419,11 +271,10 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
419 adapter->cmd_consumer = (__le32 *) (((char *)addr) + 271 adapter->cmd_consumer = (__le32 *) (((char *)addr) +
420 sizeof(struct netxen_ring_ctx)); 272 sizeof(struct netxen_ring_ctx));
421 273
422 addr = netxen_alloc(adapter->ahw.pdev, 274 addr = pci_alloc_consistent(adapter->pdev,
423 sizeof(struct cmd_desc_type0) * 275 sizeof(struct cmd_desc_type0) *
424 adapter->max_tx_desc_count, 276 adapter->max_tx_desc_count,
425 (dma_addr_t *) & hw->cmd_desc_phys_addr, 277 &hw->cmd_desc_phys_addr);
426 &adapter->ahw.cmd_desc_pdev);
427 278
428 if (addr == NULL) { 279 if (addr == NULL) {
429 DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); 280 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
@@ -443,10 +294,9 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
443 294
444 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { 295 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
445 rcv_desc = &recv_ctx->rcv_desc[ring]; 296 rcv_desc = &recv_ctx->rcv_desc[ring];
446 addr = netxen_alloc(adapter->ahw.pdev, 297 addr = pci_alloc_consistent(adapter->pdev,
447 RCV_DESC_RINGSIZE, 298 RCV_DESC_RINGSIZE,
448 &rcv_desc->phys_addr, 299 &rcv_desc->phys_addr);
449 &rcv_desc->phys_pdev);
450 if (addr == NULL) { 300 if (addr == NULL) {
451 DPRINTK(ERR, "bad return from " 301 DPRINTK(ERR, "bad return from "
452 "pci_alloc_consistent\n"); 302 "pci_alloc_consistent\n");
@@ -459,11 +309,13 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
459 cpu_to_le64(rcv_desc->phys_addr); 309 cpu_to_le64(rcv_desc->phys_addr);
460 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size = 310 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
461 cpu_to_le32(rcv_desc->max_rx_desc_count); 311 cpu_to_le32(rcv_desc->max_rx_desc_count);
312 rcv_desc->crb_rcv_producer =
313 recv_crb_registers[adapter->portnum].
314 crb_rcv_producer[ring];
462 } 315 }
463 316
464 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE, 317 addr = pci_alloc_consistent(adapter->pdev, STATUS_DESC_RINGSIZE,
465 &recv_ctx->rcv_status_desc_phys_addr, 318 &recv_ctx->rcv_status_desc_phys_addr);
466 &recv_ctx->rcv_status_desc_pdev);
467 if (addr == NULL) { 319 if (addr == NULL) {
468 DPRINTK(ERR, "bad return from" 320 DPRINTK(ERR, "bad return from"
469 " pci_alloc_consistent\n"); 321 " pci_alloc_consistent\n");
@@ -476,6 +328,8 @@ int netxen_nic_hw_resources(struct netxen_adapter *adapter)
476 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr); 328 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
477 adapter->ctx_desc->sts_ring_size = 329 adapter->ctx_desc->sts_ring_size =
478 cpu_to_le32(adapter->max_rx_desc_count); 330 cpu_to_le32(adapter->max_rx_desc_count);
331 recv_ctx->crb_sts_consumer =
332 recv_crb_registers[adapter->portnum].crb_sts_consumer;
479 333
480 } 334 }
481 /* Window = 1 */ 335 /* Window = 1 */
@@ -496,7 +350,7 @@ void netxen_free_hw_resources(struct netxen_adapter *adapter)
496 int ctx, ring; 350 int ctx, ring;
497 351
498 if (adapter->ctx_desc != NULL) { 352 if (adapter->ctx_desc != NULL) {
499 pci_free_consistent(adapter->ctx_desc_pdev, 353 pci_free_consistent(adapter->pdev,
500 sizeof(struct netxen_ring_ctx) + 354 sizeof(struct netxen_ring_ctx) +
501 sizeof(uint32_t), 355 sizeof(uint32_t),
502 adapter->ctx_desc, 356 adapter->ctx_desc,
@@ -505,7 +359,7 @@ void netxen_free_hw_resources(struct netxen_adapter *adapter)
505 } 359 }
506 360
507 if (adapter->ahw.cmd_desc_head != NULL) { 361 if (adapter->ahw.cmd_desc_head != NULL) {
508 pci_free_consistent(adapter->ahw.cmd_desc_pdev, 362 pci_free_consistent(adapter->pdev,
509 sizeof(struct cmd_desc_type0) * 363 sizeof(struct cmd_desc_type0) *
510 adapter->max_tx_desc_count, 364 adapter->max_tx_desc_count,
511 adapter->ahw.cmd_desc_head, 365 adapter->ahw.cmd_desc_head,
@@ -519,7 +373,7 @@ void netxen_free_hw_resources(struct netxen_adapter *adapter)
519 rcv_desc = &recv_ctx->rcv_desc[ring]; 373 rcv_desc = &recv_ctx->rcv_desc[ring];
520 374
521 if (rcv_desc->desc_head != NULL) { 375 if (rcv_desc->desc_head != NULL) {
522 pci_free_consistent(rcv_desc->phys_pdev, 376 pci_free_consistent(adapter->pdev,
523 RCV_DESC_RINGSIZE, 377 RCV_DESC_RINGSIZE,
524 rcv_desc->desc_head, 378 rcv_desc->desc_head,
525 rcv_desc->phys_addr); 379 rcv_desc->phys_addr);
@@ -528,7 +382,7 @@ void netxen_free_hw_resources(struct netxen_adapter *adapter)
528 } 382 }
529 383
530 if (recv_ctx->rcv_status_desc_head != NULL) { 384 if (recv_ctx->rcv_status_desc_head != NULL) {
531 pci_free_consistent(recv_ctx->rcv_status_desc_pdev, 385 pci_free_consistent(adapter->pdev,
532 STATUS_DESC_RINGSIZE, 386 STATUS_DESC_RINGSIZE,
533 recv_ctx->rcv_status_desc_head, 387 recv_ctx->rcv_status_desc_head,
534 recv_ctx-> 388 recv_ctx->
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 12:22:15 -0500