diff options
author | Dhananjay Phadke <dhananjay@netxen.com> | 2009-08-24 15:23:26 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-08-26 18:29:17 -0400 |
commit | c9517e5893db03ca8bd32b8783b39af58176947c (patch) | |
tree | 5ae4d26af6f38e70a868e634d0576056c326027e /drivers/net/netxen/netxen_nic_hdr.h | |
parent | cb7e4b6e37144f5d131ee09296be3c21c41f28d8 (diff) |
netxen: implement generic pcie semaphore functions
Implement common function for locking/unlocking 8 hardware
semaphores used for serializing access to shared resouces
on a NIC board by different PCI functions.
As by definition, callers of these semaphore API can be
put to sleep till the semaphore is locked.
Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/netxen/netxen_nic_hdr.h')
-rw-r--r-- | drivers/net/netxen/netxen_nic_hdr.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h index c4a4a8ba14f4..92f5970c9aa9 100644 --- a/drivers/net/netxen/netxen_nic_hdr.h +++ b/drivers/net/netxen/netxen_nic_hdr.h | |||
@@ -899,16 +899,24 @@ enum { | |||
899 | 899 | ||
900 | #define PCIE_DCR 0x00d8 | 900 | #define PCIE_DCR 0x00d8 |
901 | 901 | ||
902 | #define PCIE_SEM0_LOCK (0x1c000) | ||
903 | #define PCIE_SEM0_UNLOCK (0x1c004) | ||
904 | #define PCIE_SEM1_LOCK (0x1c008) | ||
905 | #define PCIE_SEM1_UNLOCK (0x1c00c) | ||
902 | #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ | 906 | #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ |
903 | #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ | 907 | #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ |
904 | #define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */ | 908 | #define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */ |
905 | #define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */ | 909 | #define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */ |
910 | #define PCIE_SEM4_LOCK (0x1c020) | ||
911 | #define PCIE_SEM4_UNLOCK (0x1c024) | ||
906 | #define PCIE_SEM5_LOCK (0x1c028) /* API lock */ | 912 | #define PCIE_SEM5_LOCK (0x1c028) /* API lock */ |
907 | #define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */ | 913 | #define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */ |
908 | #define PCIE_SEM6_LOCK (0x1c030) /* sw lock */ | 914 | #define PCIE_SEM6_LOCK (0x1c030) /* sw lock */ |
909 | #define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */ | 915 | #define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */ |
910 | #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ | 916 | #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ |
911 | #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/ | 917 | #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/ |
918 | #define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N)) | ||
919 | #define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N)) | ||
912 | 920 | ||
913 | #define PCIE_SETUP_FUNCTION (0x12040) | 921 | #define PCIE_SETUP_FUNCTION (0x12040) |
914 | #define PCIE_SETUP_FUNCTION2 (0x12048) | 922 | #define PCIE_SETUP_FUNCTION2 (0x12048) |