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authorDhananjay Phadke <dhananjay@netxen.com>2009-01-14 23:47:30 -0500
committerDavid S. Miller <davem@davemloft.net>2009-01-14 23:47:30 -0500
commit2edbb454428729f450f7a0aabbf95ac62b46b78a (patch)
tree392ae07f3448897ceff4717663af7584eccbd375 /drivers/net/netxen/netxen_nic.h
parentd1d5e6b1cead3df6f722d1d458874bd7f93da8d6 (diff)
netxen: fix endianness in firmware commands
o Set restricted (little endian) data types in firmware command requests and responses. o Remove unnecessary conversion to LE when writing registers. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/netxen/netxen_nic.h')
-rw-r--r--drivers/net/netxen/netxen_nic.h98
1 files changed, 49 insertions, 49 deletions
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index f8e601c51da7..31311cc66d18 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -995,31 +995,31 @@ struct netxen_recv_context {
995 */ 995 */
996 996
997typedef struct { 997typedef struct {
998 u64 host_phys_addr; /* Ring base addr */ 998 __le64 host_phys_addr; /* Ring base addr */
999 u32 ring_size; /* Ring entries */ 999 __le32 ring_size; /* Ring entries */
1000 u16 msi_index; 1000 __le16 msi_index;
1001 u16 rsvd; /* Padding */ 1001 __le16 rsvd; /* Padding */
1002} nx_hostrq_sds_ring_t; 1002} nx_hostrq_sds_ring_t;
1003 1003
1004typedef struct { 1004typedef struct {
1005 u64 host_phys_addr; /* Ring base addr */ 1005 __le64 host_phys_addr; /* Ring base addr */
1006 u64 buff_size; /* Packet buffer size */ 1006 __le64 buff_size; /* Packet buffer size */
1007 u32 ring_size; /* Ring entries */ 1007 __le32 ring_size; /* Ring entries */
1008 u32 ring_kind; /* Class of ring */ 1008 __le32 ring_kind; /* Class of ring */
1009} nx_hostrq_rds_ring_t; 1009} nx_hostrq_rds_ring_t;
1010 1010
1011typedef struct { 1011typedef struct {
1012 u64 host_rsp_dma_addr; /* Response dma'd here */ 1012 __le64 host_rsp_dma_addr; /* Response dma'd here */
1013 u32 capabilities[4]; /* Flag bit vector */ 1013 __le32 capabilities[4]; /* Flag bit vector */
1014 u32 host_int_crb_mode; /* Interrupt crb usage */ 1014 __le32 host_int_crb_mode; /* Interrupt crb usage */
1015 u32 host_rds_crb_mode; /* RDS crb usage */ 1015 __le32 host_rds_crb_mode; /* RDS crb usage */
1016 /* These ring offsets are relative to data[0] below */ 1016 /* These ring offsets are relative to data[0] below */
1017 u32 rds_ring_offset; /* Offset to RDS config */ 1017 __le32 rds_ring_offset; /* Offset to RDS config */
1018 u32 sds_ring_offset; /* Offset to SDS config */ 1018 __le32 sds_ring_offset; /* Offset to SDS config */
1019 u16 num_rds_rings; /* Count of RDS rings */ 1019 __le16 num_rds_rings; /* Count of RDS rings */
1020 u16 num_sds_rings; /* Count of SDS rings */ 1020 __le16 num_sds_rings; /* Count of SDS rings */
1021 u16 rsvd1; /* Padding */ 1021 __le16 rsvd1; /* Padding */
1022 u16 rsvd2; /* Padding */ 1022 __le16 rsvd2; /* Padding */
1023 u8 reserved[128]; /* reserve space for future expansion*/ 1023 u8 reserved[128]; /* reserve space for future expansion*/
1024 /* MUST BE 64-bit aligned. 1024 /* MUST BE 64-bit aligned.
1025 The following is packed: 1025 The following is packed:
@@ -1029,24 +1029,24 @@ typedef struct {
1029} nx_hostrq_rx_ctx_t; 1029} nx_hostrq_rx_ctx_t;
1030 1030
1031typedef struct { 1031typedef struct {
1032 u32 host_producer_crb; /* Crb to use */ 1032 __le32 host_producer_crb; /* Crb to use */
1033 u32 rsvd1; /* Padding */ 1033 __le32 rsvd1; /* Padding */
1034} nx_cardrsp_rds_ring_t; 1034} nx_cardrsp_rds_ring_t;
1035 1035
1036typedef struct { 1036typedef struct {
1037 u32 host_consumer_crb; /* Crb to use */ 1037 __le32 host_consumer_crb; /* Crb to use */
1038 u32 interrupt_crb; /* Crb to use */ 1038 __le32 interrupt_crb; /* Crb to use */
1039} nx_cardrsp_sds_ring_t; 1039} nx_cardrsp_sds_ring_t;
1040 1040
1041typedef struct { 1041typedef struct {
1042 /* These ring offsets are relative to data[0] below */ 1042 /* These ring offsets are relative to data[0] below */
1043 u32 rds_ring_offset; /* Offset to RDS config */ 1043 __le32 rds_ring_offset; /* Offset to RDS config */
1044 u32 sds_ring_offset; /* Offset to SDS config */ 1044 __le32 sds_ring_offset; /* Offset to SDS config */
1045 u32 host_ctx_state; /* Starting State */ 1045 __le32 host_ctx_state; /* Starting State */
1046 u32 num_fn_per_port; /* How many PCI fn share the port */ 1046 __le32 num_fn_per_port; /* How many PCI fn share the port */
1047 u16 num_rds_rings; /* Count of RDS rings */ 1047 __le16 num_rds_rings; /* Count of RDS rings */
1048 u16 num_sds_rings; /* Count of SDS rings */ 1048 __le16 num_sds_rings; /* Count of SDS rings */
1049 u16 context_id; /* Handle for context */ 1049 __le16 context_id; /* Handle for context */
1050 u8 phys_port; /* Physical id of port */ 1050 u8 phys_port; /* Physical id of port */
1051 u8 virt_port; /* Virtual/Logical id of port */ 1051 u8 virt_port; /* Virtual/Logical id of port */
1052 u8 reserved[128]; /* save space for future expansion */ 1052 u8 reserved[128]; /* save space for future expansion */
@@ -1072,34 +1072,34 @@ typedef struct {
1072 */ 1072 */
1073 1073
1074typedef struct { 1074typedef struct {
1075 u64 host_phys_addr; /* Ring base addr */ 1075 __le64 host_phys_addr; /* Ring base addr */
1076 u32 ring_size; /* Ring entries */ 1076 __le32 ring_size; /* Ring entries */
1077 u32 rsvd; /* Padding */ 1077 __le32 rsvd; /* Padding */
1078} nx_hostrq_cds_ring_t; 1078} nx_hostrq_cds_ring_t;
1079 1079
1080typedef struct { 1080typedef struct {
1081 u64 host_rsp_dma_addr; /* Response dma'd here */ 1081 __le64 host_rsp_dma_addr; /* Response dma'd here */
1082 u64 cmd_cons_dma_addr; /* */ 1082 __le64 cmd_cons_dma_addr; /* */
1083 u64 dummy_dma_addr; /* */ 1083 __le64 dummy_dma_addr; /* */
1084 u32 capabilities[4]; /* Flag bit vector */ 1084 __le32 capabilities[4]; /* Flag bit vector */
1085 u32 host_int_crb_mode; /* Interrupt crb usage */ 1085 __le32 host_int_crb_mode; /* Interrupt crb usage */
1086 u32 rsvd1; /* Padding */ 1086 __le32 rsvd1; /* Padding */
1087 u16 rsvd2; /* Padding */ 1087 __le16 rsvd2; /* Padding */
1088 u16 interrupt_ctl; 1088 __le16 interrupt_ctl;
1089 u16 msi_index; 1089 __le16 msi_index;
1090 u16 rsvd3; /* Padding */ 1090 __le16 rsvd3; /* Padding */
1091 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */ 1091 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
1092 u8 reserved[128]; /* future expansion */ 1092 u8 reserved[128]; /* future expansion */
1093} nx_hostrq_tx_ctx_t; 1093} nx_hostrq_tx_ctx_t;
1094 1094
1095typedef struct { 1095typedef struct {
1096 u32 host_producer_crb; /* Crb to use */ 1096 __le32 host_producer_crb; /* Crb to use */
1097 u32 interrupt_crb; /* Crb to use */ 1097 __le32 interrupt_crb; /* Crb to use */
1098} nx_cardrsp_cds_ring_t; 1098} nx_cardrsp_cds_ring_t;
1099 1099
1100typedef struct { 1100typedef struct {
1101 u32 host_ctx_state; /* Starting state */ 1101 __le32 host_ctx_state; /* Starting state */
1102 u16 context_id; /* Handle for context */ 1102 __le16 context_id; /* Handle for context */
1103 u8 phys_port; /* Physical id of port */ 1103 u8 phys_port; /* Physical id of port */
1104 u8 virt_port; /* Virtual/Logical id of port */ 1104 u8 virt_port; /* Virtual/Logical id of port */
1105 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */ 1105 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
@@ -1202,9 +1202,9 @@ enum {
1202#define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 1202#define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1203 1203
1204typedef struct { 1204typedef struct {
1205 u64 qhdr; 1205 __le64 qhdr;
1206 u64 req_hdr; 1206 __le64 req_hdr;
1207 u64 words[6]; 1207 __le64 words[6];
1208} nx_nic_req_t; 1208} nx_nic_req_t;
1209 1209
1210typedef struct { 1210typedef struct {