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authorDale Farnsworth <dale@farnsworth.org>2006-03-03 12:03:36 -0500
committerJeff Garzik <jeff@garzik.org>2006-03-03 12:12:36 -0500
commit7303fde88a149c4cee54dae7e46d1895fa7214b4 (patch)
tree394af13d130346d095c0830a48e3e421decf6b86 /drivers/net/mv643xx_eth.h
parentff561eef9fb37c7180085e08418acfc009a9ada7 (diff)
[PATCH] mv643xx_eth: Move #defines of constants to mv643xx_eth.h
Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/mv643xx_eth.h')
-rw-r--r--drivers/net/mv643xx_eth.h47
1 files changed, 33 insertions, 14 deletions
diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h
index cade2705423c..2e59f193e267 100644
--- a/drivers/net/mv643xx_eth.h
+++ b/drivers/net/mv643xx_eth.h
@@ -74,21 +74,40 @@
74#define MV643XX_RX_COAL 100 74#define MV643XX_RX_COAL 100
75#endif 75#endif
76 76
77/* 77#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
78 * The second part is the low level driver of the gigE ethernet ports. 78#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
79 */ 79#else
80#define MAX_DESCS_PER_SKB 1
81#endif
80 82
81/* 83#define ETH_VLAN_HLEN 4
82 * Header File for : MV-643xx network interface header 84#define ETH_FCS_LEN 4
83 * 85#define ETH_DMA_ALIGN 8 /* hw requires 8-byte alignment */
84 * DESCRIPTION: 86#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
85 * This header file contains macros typedefs and function declaration for 87#define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
86 * the Marvell Gig Bit Ethernet Controller. 88 ETH_VLAN_HLEN + ETH_FCS_LEN)
87 * 89#define ETH_RX_SKB_SIZE ((dev->mtu + ETH_WRAPPER_LEN + 7) & ~0x7)
88 * DEPENDENCIES: 90
89 * None. 91#define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
90 * 92#define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
91 */ 93
94#define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
95#define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
96#define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
97#define ETH_INT_CAUSE_EXT 0x00000002
98#define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
99
100#define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
101#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
102#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
103#define ETH_INT_CAUSE_PHY 0x00010000
104#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY)
105
106#define ETH_INT_MASK_ALL 0x00000000
107#define ETH_INT_MASK_ALL_EXT 0x00000000
108
109#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
110#define PHY_WAIT_MICRO_SECONDS 10
92 111
93/* Buffer offset from buffer pointer */ 112/* Buffer offset from buffer pointer */
94#define RX_BUF_OFFSET 0x2 113#define RX_BUF_OFFSET 0x2