diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2008-07-14 20:15:24 -0400 |
---|---|---|
committer | Lennert Buytenhek <buytenh@marvell.com> | 2008-07-24 00:22:51 -0400 |
commit | ae9ae06443f7bfa4f013c0e2c035d549e999ad3e (patch) | |
tree | 464b7e9f5bc9225d6944d4d484cf44f468c56f91 /drivers/net/mv643xx_eth.c | |
parent | 65193a91fc60fdb79e392c9842c10552a1fa3e1c (diff) |
mv643xx_eth: also check TX_IN_PROGRESS when disabling transmit path
The recommended sequence for waiting for the transmit path to clear
after disabling all of the transmit queues is to wait for the
TX_FIFO_EMPTY bit in the Port Status register to become set as well
as the TX_IN_PROGRESS bit to clear.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'drivers/net/mv643xx_eth.c')
-rw-r--r-- | drivers/net/mv643xx_eth.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 207d4391a6de..c700c1f494e9 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c | |||
@@ -90,6 +90,7 @@ static char mv643xx_eth_driver_version[] = "1.1"; | |||
90 | #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) | 90 | #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) |
91 | #define PORT_STATUS(p) (0x0444 + ((p) << 10)) | 91 | #define PORT_STATUS(p) (0x0444 + ((p) << 10)) |
92 | #define TX_FIFO_EMPTY 0x00000400 | 92 | #define TX_FIFO_EMPTY 0x00000400 |
93 | #define TX_IN_PROGRESS 0x00000080 | ||
93 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) | 94 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) |
94 | #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10)) | 95 | #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10)) |
95 | #define TX_BW_RATE(p) (0x0450 + ((p) << 10)) | 96 | #define TX_BW_RATE(p) (0x0450 + ((p) << 10)) |
@@ -2039,8 +2040,14 @@ static void port_reset(struct mv643xx_eth_private *mp) | |||
2039 | if (mp->txq_mask & (1 << i)) | 2040 | if (mp->txq_mask & (1 << i)) |
2040 | txq_disable(mp->txq + i); | 2041 | txq_disable(mp->txq + i); |
2041 | } | 2042 | } |
2042 | while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY)) | 2043 | |
2044 | while (1) { | ||
2045 | u32 ps = rdl(mp, PORT_STATUS(mp->port_num)); | ||
2046 | |||
2047 | if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) | ||
2048 | break; | ||
2043 | udelay(10); | 2049 | udelay(10); |
2050 | } | ||
2044 | 2051 | ||
2045 | /* Reset the Enable bit in the Configuration Register */ | 2052 | /* Reset the Enable bit in the Configuration Register */ |
2046 | data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); | 2053 | data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); |