aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/mlx4/mr.c
diff options
context:
space:
mode:
authorVladimir Sokolovsky <vlad@mellanox.co.il>2008-09-02 16:38:29 -0400
committerRoland Dreier <rolandd@cisco.com>2008-09-02 16:38:29 -0400
commitc9257433f2eaf8803a1f3d3be5d984232db41ffe (patch)
tree20d09185709dee8aad0f9bb7738724184b3a1f14 /drivers/net/mlx4/mr.c
parent1941246dd98089dd637f44d3bd4f6cc1c61aa9e4 (diff)
mlx4_core: Set RAE and init mtt_sz field in FRMR MPT entries
Set the RAE (remote access enable) bit and correctly initialize the MTT size in MPT entries being set up for fast register memory regions. Otherwise the callers can't enable remote access and in fact can't fast register at all (since the HCA will think no MTT entries are allocated). Signed-off-by: Vladimir Sokolovsky <vlad@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/net/mlx4/mr.c')
-rw-r--r--drivers/net/mlx4/mr.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/net/mlx4/mr.c b/drivers/net/mlx4/mr.c
index 62071d9c4a55..644adf074a35 100644
--- a/drivers/net/mlx4/mr.c
+++ b/drivers/net/mlx4/mr.c
@@ -67,7 +67,8 @@ struct mlx4_mpt_entry {
67#define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 67#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
68#define MLX4_MPT_FLAG_REGION (1 << 8) 68#define MLX4_MPT_FLAG_REGION (1 << 8)
69 69
70#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 26) 70#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
71#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
71#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 72#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
72 73
73#define MLX4_MTT_FLAG_PRESENT 1 74#define MLX4_MTT_FLAG_PRESENT 1
@@ -348,7 +349,10 @@ int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
348 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) { 349 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
349 /* fast register MR in free state */ 350 /* fast register MR in free state */
350 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE); 351 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
351 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG); 352 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
353 MLX4_MPT_PD_FLAG_RAE);
354 mpt_entry->mtt_sz = cpu_to_be32((1 << mr->mtt.order) *
355 MLX4_MTT_ENTRY_PER_SEG);
352 } else { 356 } else {
353 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS); 357 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
354 } 358 }