diff options
author | Yevgeny Petrilin <yevgenyp@mellanox.co.il> | 2009-08-06 22:28:18 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-08-06 22:28:18 -0400 |
commit | 9f519f68cfffba022978634f724944a0b971fec1 (patch) | |
tree | dec840b3dfd1bd3173c12686e85a62466a82202b /drivers/net/mlx4/en_resources.c | |
parent | b6b912e0804dc1b3e856da3cc82fbe78b50e968c (diff) |
mlx4_en: Not using Shared Receive Queues
We use 1:1 mapping between QPs and SRQs on receive side,
so additional indirection level not required. Allocated the receive
buffers for the RSS QPs.
Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/mlx4/en_resources.c')
-rw-r--r-- | drivers/net/mlx4/en_resources.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/net/mlx4/en_resources.c b/drivers/net/mlx4/en_resources.c index 65ca706c04bb..16256784a943 100644 --- a/drivers/net/mlx4/en_resources.c +++ b/drivers/net/mlx4/en_resources.c | |||
@@ -37,7 +37,7 @@ | |||
37 | #include "mlx4_en.h" | 37 | #include "mlx4_en.h" |
38 | 38 | ||
39 | void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, | 39 | void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, |
40 | int is_tx, int rss, int qpn, int cqn, int srqn, | 40 | int is_tx, int rss, int qpn, int cqn, |
41 | struct mlx4_qp_context *context) | 41 | struct mlx4_qp_context *context) |
42 | { | 42 | { |
43 | struct mlx4_en_dev *mdev = priv->mdev; | 43 | struct mlx4_en_dev *mdev = priv->mdev; |
@@ -46,11 +46,12 @@ void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, | |||
46 | context->flags = cpu_to_be32(7 << 16 | rss << 13); | 46 | context->flags = cpu_to_be32(7 << 16 | rss << 13); |
47 | context->pd = cpu_to_be32(mdev->priv_pdn); | 47 | context->pd = cpu_to_be32(mdev->priv_pdn); |
48 | context->mtu_msgmax = 0xff; | 48 | context->mtu_msgmax = 0xff; |
49 | context->rq_size_stride = 0; | 49 | if (!is_tx && !rss) |
50 | context->rq_size_stride = ilog2(size) << 3 | (ilog2(stride) - 4); | ||
50 | if (is_tx) | 51 | if (is_tx) |
51 | context->sq_size_stride = ilog2(size) << 3 | (ilog2(stride) - 4); | 52 | context->sq_size_stride = ilog2(size) << 3 | (ilog2(stride) - 4); |
52 | else | 53 | else |
53 | context->sq_size_stride = 1; | 54 | context->sq_size_stride = ilog2(TXBB_SIZE) - 4; |
54 | context->usr_page = cpu_to_be32(mdev->priv_uar.index); | 55 | context->usr_page = cpu_to_be32(mdev->priv_uar.index); |
55 | context->local_qpn = cpu_to_be32(qpn); | 56 | context->local_qpn = cpu_to_be32(qpn); |
56 | context->pri_path.ackto = 1 & 0x07; | 57 | context->pri_path.ackto = 1 & 0x07; |
@@ -59,8 +60,6 @@ void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, | |||
59 | context->cqn_send = cpu_to_be32(cqn); | 60 | context->cqn_send = cpu_to_be32(cqn); |
60 | context->cqn_recv = cpu_to_be32(cqn); | 61 | context->cqn_recv = cpu_to_be32(cqn); |
61 | context->db_rec_addr = cpu_to_be64(priv->res.db.dma << 2); | 62 | context->db_rec_addr = cpu_to_be64(priv->res.db.dma << 2); |
62 | if (!rss) | ||
63 | context->srqn = cpu_to_be32(MLX4_EN_USE_SRQ | srqn); | ||
64 | } | 63 | } |
65 | 64 | ||
66 | 65 | ||