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authorEli Cohen <eli@dev.mellanox.co.il>2008-04-17 00:09:33 -0400
committerRoland Dreier <rolandd@cisco.com>2008-04-17 00:09:33 -0400
commit3fdcb97f0b8d8a29117dc36acd0b15965d2a2160 (patch)
treea8bad6e48e9654f10e1b8ebfde3b086d83d2756e /drivers/net/mlx4/cq.c
parent28d52b3cd8d48ef0ff77d4a8a7a21fc2816bb0a5 (diff)
IB/mlx4: Add support for modifying CQ moderation parameters
Signed-off-by: Eli Cohen <eli@mellnaox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/net/mlx4/cq.c')
-rw-r--r--drivers/net/mlx4/cq.c44
1 files changed, 37 insertions, 7 deletions
diff --git a/drivers/net/mlx4/cq.c b/drivers/net/mlx4/cq.c
index d4441fee3d80..8c314341434f 100644
--- a/drivers/net/mlx4/cq.c
+++ b/drivers/net/mlx4/cq.c
@@ -38,6 +38,7 @@
38#include <linux/hardirq.h> 38#include <linux/hardirq.h>
39 39
40#include <linux/mlx4/cmd.h> 40#include <linux/mlx4/cmd.h>
41#include <linux/mlx4/cq.h>
41 42
42#include "mlx4.h" 43#include "mlx4.h"
43#include "icm.h" 44#include "icm.h"
@@ -47,21 +48,19 @@ struct mlx4_cq_context {
47 u16 reserved1[3]; 48 u16 reserved1[3];
48 __be16 page_offset; 49 __be16 page_offset;
49 __be32 logsize_usrpage; 50 __be32 logsize_usrpage;
50 u8 reserved2; 51 __be16 cq_period;
51 u8 cq_period; 52 __be16 cq_max_count;
52 u8 reserved3; 53 u8 reserved2[3];
53 u8 cq_max_count;
54 u8 reserved4[3];
55 u8 comp_eqn; 54 u8 comp_eqn;
56 u8 log_page_size; 55 u8 log_page_size;
57 u8 reserved5[2]; 56 u8 reserved3[2];
58 u8 mtt_base_addr_h; 57 u8 mtt_base_addr_h;
59 __be32 mtt_base_addr_l; 58 __be32 mtt_base_addr_l;
60 __be32 last_notified_index; 59 __be32 last_notified_index;
61 __be32 solicit_producer_index; 60 __be32 solicit_producer_index;
62 __be32 consumer_index; 61 __be32 consumer_index;
63 __be32 producer_index; 62 __be32 producer_index;
64 u32 reserved6[2]; 63 u32 reserved4[2];
65 __be64 db_rec_addr; 64 __be64 db_rec_addr;
66}; 65};
67 66
@@ -121,6 +120,13 @@ static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
121 MLX4_CMD_TIME_CLASS_A); 120 MLX4_CMD_TIME_CLASS_A);
122} 121}
123 122
123static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
124 int cq_num, u32 opmod)
125{
126 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
127 MLX4_CMD_TIME_CLASS_A);
128}
129
124static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 130static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
125 int cq_num) 131 int cq_num)
126{ 132{
@@ -129,6 +135,30 @@ static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
129 MLX4_CMD_TIME_CLASS_A); 135 MLX4_CMD_TIME_CLASS_A);
130} 136}
131 137
138int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
139 u16 count, u16 period)
140{
141 struct mlx4_cmd_mailbox *mailbox;
142 struct mlx4_cq_context *cq_context;
143 int err;
144
145 mailbox = mlx4_alloc_cmd_mailbox(dev);
146 if (IS_ERR(mailbox))
147 return PTR_ERR(mailbox);
148
149 cq_context = mailbox->buf;
150 memset(cq_context, 0, sizeof *cq_context);
151
152 cq_context->cq_max_count = cpu_to_be16(count);
153 cq_context->cq_period = cpu_to_be16(period);
154
155 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
156
157 mlx4_free_cmd_mailbox(dev, mailbox);
158 return err;
159}
160EXPORT_SYMBOL_GPL(mlx4_cq_modify);
161
132int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 162int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
133 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq) 163 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq)
134{ 164{