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authorJames Morris <jmorris@namei.org>2011-04-19 07:32:41 -0400
committerJames Morris <jmorris@namei.org>2011-04-19 07:32:41 -0400
commitd4ab4e6a23f805abb8fc3cc34525eec3788aeca1 (patch)
treeeefd82c155bc27469a85667d759cd90facf4a6e3 /drivers/net/meth.h
parentc0fa797ae6cd02ff87c0bfe0d509368a3b45640e (diff)
parent96fd2d57b8252e16dfacf8941f7a74a6119197f5 (diff)
Merge branch 'master'; commit 'v2.6.39-rc3' into next
Diffstat (limited to 'drivers/net/meth.h')
-rw-r--r--drivers/net/meth.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/meth.h b/drivers/net/meth.h
index a78dc1ca8c29..5b145c6bad60 100644
--- a/drivers/net/meth.h
+++ b/drivers/net/meth.h
@@ -144,7 +144,7 @@ typedef struct rx_packet {
144 /* Bits 22 through 28 are used to determine IPGR2 */ 144 /* Bits 22 through 28 are used to determine IPGR2 */
145 145
146#define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */ 146#define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */
147 /* 000: Inital revision */ 147 /* 000: Initial revision */
148 /* 001: First revision, Improved TX concatenation */ 148 /* 001: First revision, Improved TX concatenation */
149 149
150 150
@@ -193,7 +193,7 @@ typedef struct rx_packet {
193 /* 1: A TX message had the INT request bit set, the packet has been sent. */ 193 /* 1: A TX message had the INT request bit set, the packet has been sent. */
194#define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */ 194#define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */
195#define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */ 195#define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */
196 /* 1: A memory error occurred durring DMA, DMA stopped, Fatal */ 196 /* 1: A memory error occurred during DMA, DMA stopped, Fatal */
197#define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */ 197#define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */
198#define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */ 198#define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */
199#define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */ 199#define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */