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authorDavid S. Miller <davem@davemloft.net>2010-04-08 02:28:28 -0400
committerDavid S. Miller <davem@davemloft.net>2010-04-08 02:28:28 -0400
commit4d8dc679084d8dd7b81b2ae245844246deb0759c (patch)
tree1cac100df1e9cb8e569abc87bf39fa311da76e26 /drivers/net/ll_temac_main.c
parent97f8aefbbfb5aa5c9944e5fa8149f1fdaf71c7b6 (diff)
Revert "Add non-Virtex5 support for LL TEMAC driver"
This reverts commit 459569145516f7967b916c57445feb02c600668c. Uses virt_to_bus() and breaks the build. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ll_temac_main.c')
-rw-r--r--drivers/net/ll_temac_main.c137
1 files changed, 33 insertions, 104 deletions
diff --git a/drivers/net/ll_temac_main.c b/drivers/net/ll_temac_main.c
index b6edb2fd0a8a..30474d6b15c3 100644
--- a/drivers/net/ll_temac_main.c
+++ b/drivers/net/ll_temac_main.c
@@ -20,6 +20,9 @@
20 * or rx, so this should be okay. 20 * or rx, so this should be okay.
21 * 21 *
22 * TODO: 22 * TODO:
23 * - Fix driver to work on more than just Virtex5. Right now the driver
24 * assumes that the locallink DMA registers are accessed via DCR
25 * instructions.
23 * - Factor out locallink DMA code into separate driver 26 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment. 27 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming. 28 * - Fix support for hardware checksumming.
@@ -112,86 +115,17 @@ void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
112 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg); 115 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
113} 116}
114 117
115/**
116 * temac_dma_in32 - Memory mapped DMA read, this function expects a
117 * register input that is based on DCR word addresses which
118 * are then converted to memory mapped byte addresses
119 */
120static u32 temac_dma_in32(struct temac_local *lp, int reg) 118static u32 temac_dma_in32(struct temac_local *lp, int reg)
121{ 119{
122 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
123}
124
125/**
126 * temac_dma_out32 - Memory mapped DMA read, this function expects a
127 * register input that is based on DCR word addresses which
128 * are then converted to memory mapped byte addresses
129 */
130static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
131{
132 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
133}
134
135/* DMA register access functions can be DCR based or memory mapped.
136 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
137 * memory mapped.
138 */
139#ifdef CONFIG_PPC_DCR
140
141/**
142 * temac_dma_dcr_in32 - DCR based DMA read
143 */
144static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
145{
146 return dcr_read(lp->sdma_dcrs, reg); 120 return dcr_read(lp->sdma_dcrs, reg);
147} 121}
148 122
149/** 123static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
150 * temac_dma_dcr_out32 - DCR based DMA write
151 */
152static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
153{ 124{
154 dcr_write(lp->sdma_dcrs, reg, value); 125 dcr_write(lp->sdma_dcrs, reg, value);
155} 126}
156 127
157/** 128/**
158 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
159 * I/O functions
160 */
161static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
162 struct device_node *np)
163{
164 unsigned int dcrs;
165
166 /* setup the dcr address mapping if it's in the device tree */
167
168 dcrs = dcr_resource_start(np, 0);
169 if (dcrs != 0) {
170 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
171 lp->dma_in = temac_dma_dcr_in;
172 lp->dma_out = temac_dma_dcr_out;
173 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
174 return 0;
175 }
176 /* no DCR in the device tree, indicate a failure */
177 return -1;
178}
179
180#else
181
182/*
183 * temac_dcr_setup - This is a stub for when DCR is not supported,
184 * such as with MicroBlaze
185 */
186static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
187 struct device_node *np)
188{
189 return -1;
190}
191
192#endif
193
194/**
195 * temac_dma_bd_init - Setup buffer descriptor rings 129 * temac_dma_bd_init - Setup buffer descriptor rings
196 */ 130 */
197static int temac_dma_bd_init(struct net_device *ndev) 131static int temac_dma_bd_init(struct net_device *ndev)
@@ -221,14 +155,14 @@ static int temac_dma_bd_init(struct net_device *ndev)
221 lp->rx_bd_v[i].next = lp->rx_bd_p + 155 lp->rx_bd_v[i].next = lp->rx_bd_p +
222 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM); 156 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
223 157
224 skb = netdev_alloc_skb_ip_align(ndev, 158 skb = alloc_skb(XTE_MAX_JUMBO_FRAME_SIZE
225 XTE_MAX_JUMBO_FRAME_SIZE); 159 + XTE_ALIGN, GFP_ATOMIC);
226
227 if (skb == 0) { 160 if (skb == 0) {
228 dev_err(&ndev->dev, "alloc_skb error %d\n", i); 161 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
229 return -1; 162 return -1;
230 } 163 }
231 lp->rx_skb[i] = skb; 164 lp->rx_skb[i] = skb;
165 skb_reserve(skb, BUFFER_ALIGN(skb->data));
232 /* returns physical address of skb->data */ 166 /* returns physical address of skb->data */
233 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent, 167 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
234 skb->data, 168 skb->data,
@@ -238,23 +172,23 @@ static int temac_dma_bd_init(struct net_device *ndev)
238 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND; 172 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
239 } 173 }
240 174
241 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 | 175 temac_dma_out32(lp, TX_CHNL_CTRL, 0x10220400 |
242 CHNL_CTRL_IRQ_EN | 176 CHNL_CTRL_IRQ_EN |
243 CHNL_CTRL_IRQ_DLY_EN | 177 CHNL_CTRL_IRQ_DLY_EN |
244 CHNL_CTRL_IRQ_COAL_EN); 178 CHNL_CTRL_IRQ_COAL_EN);
245 /* 0x10220483 */ 179 /* 0x10220483 */
246 /* 0x00100483 */ 180 /* 0x00100483 */
247 lp->dma_out(lp, RX_CHNL_CTRL, 0xff010000 | 181 temac_dma_out32(lp, RX_CHNL_CTRL, 0xff010000 |
248 CHNL_CTRL_IRQ_EN | 182 CHNL_CTRL_IRQ_EN |
249 CHNL_CTRL_IRQ_DLY_EN | 183 CHNL_CTRL_IRQ_DLY_EN |
250 CHNL_CTRL_IRQ_COAL_EN | 184 CHNL_CTRL_IRQ_COAL_EN |
251 CHNL_CTRL_IRQ_IOE); 185 CHNL_CTRL_IRQ_IOE);
252 /* 0xff010283 */ 186 /* 0xff010283 */
253 187
254 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p); 188 temac_dma_out32(lp, RX_CURDESC_PTR, lp->rx_bd_p);
255 lp->dma_out(lp, RX_TAILDESC_PTR, 189 temac_dma_out32(lp, RX_TAILDESC_PTR,
256 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1))); 190 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
257 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p); 191 temac_dma_out32(lp, TX_CURDESC_PTR, lp->tx_bd_p);
258 192
259 return 0; 193 return 0;
260} 194}
@@ -492,9 +426,9 @@ static void temac_device_reset(struct net_device *ndev)
492 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK); 426 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
493 427
494 /* Reset Local Link (DMA) */ 428 /* Reset Local Link (DMA) */
495 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST); 429 temac_dma_out32(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
496 timeout = 1000; 430 timeout = 1000;
497 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) { 431 while (temac_dma_in32(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
498 udelay(1); 432 udelay(1);
499 if (--timeout == 0) { 433 if (--timeout == 0) {
500 dev_err(&ndev->dev, 434 dev_err(&ndev->dev,
@@ -502,7 +436,7 @@ static void temac_device_reset(struct net_device *ndev)
502 break; 436 break;
503 } 437 }
504 } 438 }
505 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE); 439 temac_dma_out32(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
506 440
507 temac_dma_bd_init(ndev); 441 temac_dma_bd_init(ndev);
508 442
@@ -663,7 +597,7 @@ static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
663 lp->tx_bd_tail = 0; 597 lp->tx_bd_tail = 0;
664 598
665 /* Kick off the transfer */ 599 /* Kick off the transfer */
666 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */ 600 temac_dma_out32(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
667 601
668 return NETDEV_TX_OK; 602 return NETDEV_TX_OK;
669} 603}
@@ -705,15 +639,16 @@ static void ll_temac_recv(struct net_device *ndev)
705 ndev->stats.rx_packets++; 639 ndev->stats.rx_packets++;
706 ndev->stats.rx_bytes += length; 640 ndev->stats.rx_bytes += length;
707 641
708 new_skb = netdev_alloc_skb_ip_align(ndev, 642 new_skb = alloc_skb(XTE_MAX_JUMBO_FRAME_SIZE + XTE_ALIGN,
709 XTE_MAX_JUMBO_FRAME_SIZE); 643 GFP_ATOMIC);
710
711 if (new_skb == 0) { 644 if (new_skb == 0) {
712 dev_err(&ndev->dev, "no memory for new sk_buff\n"); 645 dev_err(&ndev->dev, "no memory for new sk_buff\n");
713 spin_unlock_irqrestore(&lp->rx_lock, flags); 646 spin_unlock_irqrestore(&lp->rx_lock, flags);
714 return; 647 return;
715 } 648 }
716 649
650 skb_reserve(new_skb, BUFFER_ALIGN(new_skb->data));
651
717 cur_p->app0 = STS_CTRL_APP0_IRQONEND; 652 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
718 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data, 653 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
719 XTE_MAX_JUMBO_FRAME_SIZE, 654 XTE_MAX_JUMBO_FRAME_SIZE,
@@ -728,7 +663,7 @@ static void ll_temac_recv(struct net_device *ndev)
728 cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; 663 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
729 bdstat = cur_p->app0; 664 bdstat = cur_p->app0;
730 } 665 }
731 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p); 666 temac_dma_out32(lp, RX_TAILDESC_PTR, tail_p);
732 667
733 spin_unlock_irqrestore(&lp->rx_lock, flags); 668 spin_unlock_irqrestore(&lp->rx_lock, flags);
734} 669}
@@ -739,8 +674,8 @@ static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
739 struct temac_local *lp = netdev_priv(ndev); 674 struct temac_local *lp = netdev_priv(ndev);
740 unsigned int status; 675 unsigned int status;
741 676
742 status = lp->dma_in(lp, TX_IRQ_REG); 677 status = temac_dma_in32(lp, TX_IRQ_REG);
743 lp->dma_out(lp, TX_IRQ_REG, status); 678 temac_dma_out32(lp, TX_IRQ_REG, status);
744 679
745 if (status & (IRQ_COAL | IRQ_DLY)) 680 if (status & (IRQ_COAL | IRQ_DLY))
746 temac_start_xmit_done(lp->ndev); 681 temac_start_xmit_done(lp->ndev);
@@ -757,8 +692,8 @@ static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
757 unsigned int status; 692 unsigned int status;
758 693
759 /* Read and clear the status registers */ 694 /* Read and clear the status registers */
760 status = lp->dma_in(lp, RX_IRQ_REG); 695 status = temac_dma_in32(lp, RX_IRQ_REG);
761 lp->dma_out(lp, RX_IRQ_REG, status); 696 temac_dma_out32(lp, RX_IRQ_REG, status);
762 697
763 if (status & (IRQ_COAL | IRQ_DLY)) 698 if (status & (IRQ_COAL | IRQ_DLY))
764 ll_temac_recv(lp->ndev); 699 ll_temac_recv(lp->ndev);
@@ -859,7 +794,7 @@ static ssize_t temac_show_llink_regs(struct device *dev,
859 int i, len = 0; 794 int i, len = 0;
860 795
861 for (i = 0; i < 0x11; i++) 796 for (i = 0; i < 0x11; i++)
862 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i), 797 len += sprintf(buf + len, "%.8x%s", temac_dma_in32(lp, i),
863 (i % 8) == 7 ? "\n" : " "); 798 (i % 8) == 7 ? "\n" : " ");
864 len += sprintf(buf + len, "\n"); 799 len += sprintf(buf + len, "\n");
865 800
@@ -885,6 +820,7 @@ temac_of_probe(struct of_device *op, const struct of_device_id *match)
885 struct net_device *ndev; 820 struct net_device *ndev;
886 const void *addr; 821 const void *addr;
887 int size, rc = 0; 822 int size, rc = 0;
823 unsigned int dcrs;
888 824
889 /* Init network device structure */ 825 /* Init network device structure */
890 ndev = alloc_etherdev(sizeof(*lp)); 826 ndev = alloc_etherdev(sizeof(*lp));
@@ -934,20 +870,13 @@ temac_of_probe(struct of_device *op, const struct of_device_id *match)
934 goto nodev; 870 goto nodev;
935 } 871 }
936 872
937 /* Setup the DMA register accesses, could be DCR or memory mapped */ 873 dcrs = dcr_resource_start(np, 0);
938 if (temac_dcr_setup(lp, op, np)) { 874 if (dcrs == 0) {
939 875 dev_err(&op->dev, "could not get DMA register address\n");
940 /* no DCR in the device tree, try non-DCR */ 876 goto nodev;
941 lp->sdma_regs = of_iomap(np, 0);
942 if (lp->sdma_regs) {
943 lp->dma_in = temac_dma_in32;
944 lp->dma_out = temac_dma_out32;
945 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
946 } else {
947 dev_err(&op->dev, "unable to map DMA registers\n");
948 goto nodev;
949 }
950 } 877 }
878 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
879 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
951 880
952 lp->rx_irq = irq_of_parse_and_map(np, 0); 881 lp->rx_irq = irq_of_parse_and_map(np, 0);
953 lp->tx_irq = irq_of_parse_and_map(np, 1); 882 lp->tx_irq = irq_of_parse_and_map(np, 1);