jme: Added half-duplex mode and IPv6 RSS fix

1. Set bit 5 of GPREG1 to 1 to enable hardware workaround for half-duplex
   mode. Which the MAC processor generates CRS/COL by itself instead of
   receive it from PHY processor.

2. Set bit 6 of GPREG1 to 1 to enable hardware workaround that masks the
   MAC processor working right while calculating IPv6 RSS in 10/100
   mode.

3. Group the workaround codes all together.

Signed-off-by: Guo-Fu Tseng <cooldavid@cooldavid.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 30 insertions, 0 deletions

diff --git a/drivers/net/jme.h b/drivers/net/jme.h
index b29688431a6d..9fdf20a9a820 100644
--- a/drivers/net/jme.h
+++ b/drivers/net/jme.h
@@ -964,6 +964,36 @@ enum jme_gpreg0_vals {
 };
 
 /*
+ * General Purpose REG-1
+ * Note: All theses bits defined here are for
+ *       Chip mode revision 0x11 only
+ */
+enum jme_gpreg1_masks {
+        GPREG1_INTRDELAYUNIT    = 0x00000018,
+        GPREG1_INTRDELAYENABLE  = 0x00000007,
+};
+
+enum jme_gpreg1_vals {
+        GPREG1_RSSPATCH         = 0x00000040,
+        GPREG1_HALFMODEPATCH    = 0x00000020,
+
+        GPREG1_INTDLYUNIT_16NS  = 0x00000000,
+        GPREG1_INTDLYUNIT_256NS = 0x00000008,
+        GPREG1_INTDLYUNIT_1US   = 0x00000010,
+        GPREG1_INTDLYUNIT_16US  = 0x00000018,
+
+        GPREG1_INTDLYEN_1U      = 0x00000001,
+        GPREG1_INTDLYEN_2U      = 0x00000002,
+        GPREG1_INTDLYEN_3U      = 0x00000003,
+        GPREG1_INTDLYEN_4U      = 0x00000004,
+        GPREG1_INTDLYEN_5U      = 0x00000005,
+        GPREG1_INTDLYEN_6U      = 0x00000006,
+        GPREG1_INTDLYEN_7U      = 0x00000007,
+
+        GPREG1_DEFAULT          = 0x00000000,
+};
+
+/*
  * Interrupt Status Bits
  */
 enum jme_interrupt_bits {