jme: GHC register control fix for new hardware

Due to the hardware design, except the first chip on the market,
other chips needs to setup the clock source for MAC processor
implicitly through Global Host Control Register(GHC).
(Strange design huh?)

10/100M uses the PCI-E as clock source, and 1G uses GPHY.

And I reordered the code a little, to make it easier to read.

Found-by: "Ethan" <ethanhsiao@jmicron.com>
Fixed-by: "akeemting" <akeem@jmicron.com>
Signed-off-by: "Guo-Fu Tseng" <cooldavid@cooldavid.org>
Acked-by: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 21 insertions, 7 deletions

diff --git a/drivers/net/jme.h b/drivers/net/jme.h
index f863aee6648b..adaf3ddbf783 100644
--- a/drivers/net/jme.h
+++ b/drivers/net/jme.h
@@ -815,16 +815,30 @@ static inline u32 smi_phy_addr(int x)
  * Global Host Control
  */
 enum jme_ghc_bit_mask {
-        GHC_SWRST       = 0x40000000,
-        GHC_DPX         = 0x00000040,
-        GHC_SPEED       = 0x00000030,
-        GHC_LINK_POLL   = 0x00000001,
+        GHC_SWRST               = 0x40000000,
+        GHC_DPX                 = 0x00000040,
+        GHC_SPEED               = 0x00000030,
+        GHC_LINK_POLL           = 0x00000001,
 };
 
 enum jme_ghc_speed_val {
-        GHC_SPEED_10M   = 0x00000010,
-        GHC_SPEED_100M  = 0x00000020,
-        GHC_SPEED_1000M = 0x00000030,
+        GHC_SPEED_10M           = 0x00000010,
+        GHC_SPEED_100M          = 0x00000020,
+        GHC_SPEED_1000M         = 0x00000030,
+};
+
+enum jme_ghc_to_clk {
+        GHC_TO_CLK_OFF          = 0x00000000,
+        GHC_TO_CLK_GPHY         = 0x00400000,
+        GHC_TO_CLK_PCIE         = 0x00800000,
+        GHC_TO_CLK_INVALID      = 0x00C00000,
+};
+
+enum jme_ghc_txmac_clk {
+        GHC_TXMAC_CLK_OFF       = 0x00000000,
+        GHC_TXMAC_CLK_GPHY      = 0x00100000,
+        GHC_TXMAC_CLK_PCIE      = 0x00200000,
+        GHC_TXMAC_CLK_INVALID   = 0x00300000,
 };
 
 /*