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authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-02 10:55:08 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-02 10:55:08 -0500
commit6d6b89bd2e316b78d668f761d380837b81fa71ef (patch)
tree7e63c58611fc6181153526abbdafdd846ed1a19d /drivers/net/ixgbevf
parent13dda80e48439b446d0bc9bab34b91484bc8f533 (diff)
parent2507c05ff55fbf38326b08ed27eaed233bc75042 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1341 commits) virtio_net: remove forgotten assignment be2net: fix tx completion polling sis190: fix cable detect via link status poll net: fix protocol sk_buff field bridge: Fix build error when IGMP_SNOOPING is not enabled bnx2x: Tx barriers and locks scm: Only support SCM_RIGHTS on unix domain sockets. vhost-net: restart tx poll on sk_sndbuf full vhost: fix get_user_pages_fast error handling vhost: initialize log eventfd context pointer vhost: logging thinko fix wireless: convert to use netdev_for_each_mc_addr ethtool: do not set some flags, if others failed ipoib: returned back addrlen check for mc addresses netlink: Adding inode field to /proc/net/netlink axnet_cs: add new id bridge: Make IGMP snooping depend upon BRIDGE. bridge: Add multicast count/interval sysfs entries bridge: Add hash elasticity/max sysfs entries bridge: Add multicast_snooping sysfs toggle ... Trivial conflicts in Documentation/feature-removal-schedule.txt
Diffstat (limited to 'drivers/net/ixgbevf')
-rw-r--r--drivers/net/ixgbevf/Makefile38
-rw-r--r--drivers/net/ixgbevf/defines.h292
-rw-r--r--drivers/net/ixgbevf/ethtool.c716
-rw-r--r--drivers/net/ixgbevf/ixgbevf.h318
-rw-r--r--drivers/net/ixgbevf/ixgbevf_main.c3578
-rw-r--r--drivers/net/ixgbevf/mbx.c341
-rw-r--r--drivers/net/ixgbevf/mbx.h100
-rw-r--r--drivers/net/ixgbevf/regs.h85
-rw-r--r--drivers/net/ixgbevf/vf.c387
-rw-r--r--drivers/net/ixgbevf/vf.h168
10 files changed, 6023 insertions, 0 deletions
diff --git a/drivers/net/ixgbevf/Makefile b/drivers/net/ixgbevf/Makefile
new file mode 100644
index 000000000000..dd4e0d27e8cc
--- /dev/null
+++ b/drivers/net/ixgbevf/Makefile
@@ -0,0 +1,38 @@
1################################################################################
2#
3# Intel 82599 Virtual Function driver
4# Copyright(c) 1999 - 2009 Intel Corporation.
5#
6# This program is free software; you can redistribute it and/or modify it
7# under the terms and conditions of the GNU General Public License,
8# version 2, as published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13# more details.
14#
15# You should have received a copy of the GNU General Public License along with
16# this program; if not, write to the Free Software Foundation, Inc.,
17# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18#
19# The full GNU General Public License is included in this distribution in
20# the file called "COPYING".
21#
22# Contact Information:
23# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25#
26################################################################################
27
28#
29# Makefile for the Intel(R) 82599 VF ethernet driver
30#
31
32obj-$(CONFIG_IXGBEVF) += ixgbevf.o
33
34ixgbevf-objs := vf.o \
35 mbx.o \
36 ethtool.o \
37 ixgbevf_main.o
38
diff --git a/drivers/net/ixgbevf/defines.h b/drivers/net/ixgbevf/defines.h
new file mode 100644
index 000000000000..c44fdb05447a
--- /dev/null
+++ b/drivers/net/ixgbevf/defines.h
@@ -0,0 +1,292 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBEVF_DEFINES_H_
29#define _IXGBEVF_DEFINES_H_
30
31/* Device IDs */
32#define IXGBE_DEV_ID_82599_VF 0x10ED
33
34#define IXGBE_VF_IRQ_CLEAR_MASK 7
35#define IXGBE_VF_MAX_TX_QUEUES 1
36#define IXGBE_VF_MAX_RX_QUEUES 1
37#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
38
39/* Link speed */
40typedef u32 ixgbe_link_speed;
41#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
42#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
43
44#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
45#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
46#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
47#define IXGBE_LINKS_UP 0x40000000
48#define IXGBE_LINKS_SPEED 0x20000000
49
50/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
51#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
52#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
53#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
54
55/* Interrupt Vector Allocation Registers */
56#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
57
58#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
59
60/* Receive Config masks */
61#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
62#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
63#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
64#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
65
66/* DCA Control */
67#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
68
69/* PSRTYPE bit definitions */
70#define IXGBE_PSRTYPE_TCPHDR 0x00000010
71#define IXGBE_PSRTYPE_UDPHDR 0x00000020
72#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
73#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
74#define IXGBE_PSRTYPE_L2HDR 0x00001000
75
76/* SRRCTL bit definitions */
77#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
78#define IXGBE_SRRCTL_RDMTS_SHIFT 22
79#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
80#define IXGBE_SRRCTL_DROP_EN 0x10000000
81#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
82#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
83#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
84#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
85#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
86#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
87#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
88#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
89
90/* Receive Descriptor bit definitions */
91#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
92#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
93#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
94#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
95#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
96#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
97#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
98#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
99#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
100#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
101#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
102#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
103#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
104#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
105#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
106#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
107#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
108#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
109#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
110#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
111#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
112#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
113#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
114#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
115#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
116#define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */
117#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
118#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
119#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
120#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
121#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
122#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
123#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
124#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
125#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
126#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
127#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
128#define IXGBE_RXD_PRI_SHIFT 13
129#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
130#define IXGBE_RXD_CFI_SHIFT 12
131
132#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
133#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
134#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
135#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
136#define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */
137#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
138#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
139#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
140#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
141#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
142#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
143
144#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
145#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
146#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
147#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
148#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
149#define IXGBE_RXDADV_RSCCNT_SHIFT 17
150#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
151#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
152#define IXGBE_RXDADV_SPH 0x8000
153
154#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
155 IXGBE_RXD_ERR_CE | \
156 IXGBE_RXD_ERR_LE | \
157 IXGBE_RXD_ERR_PE | \
158 IXGBE_RXD_ERR_OSE | \
159 IXGBE_RXD_ERR_USE)
160
161#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
162 IXGBE_RXDADV_ERR_CE | \
163 IXGBE_RXDADV_ERR_LE | \
164 IXGBE_RXDADV_ERR_PE | \
165 IXGBE_RXDADV_ERR_OSE | \
166 IXGBE_RXDADV_ERR_USE)
167
168#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
169#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
170#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
171#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
172#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
173#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
174#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
175#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
176#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
177
178/* Transmit Descriptor - Advanced */
179union ixgbe_adv_tx_desc {
180 struct {
181 __le64 buffer_addr; /* Address of descriptor's data buf */
182 __le32 cmd_type_len;
183 __le32 olinfo_status;
184 } read;
185 struct {
186 __le64 rsvd; /* Reserved */
187 __le32 nxtseq_seed;
188 __le32 status;
189 } wb;
190};
191
192/* Receive Descriptor - Advanced */
193union ixgbe_adv_rx_desc {
194 struct {
195 __le64 pkt_addr; /* Packet buffer address */
196 __le64 hdr_addr; /* Header buffer address */
197 } read;
198 struct {
199 struct {
200 union {
201 __le32 data;
202 struct {
203 __le16 pkt_info; /* RSS, Pkt type */
204 __le16 hdr_info; /* Splithdr, hdrlen */
205 } hs_rss;
206 } lo_dword;
207 union {
208 __le32 rss; /* RSS Hash */
209 struct {
210 __le16 ip_id; /* IP id */
211 __le16 csum; /* Packet Checksum */
212 } csum_ip;
213 } hi_dword;
214 } lower;
215 struct {
216 __le32 status_error; /* ext status/error */
217 __le16 length; /* Packet length */
218 __le16 vlan; /* VLAN tag */
219 } upper;
220 } wb; /* writeback */
221};
222
223/* Context descriptors */
224struct ixgbe_adv_tx_context_desc {
225 __le32 vlan_macip_lens;
226 __le32 seqnum_seed;
227 __le32 type_tucmd_mlhl;
228 __le32 mss_l4len_idx;
229};
230
231/* Adv Transmit Descriptor Config Masks */
232#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
233#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
234#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
235#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
236#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
237#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
238#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
239#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
240#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
241#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
242#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
243#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
244#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
245#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
246#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
247#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
248#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
249#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
250 IXGBE_ADVTXD_POPTS_SHIFT)
251#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
252 IXGBE_ADVTXD_POPTS_SHIFT)
253#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
254#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
255#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
256#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
257#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
258
259/* Interrupt register bitmasks */
260
261/* Extended Interrupt Cause Read */
262#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
263#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
264#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
265
266/* Extended Interrupt Cause Set */
267#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
268#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
269#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
270
271/* Extended Interrupt Mask Set */
272#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
273#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
274#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
275
276/* Extended Interrupt Mask Clear */
277#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
278#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
279#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
280
281#define IXGBE_EIMS_ENABLE_MASK ( \
282 IXGBE_EIMS_RTX_QUEUE | \
283 IXGBE_EIMS_MAILBOX | \
284 IXGBE_EIMS_OTHER)
285
286#define IXGBE_EITR_CNT_WDIS 0x80000000
287
288/* Error Codes */
289#define IXGBE_ERR_INVALID_MAC_ADDR -1
290#define IXGBE_ERR_RESET_FAILED -2
291
292#endif /* _IXGBEVF_DEFINES_H_ */
diff --git a/drivers/net/ixgbevf/ethtool.c b/drivers/net/ixgbevf/ethtool.c
new file mode 100644
index 000000000000..399be0c34c36
--- /dev/null
+++ b/drivers/net/ixgbevf/ethtool.c
@@ -0,0 +1,716 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbevf */
29
30#include <linux/types.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/ethtool.h>
35#include <linux/vmalloc.h>
36#include <linux/if_vlan.h>
37#include <linux/uaccess.h>
38
39#include "ixgbevf.h"
40
41#define IXGBE_ALL_RAR_ENTRIES 16
42
43#ifdef ETHTOOL_GSTATS
44struct ixgbe_stats {
45 char stat_string[ETH_GSTRING_LEN];
46 int sizeof_stat;
47 int stat_offset;
48 int base_stat_offset;
49};
50
51#define IXGBEVF_STAT(m, b) sizeof(((struct ixgbevf_adapter *)0)->m), \
52 offsetof(struct ixgbevf_adapter, m), \
53 offsetof(struct ixgbevf_adapter, b)
54static struct ixgbe_stats ixgbe_gstrings_stats[] = {
55 {"rx_packets", IXGBEVF_STAT(stats.vfgprc, stats.base_vfgprc)},
56 {"tx_packets", IXGBEVF_STAT(stats.vfgptc, stats.base_vfgptc)},
57 {"rx_bytes", IXGBEVF_STAT(stats.vfgorc, stats.base_vfgorc)},
58 {"tx_bytes", IXGBEVF_STAT(stats.vfgotc, stats.base_vfgotc)},
59 {"tx_busy", IXGBEVF_STAT(tx_busy, zero_base)},
60 {"multicast", IXGBEVF_STAT(stats.vfmprc, stats.base_vfmprc)},
61 {"rx_csum_offload_good", IXGBEVF_STAT(hw_csum_rx_good, zero_base)},
62 {"rx_csum_offload_errors", IXGBEVF_STAT(hw_csum_rx_error, zero_base)},
63 {"tx_csum_offload_ctxt", IXGBEVF_STAT(hw_csum_tx_good, zero_base)},
64 {"rx_header_split", IXGBEVF_STAT(rx_hdr_split, zero_base)},
65};
66
67#define IXGBE_QUEUE_STATS_LEN 0
68#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
69
70#define IXGBEVF_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + IXGBE_QUEUE_STATS_LEN)
71#endif /* ETHTOOL_GSTATS */
72#ifdef ETHTOOL_TEST
73static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
74 "Register test (offline)",
75 "Link test (on/offline)"
76};
77#define IXGBE_TEST_LEN (sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN)
78#endif /* ETHTOOL_TEST */
79
80static int ixgbevf_get_settings(struct net_device *netdev,
81 struct ethtool_cmd *ecmd)
82{
83 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
84 struct ixgbe_hw *hw = &adapter->hw;
85 u32 link_speed = 0;
86 bool link_up;
87
88 ecmd->supported = SUPPORTED_10000baseT_Full;
89 ecmd->autoneg = AUTONEG_DISABLE;
90 ecmd->transceiver = XCVR_DUMMY1;
91 ecmd->port = -1;
92
93 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
94
95 if (link_up) {
96 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
97 SPEED_10000 : SPEED_1000;
98 ecmd->duplex = DUPLEX_FULL;
99 } else {
100 ecmd->speed = -1;
101 ecmd->duplex = -1;
102 }
103
104 return 0;
105}
106
107static u32 ixgbevf_get_rx_csum(struct net_device *netdev)
108{
109 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
110 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED;
111}
112
113static int ixgbevf_set_rx_csum(struct net_device *netdev, u32 data)
114{
115 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
116 if (data)
117 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
118 else
119 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
120
121 if (netif_running(netdev)) {
122 if (!adapter->dev_closed)
123 ixgbevf_reinit_locked(adapter);
124 } else {
125 ixgbevf_reset(adapter);
126 }
127
128 return 0;
129}
130
131static int ixgbevf_set_tso(struct net_device *netdev, u32 data)
132{
133 if (data) {
134 netdev->features |= NETIF_F_TSO;
135 netdev->features |= NETIF_F_TSO6;
136 } else {
137 netif_tx_stop_all_queues(netdev);
138 netdev->features &= ~NETIF_F_TSO;
139 netdev->features &= ~NETIF_F_TSO6;
140 netif_tx_start_all_queues(netdev);
141 }
142 return 0;
143}
144
145static u32 ixgbevf_get_msglevel(struct net_device *netdev)
146{
147 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
148 return adapter->msg_enable;
149}
150
151static void ixgbevf_set_msglevel(struct net_device *netdev, u32 data)
152{
153 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
154 adapter->msg_enable = data;
155}
156
157#define IXGBE_GET_STAT(_A_, _R_) (_A_->stats._R_)
158
159static char *ixgbevf_reg_names[] = {
160 "IXGBE_VFCTRL",
161 "IXGBE_VFSTATUS",
162 "IXGBE_VFLINKS",
163 "IXGBE_VFRXMEMWRAP",
164 "IXGBE_VFRTIMER",
165 "IXGBE_VTEICR",
166 "IXGBE_VTEICS",
167 "IXGBE_VTEIMS",
168 "IXGBE_VTEIMC",
169 "IXGBE_VTEIAC",
170 "IXGBE_VTEIAM",
171 "IXGBE_VTEITR",
172 "IXGBE_VTIVAR",
173 "IXGBE_VTIVAR_MISC",
174 "IXGBE_VFRDBAL0",
175 "IXGBE_VFRDBAL1",
176 "IXGBE_VFRDBAH0",
177 "IXGBE_VFRDBAH1",
178 "IXGBE_VFRDLEN0",
179 "IXGBE_VFRDLEN1",
180 "IXGBE_VFRDH0",
181 "IXGBE_VFRDH1",
182 "IXGBE_VFRDT0",
183 "IXGBE_VFRDT1",
184 "IXGBE_VFRXDCTL0",
185 "IXGBE_VFRXDCTL1",
186 "IXGBE_VFSRRCTL0",
187 "IXGBE_VFSRRCTL1",
188 "IXGBE_VFPSRTYPE",
189 "IXGBE_VFTDBAL0",
190 "IXGBE_VFTDBAL1",
191 "IXGBE_VFTDBAH0",
192 "IXGBE_VFTDBAH1",
193 "IXGBE_VFTDLEN0",
194 "IXGBE_VFTDLEN1",
195 "IXGBE_VFTDH0",
196 "IXGBE_VFTDH1",
197 "IXGBE_VFTDT0",
198 "IXGBE_VFTDT1",
199 "IXGBE_VFTXDCTL0",
200 "IXGBE_VFTXDCTL1",
201 "IXGBE_VFTDWBAL0",
202 "IXGBE_VFTDWBAL1",
203 "IXGBE_VFTDWBAH0",
204 "IXGBE_VFTDWBAH1"
205};
206
207
208static int ixgbevf_get_regs_len(struct net_device *netdev)
209{
210 return (ARRAY_SIZE(ixgbevf_reg_names)) * sizeof(u32);
211}
212
213static void ixgbevf_get_regs(struct net_device *netdev,
214 struct ethtool_regs *regs,
215 void *p)
216{
217 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
218 struct ixgbe_hw *hw = &adapter->hw;
219 u32 *regs_buff = p;
220 u32 regs_len = ixgbevf_get_regs_len(netdev);
221 u8 i;
222
223 memset(p, 0, regs_len);
224
225 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
226
227 /* General Registers */
228 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_VFCTRL);
229 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_VFSTATUS);
230 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
231 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_VFRXMEMWRAP);
232 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_VFRTIMER);
233
234 /* Interrupt */
235 /* don't read EICR because it can clear interrupt causes, instead
236 * read EICS which is a shadow but doesn't clear EICR */
237 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_VTEICS);
238 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_VTEICS);
239 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
240 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_VTEIMC);
241 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_VTEIAC);
242 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_VTEIAM);
243 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_VTEITR(0));
244 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_VTIVAR(0));
245 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
246
247 /* Receive DMA */
248 for (i = 0; i < 2; i++)
249 regs_buff[14 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAL(i));
250 for (i = 0; i < 2; i++)
251 regs_buff[16 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDBAH(i));
252 for (i = 0; i < 2; i++)
253 regs_buff[18 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDLEN(i));
254 for (i = 0; i < 2; i++)
255 regs_buff[20 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDH(i));
256 for (i = 0; i < 2; i++)
257 regs_buff[22 + i] = IXGBE_READ_REG(hw, IXGBE_VFRDT(i));
258 for (i = 0; i < 2; i++)
259 regs_buff[24 + i] = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
260 for (i = 0; i < 2; i++)
261 regs_buff[26 + i] = IXGBE_READ_REG(hw, IXGBE_VFSRRCTL(i));
262
263 /* Receive */
264 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_VFPSRTYPE);
265
266 /* Transmit */
267 for (i = 0; i < 2; i++)
268 regs_buff[29 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDBAL(i));
269 for (i = 0; i < 2; i++)
270 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDBAH(i));
271 for (i = 0; i < 2; i++)
272 regs_buff[33 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDLEN(i));
273 for (i = 0; i < 2; i++)
274 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDH(i));
275 for (i = 0; i < 2; i++)
276 regs_buff[37 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDT(i));
277 for (i = 0; i < 2; i++)
278 regs_buff[39 + i] = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
279 for (i = 0; i < 2; i++)
280 regs_buff[41 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDWBAL(i));
281 for (i = 0; i < 2; i++)
282 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_VFTDWBAH(i));
283
284 for (i = 0; i < ARRAY_SIZE(ixgbevf_reg_names); i++)
285 hw_dbg(hw, "%s\t%8.8x\n", ixgbevf_reg_names[i], regs_buff[i]);
286}
287
288static void ixgbevf_get_drvinfo(struct net_device *netdev,
289 struct ethtool_drvinfo *drvinfo)
290{
291 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
292
293 strlcpy(drvinfo->driver, ixgbevf_driver_name, 32);
294 strlcpy(drvinfo->version, ixgbevf_driver_version, 32);
295
296 strlcpy(drvinfo->fw_version, "N/A", 4);
297 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
298}
299
300static void ixgbevf_get_ringparam(struct net_device *netdev,
301 struct ethtool_ringparam *ring)
302{
303 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
304 struct ixgbevf_ring *tx_ring = adapter->tx_ring;
305 struct ixgbevf_ring *rx_ring = adapter->rx_ring;
306
307 ring->rx_max_pending = IXGBEVF_MAX_RXD;
308 ring->tx_max_pending = IXGBEVF_MAX_TXD;
309 ring->rx_mini_max_pending = 0;
310 ring->rx_jumbo_max_pending = 0;
311 ring->rx_pending = rx_ring->count;
312 ring->tx_pending = tx_ring->count;
313 ring->rx_mini_pending = 0;
314 ring->rx_jumbo_pending = 0;
315}
316
317static int ixgbevf_set_ringparam(struct net_device *netdev,
318 struct ethtool_ringparam *ring)
319{
320 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
321 struct ixgbevf_ring *tx_ring = NULL, *rx_ring = NULL;
322 int i, err;
323 u32 new_rx_count, new_tx_count;
324 bool need_tx_update = false;
325 bool need_rx_update = false;
326
327 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
328 return -EINVAL;
329
330 new_rx_count = max(ring->rx_pending, (u32)IXGBEVF_MIN_RXD);
331 new_rx_count = min(new_rx_count, (u32)IXGBEVF_MAX_RXD);
332 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
333
334 new_tx_count = max(ring->tx_pending, (u32)IXGBEVF_MIN_TXD);
335 new_tx_count = min(new_tx_count, (u32)IXGBEVF_MAX_TXD);
336 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
337
338 if ((new_tx_count == adapter->tx_ring->count) &&
339 (new_rx_count == adapter->rx_ring->count)) {
340 /* nothing to do */
341 return 0;
342 }
343
344 while (test_and_set_bit(__IXGBEVF_RESETTING, &adapter->state))
345 msleep(1);
346
347 if (new_tx_count != adapter->tx_ring_count) {
348 tx_ring = kcalloc(adapter->num_tx_queues,
349 sizeof(struct ixgbevf_ring), GFP_KERNEL);
350 if (!tx_ring) {
351 err = -ENOMEM;
352 goto err_setup;
353 }
354 memcpy(tx_ring, adapter->tx_ring,
355 adapter->num_tx_queues * sizeof(struct ixgbevf_ring));
356 for (i = 0; i < adapter->num_tx_queues; i++) {
357 tx_ring[i].count = new_tx_count;
358 err = ixgbevf_setup_tx_resources(adapter,
359 &tx_ring[i]);
360 if (err) {
361 while (i) {
362 i--;
363 ixgbevf_free_tx_resources(adapter,
364 &tx_ring[i]);
365 }
366 kfree(tx_ring);
367 goto err_setup;
368 }
369 tx_ring[i].v_idx = adapter->tx_ring[i].v_idx;
370 }
371 need_tx_update = true;
372 }
373
374 if (new_rx_count != adapter->rx_ring_count) {
375 rx_ring = kcalloc(adapter->num_rx_queues,
376 sizeof(struct ixgbevf_ring), GFP_KERNEL);
377 if ((!rx_ring) && (need_tx_update)) {
378 err = -ENOMEM;
379 goto err_rx_setup;
380 }
381 memcpy(rx_ring, adapter->rx_ring,
382 adapter->num_rx_queues * sizeof(struct ixgbevf_ring));
383 for (i = 0; i < adapter->num_rx_queues; i++) {
384 rx_ring[i].count = new_rx_count;
385 err = ixgbevf_setup_rx_resources(adapter,
386 &rx_ring[i]);
387 if (err) {
388 while (i) {
389 i--;
390 ixgbevf_free_rx_resources(adapter,
391 &rx_ring[i]);
392 }
393 kfree(rx_ring);
394 goto err_rx_setup;
395 }
396 rx_ring[i].v_idx = adapter->rx_ring[i].v_idx;
397 }
398 need_rx_update = true;
399 }
400
401err_rx_setup:
402 /* if rings need to be updated, here's the place to do it in one shot */
403 if (need_tx_update || need_rx_update) {
404 if (netif_running(netdev))
405 ixgbevf_down(adapter);
406 }
407
408 /* tx */
409 if (need_tx_update) {
410 kfree(adapter->tx_ring);
411 adapter->tx_ring = tx_ring;
412 tx_ring = NULL;
413 adapter->tx_ring_count = new_tx_count;
414 }
415
416 /* rx */
417 if (need_rx_update) {
418 kfree(adapter->rx_ring);
419 adapter->rx_ring = rx_ring;
420 rx_ring = NULL;
421 adapter->rx_ring_count = new_rx_count;
422 }
423
424 /* success! */
425 err = 0;
426 if (netif_running(netdev))
427 ixgbevf_up(adapter);
428
429err_setup:
430 clear_bit(__IXGBEVF_RESETTING, &adapter->state);
431 return err;
432}
433
434static int ixgbevf_get_sset_count(struct net_device *dev, int stringset)
435{
436 switch (stringset) {
437 case ETH_SS_TEST:
438 return IXGBE_TEST_LEN;
439 case ETH_SS_STATS:
440 return IXGBE_GLOBAL_STATS_LEN;
441 default:
442 return -EINVAL;
443 }
444}
445
446static void ixgbevf_get_ethtool_stats(struct net_device *netdev,
447 struct ethtool_stats *stats, u64 *data)
448{
449 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
450 int i;
451
452 ixgbevf_update_stats(adapter);
453 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
454 char *p = (char *)adapter +
455 ixgbe_gstrings_stats[i].stat_offset;
456 char *b = (char *)adapter +
457 ixgbe_gstrings_stats[i].base_stat_offset;
458 data[i] = ((ixgbe_gstrings_stats[i].sizeof_stat ==
459 sizeof(u64)) ? *(u64 *)p : *(u32 *)p) -
460 ((ixgbe_gstrings_stats[i].sizeof_stat ==
461 sizeof(u64)) ? *(u64 *)b : *(u32 *)b);
462 }
463}
464
465static void ixgbevf_get_strings(struct net_device *netdev, u32 stringset,
466 u8 *data)
467{
468 char *p = (char *)data;
469 int i;
470
471 switch (stringset) {
472 case ETH_SS_TEST:
473 memcpy(data, *ixgbe_gstrings_test,
474 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
475 break;
476 case ETH_SS_STATS:
477 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
478 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
479 ETH_GSTRING_LEN);
480 p += ETH_GSTRING_LEN;
481 }
482 break;
483 }
484}
485
486static int ixgbevf_link_test(struct ixgbevf_adapter *adapter, u64 *data)
487{
488 struct ixgbe_hw *hw = &adapter->hw;
489 bool link_up;
490 u32 link_speed = 0;
491 *data = 0;
492
493 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
494 if (!link_up)
495 *data = 1;
496
497 return *data;
498}
499
500/* ethtool register test data */
501struct ixgbevf_reg_test {
502 u16 reg;
503 u8 array_len;
504 u8 test_type;
505 u32 mask;
506 u32 write;
507};
508
509/* In the hardware, registers are laid out either singly, in arrays
510 * spaced 0x40 bytes apart, or in contiguous tables. We assume
511 * most tests take place on arrays or single registers (handled
512 * as a single-element array) and special-case the tables.
513 * Table tests are always pattern tests.
514 *
515 * We also make provision for some required setup steps by specifying
516 * registers to be written without any read-back testing.
517 */
518
519#define PATTERN_TEST 1
520#define SET_READ_TEST 2
521#define WRITE_NO_TEST 3
522#define TABLE32_TEST 4
523#define TABLE64_TEST_LO 5
524#define TABLE64_TEST_HI 6
525
526/* default VF register test */
527static struct ixgbevf_reg_test reg_test_vf[] = {
528 { IXGBE_VFRDBAL(0), 2, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
529 { IXGBE_VFRDBAH(0), 2, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
530 { IXGBE_VFRDLEN(0), 2, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
531 { IXGBE_VFRXDCTL(0), 2, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
532 { IXGBE_VFRDT(0), 2, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
533 { IXGBE_VFRXDCTL(0), 2, WRITE_NO_TEST, 0, 0 },
534 { IXGBE_VFTDBAL(0), 2, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
535 { IXGBE_VFTDBAH(0), 2, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
536 { IXGBE_VFTDLEN(0), 2, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
537 { 0, 0, 0, 0 }
538};
539
540#define REG_PATTERN_TEST(R, M, W) \
541{ \
542 u32 pat, val, before; \
543 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
544 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
545 before = readl(adapter->hw.hw_addr + R); \
546 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
547 val = readl(adapter->hw.hw_addr + R); \
548 if (val != (_test[pat] & W & M)) { \
549 hw_dbg(&adapter->hw, \
550 "pattern test reg %04X failed: got " \
551 "0x%08X expected 0x%08X\n", \
552 R, val, (_test[pat] & W & M)); \
553 *data = R; \
554 writel(before, adapter->hw.hw_addr + R); \
555 return 1; \
556 } \
557 writel(before, adapter->hw.hw_addr + R); \
558 } \
559}
560
561#define REG_SET_AND_CHECK(R, M, W) \
562{ \
563 u32 val, before; \
564 before = readl(adapter->hw.hw_addr + R); \
565 writel((W & M), (adapter->hw.hw_addr + R)); \
566 val = readl(adapter->hw.hw_addr + R); \
567 if ((W & M) != (val & M)) { \
568 printk(KERN_ERR "set/check reg %04X test failed: got 0x%08X " \
569 "expected 0x%08X\n", R, (val & M), (W & M)); \
570 *data = R; \
571 writel(before, (adapter->hw.hw_addr + R)); \
572 return 1; \
573 } \
574 writel(before, (adapter->hw.hw_addr + R)); \
575}
576
577static int ixgbevf_reg_test(struct ixgbevf_adapter *adapter, u64 *data)
578{
579 struct ixgbevf_reg_test *test;
580 u32 i;
581
582 test = reg_test_vf;
583
584 /*
585 * Perform the register test, looping through the test table
586 * until we either fail or reach the null entry.
587 */
588 while (test->reg) {
589 for (i = 0; i < test->array_len; i++) {
590 switch (test->test_type) {
591 case PATTERN_TEST:
592 REG_PATTERN_TEST(test->reg + (i * 0x40),
593 test->mask,
594 test->write);
595 break;
596 case SET_READ_TEST:
597 REG_SET_AND_CHECK(test->reg + (i * 0x40),
598 test->mask,
599 test->write);
600 break;
601 case WRITE_NO_TEST:
602 writel(test->write,
603 (adapter->hw.hw_addr + test->reg)
604 + (i * 0x40));
605 break;
606 case TABLE32_TEST:
607 REG_PATTERN_TEST(test->reg + (i * 4),
608 test->mask,
609 test->write);
610 break;
611 case TABLE64_TEST_LO:
612 REG_PATTERN_TEST(test->reg + (i * 8),
613 test->mask,
614 test->write);
615 break;
616 case TABLE64_TEST_HI:
617 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
618 test->mask,
619 test->write);
620 break;
621 }
622 }
623 test++;
624 }
625
626 *data = 0;
627 return *data;
628}
629
630static void ixgbevf_diag_test(struct net_device *netdev,
631 struct ethtool_test *eth_test, u64 *data)
632{
633 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
634 bool if_running = netif_running(netdev);
635
636 set_bit(__IXGBEVF_TESTING, &adapter->state);
637 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
638 /* Offline tests */
639
640 hw_dbg(&adapter->hw, "offline testing starting\n");
641
642 /* Link test performed before hardware reset so autoneg doesn't
643 * interfere with test result */
644 if (ixgbevf_link_test(adapter, &data[1]))
645 eth_test->flags |= ETH_TEST_FL_FAILED;
646
647 if (if_running)
648 /* indicate we're in test mode */
649 dev_close(netdev);
650 else
651 ixgbevf_reset(adapter);
652
653 hw_dbg(&adapter->hw, "register testing starting\n");
654 if (ixgbevf_reg_test(adapter, &data[0]))
655 eth_test->flags |= ETH_TEST_FL_FAILED;
656
657 ixgbevf_reset(adapter);
658
659 clear_bit(__IXGBEVF_TESTING, &adapter->state);
660 if (if_running)
661 dev_open(netdev);
662 } else {
663 hw_dbg(&adapter->hw, "online testing starting\n");
664 /* Online tests */
665 if (ixgbevf_link_test(adapter, &data[1]))
666 eth_test->flags |= ETH_TEST_FL_FAILED;
667
668 /* Online tests aren't run; pass by default */
669 data[0] = 0;
670
671 clear_bit(__IXGBEVF_TESTING, &adapter->state);
672 }
673 msleep_interruptible(4 * 1000);
674}
675
676static int ixgbevf_nway_reset(struct net_device *netdev)
677{
678 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
679
680 if (netif_running(netdev)) {
681 if (!adapter->dev_closed)
682 ixgbevf_reinit_locked(adapter);
683 }
684
685 return 0;
686}
687
688static struct ethtool_ops ixgbevf_ethtool_ops = {
689 .get_settings = ixgbevf_get_settings,
690 .get_drvinfo = ixgbevf_get_drvinfo,
691 .get_regs_len = ixgbevf_get_regs_len,
692 .get_regs = ixgbevf_get_regs,
693 .nway_reset = ixgbevf_nway_reset,
694 .get_link = ethtool_op_get_link,
695 .get_ringparam = ixgbevf_get_ringparam,
696 .set_ringparam = ixgbevf_set_ringparam,
697 .get_rx_csum = ixgbevf_get_rx_csum,
698 .set_rx_csum = ixgbevf_set_rx_csum,
699 .get_tx_csum = ethtool_op_get_tx_csum,
700 .set_tx_csum = ethtool_op_set_tx_ipv6_csum,
701 .get_sg = ethtool_op_get_sg,
702 .set_sg = ethtool_op_set_sg,
703 .get_msglevel = ixgbevf_get_msglevel,
704 .set_msglevel = ixgbevf_set_msglevel,
705 .get_tso = ethtool_op_get_tso,
706 .set_tso = ixgbevf_set_tso,
707 .self_test = ixgbevf_diag_test,
708 .get_sset_count = ixgbevf_get_sset_count,
709 .get_strings = ixgbevf_get_strings,
710 .get_ethtool_stats = ixgbevf_get_ethtool_stats,
711};
712
713void ixgbevf_set_ethtool_ops(struct net_device *netdev)
714{
715 SET_ETHTOOL_OPS(netdev, &ixgbevf_ethtool_ops);
716}
diff --git a/drivers/net/ixgbevf/ixgbevf.h b/drivers/net/ixgbevf/ixgbevf.h
new file mode 100644
index 000000000000..f7015efbff05
--- /dev/null
+++ b/drivers/net/ixgbevf/ixgbevf.h
@@ -0,0 +1,318 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBEVF_H_
29#define _IXGBEVF_H_
30
31#include <linux/types.h>
32#include <linux/timer.h>
33#include <linux/io.h>
34#include <linux/netdevice.h>
35
36#include "vf.h"
37
38/* wrapper around a pointer to a socket buffer,
39 * so a DMA handle can be stored along with the buffer */
40struct ixgbevf_tx_buffer {
41 struct sk_buff *skb;
42 dma_addr_t dma;
43 unsigned long time_stamp;
44 u16 length;
45 u16 next_to_watch;
46 u16 mapped_as_page;
47};
48
49struct ixgbevf_rx_buffer {
50 struct sk_buff *skb;
51 dma_addr_t dma;
52 struct page *page;
53 dma_addr_t page_dma;
54 unsigned int page_offset;
55};
56
57struct ixgbevf_ring {
58 struct ixgbevf_adapter *adapter; /* backlink */
59 void *desc; /* descriptor ring memory */
60 dma_addr_t dma; /* phys. address of descriptor ring */
61 unsigned int size; /* length in bytes */
62 unsigned int count; /* amount of descriptors */
63 unsigned int next_to_use;
64 unsigned int next_to_clean;
65
66 int queue_index; /* needed for multiqueue queue management */
67 union {
68 struct ixgbevf_tx_buffer *tx_buffer_info;
69 struct ixgbevf_rx_buffer *rx_buffer_info;
70 };
71
72 u16 head;
73 u16 tail;
74
75 unsigned int total_bytes;
76 unsigned int total_packets;
77
78 u16 reg_idx; /* holds the special value that gets the hardware register
79 * offset associated with this ring, which is different
80 * for DCB and RSS modes */
81
82#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
83 /* cpu for tx queue */
84 int cpu;
85#endif
86
87 u64 v_idx; /* maps directly to the index for this ring in the hardware
88 * vector array, can also be used for finding the bit in EICR
89 * and friends that represents the vector for this ring */
90
91 u16 work_limit; /* max work per interrupt */
92 u16 rx_buf_len;
93};
94
95enum ixgbevf_ring_f_enum {
96 RING_F_NONE = 0,
97 RING_F_ARRAY_SIZE /* must be last in enum set */
98};
99
100struct ixgbevf_ring_feature {
101 int indices;
102 int mask;
103};
104
105/* How many Rx Buffers do we bundle into one write to the hardware ? */
106#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
107
108#define MAX_RX_QUEUES 1
109#define MAX_TX_QUEUES 1
110
111#define IXGBEVF_DEFAULT_TXD 1024
112#define IXGBEVF_DEFAULT_RXD 512
113#define IXGBEVF_MAX_TXD 4096
114#define IXGBEVF_MIN_TXD 64
115#define IXGBEVF_MAX_RXD 4096
116#define IXGBEVF_MIN_RXD 64
117
118/* Supported Rx Buffer Sizes */
119#define IXGBEVF_RXBUFFER_64 64 /* Used for packet split */
120#define IXGBEVF_RXBUFFER_128 128 /* Used for packet split */
121#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
122#define IXGBEVF_RXBUFFER_2048 2048
123#define IXGBEVF_MAX_RXBUFFER 16384 /* largest size for single descriptor */
124
125#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
126
127#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
128
129#define IXGBE_TX_FLAGS_CSUM (u32)(1)
130#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
131#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
132#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
133#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
134#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
135#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
136#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
137#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
138
139/* MAX_MSIX_Q_VECTORS of these are allocated,
140 * but we only use one per queue-specific vector.
141 */
142struct ixgbevf_q_vector {
143 struct ixgbevf_adapter *adapter;
144 struct napi_struct napi;
145 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
146 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
147 u8 rxr_count; /* Rx ring count assigned to this vector */
148 u8 txr_count; /* Tx ring count assigned to this vector */
149 u8 tx_itr;
150 u8 rx_itr;
151 u32 eitr;
152 int v_idx; /* vector index in list */
153};
154
155/* Helper macros to switch between ints/sec and what the register uses.
156 * And yes, it's the same math going both ways. The lowest value
157 * supported by all of the ixgbe hardware is 8.
158 */
159#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
160 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
161#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
162
163#define IXGBE_DESC_UNUSED(R) \
164 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
165 (R)->next_to_clean - (R)->next_to_use - 1)
166
167#define IXGBE_RX_DESC_ADV(R, i) \
168 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
169#define IXGBE_TX_DESC_ADV(R, i) \
170 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
171#define IXGBE_TX_CTXTDESC_ADV(R, i) \
172 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
173
174#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
175
176#define OTHER_VECTOR 1
177#define NON_Q_VECTORS (OTHER_VECTOR)
178
179#define MAX_MSIX_Q_VECTORS 2
180#define MAX_MSIX_COUNT 2
181
182#define MIN_MSIX_Q_VECTORS 2
183#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
184
185/* board specific private data structure */
186struct ixgbevf_adapter {
187 struct timer_list watchdog_timer;
188#ifdef NETIF_F_HW_VLAN_TX
189 struct vlan_group *vlgrp;
190#endif
191 u16 bd_number;
192 struct work_struct reset_task;
193 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
194 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
195
196 /* Interrupt Throttle Rate */
197 u32 itr_setting;
198 u16 eitr_low;
199 u16 eitr_high;
200
201 /* TX */
202 struct ixgbevf_ring *tx_ring; /* One per active queue */
203 int num_tx_queues;
204 u64 restart_queue;
205 u64 hw_csum_tx_good;
206 u64 lsc_int;
207 u64 hw_tso_ctxt;
208 u64 hw_tso6_ctxt;
209 u32 tx_timeout_count;
210 bool detect_tx_hung;
211
212 /* RX */
213 struct ixgbevf_ring *rx_ring; /* One per active queue */
214 int num_rx_queues;
215 int num_rx_pools; /* == num_rx_queues in 82598 */
216 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
217 u64 hw_csum_rx_error;
218 u64 hw_rx_no_dma_resources;
219 u64 hw_csum_rx_good;
220 u64 non_eop_descs;
221 int num_msix_vectors;
222 int max_msix_q_vectors; /* true count of q_vectors for device */
223 struct ixgbevf_ring_feature ring_feature[RING_F_ARRAY_SIZE];
224 struct msix_entry *msix_entries;
225
226 u64 rx_hdr_split;
227 u32 alloc_rx_page_failed;
228 u32 alloc_rx_buff_failed;
229
230 /* Some features need tri-state capability,
231 * thus the additional *_CAPABLE flags.
232 */
233 u32 flags;
234#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
235#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 1)
236#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 2)
237#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 3)
238#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 4)
239#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 5)
240#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 6)
241#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 7)
242#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 8)
243 /* OS defined structs */
244 struct net_device *netdev;
245 struct pci_dev *pdev;
246 struct net_device_stats net_stats;
247
248 /* structs defined in ixgbe_vf.h */
249 struct ixgbe_hw hw;
250 u16 msg_enable;
251 struct ixgbevf_hw_stats stats;
252 u64 zero_base;
253 /* Interrupt Throttle Rate */
254 u32 eitr_param;
255
256 unsigned long state;
257 u32 *config_space;
258 u64 tx_busy;
259 unsigned int tx_ring_count;
260 unsigned int rx_ring_count;
261
262 u32 link_speed;
263 bool link_up;
264 unsigned long link_check_timeout;
265
266 struct work_struct watchdog_task;
267 bool netdev_registered;
268 bool dev_closed;
269};
270
271enum ixbgevf_state_t {
272 __IXGBEVF_TESTING,
273 __IXGBEVF_RESETTING,
274 __IXGBEVF_DOWN
275};
276
277enum ixgbevf_boards {
278 board_82599_vf,
279};
280
281extern struct ixgbevf_info ixgbevf_vf_info;
282extern struct ixgbe_mac_operations ixgbevf_mbx_ops;
283
284/* needed by ethtool.c */
285extern char ixgbevf_driver_name[];
286extern const char ixgbevf_driver_version[];
287
288extern int ixgbevf_up(struct ixgbevf_adapter *adapter);
289extern void ixgbevf_down(struct ixgbevf_adapter *adapter);
290extern void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
291extern void ixgbevf_reset(struct ixgbevf_adapter *adapter);
292extern void ixgbevf_set_ethtool_ops(struct net_device *netdev);
293extern int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *,
294 struct ixgbevf_ring *);
295extern int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *,
296 struct ixgbevf_ring *);
297extern void ixgbevf_free_rx_resources(struct ixgbevf_adapter *,
298 struct ixgbevf_ring *);
299extern void ixgbevf_free_tx_resources(struct ixgbevf_adapter *,
300 struct ixgbevf_ring *);
301extern void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
302
303#ifdef ETHTOOL_OPS_COMPAT
304extern int ethtool_ioctl(struct ifreq *ifr);
305
306#endif
307extern void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
308extern void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
309
310#ifdef DEBUG
311extern char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw);
312#define hw_dbg(hw, format, arg...) \
313 printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg)
314#else
315#define hw_dbg(hw, format, arg...) do {} while (0)
316#endif
317
318#endif /* _IXGBEVF_H_ */
diff --git a/drivers/net/ixgbevf/ixgbevf_main.c b/drivers/net/ixgbevf/ixgbevf_main.c
new file mode 100644
index 000000000000..235b5fd4b8d4
--- /dev/null
+++ b/drivers/net/ixgbevf/ixgbevf_main.c
@@ -0,0 +1,3578 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/******************************************************************************
30 Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code
31******************************************************************************/
32#include <linux/types.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/vmalloc.h>
37#include <linux/string.h>
38#include <linux/in.h>
39#include <linux/ip.h>
40#include <linux/tcp.h>
41#include <linux/ipv6.h>
42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
45#include <linux/if_vlan.h>
46
47#include "ixgbevf.h"
48
49char ixgbevf_driver_name[] = "ixgbevf";
50static const char ixgbevf_driver_string[] =
51 "Intel(R) 82599 Virtual Function";
52
53#define DRV_VERSION "1.0.0-k0"
54const char ixgbevf_driver_version[] = DRV_VERSION;
55static char ixgbevf_copyright[] = "Copyright (c) 2009 Intel Corporation.";
56
57static const struct ixgbevf_info *ixgbevf_info_tbl[] = {
58 [board_82599_vf] = &ixgbevf_vf_info,
59};
60
61/* ixgbevf_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69static struct pci_device_id ixgbevf_pci_tbl[] = {
70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_VF),
71 board_82599_vf},
72
73 /* required last entry */
74 {0, }
75};
76MODULE_DEVICE_TABLE(pci, ixgbevf_pci_tbl);
77
78MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
79MODULE_DESCRIPTION("Intel(R) 82599 Virtual Function Driver");
80MODULE_LICENSE("GPL");
81MODULE_VERSION(DRV_VERSION);
82
83#define DEFAULT_DEBUG_LEVEL_SHIFT 3
84
85/* forward decls */
86static void ixgbevf_set_itr_msix(struct ixgbevf_q_vector *q_vector);
87static void ixgbevf_write_eitr(struct ixgbevf_adapter *adapter, int v_idx,
88 u32 itr_reg);
89
90static inline void ixgbevf_release_rx_desc(struct ixgbe_hw *hw,
91 struct ixgbevf_ring *rx_ring,
92 u32 val)
93{
94 /*
95 * Force memory writes to complete before letting h/w
96 * know there are new descriptors to fetch. (Only
97 * applicable for weak-ordered memory model archs,
98 * such as IA-64).
99 */
100 wmb();
101 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rx_ring->reg_idx), val);
102}
103
104/*
105 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
106 * @adapter: pointer to adapter struct
107 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
108 * @queue: queue to map the corresponding interrupt to
109 * @msix_vector: the vector to map to the corresponding queue
110 *
111 */
112static void ixgbevf_set_ivar(struct ixgbevf_adapter *adapter, s8 direction,
113 u8 queue, u8 msix_vector)
114{
115 u32 ivar, index;
116 struct ixgbe_hw *hw = &adapter->hw;
117 if (direction == -1) {
118 /* other causes */
119 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
120 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
121 ivar &= ~0xFF;
122 ivar |= msix_vector;
123 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, ivar);
124 } else {
125 /* tx or rx causes */
126 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
127 index = ((16 * (queue & 1)) + (8 * direction));
128 ivar = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
129 ivar &= ~(0xFF << index);
130 ivar |= (msix_vector << index);
131 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), ivar);
132 }
133}
134
135static void ixgbevf_unmap_and_free_tx_resource(struct ixgbevf_adapter *adapter,
136 struct ixgbevf_tx_buffer
137 *tx_buffer_info)
138{
139 if (tx_buffer_info->dma) {
140 if (tx_buffer_info->mapped_as_page)
141 pci_unmap_page(adapter->pdev,
142 tx_buffer_info->dma,
143 tx_buffer_info->length,
144 PCI_DMA_TODEVICE);
145 else
146 pci_unmap_single(adapter->pdev,
147 tx_buffer_info->dma,
148 tx_buffer_info->length,
149 PCI_DMA_TODEVICE);
150 tx_buffer_info->dma = 0;
151 }
152 if (tx_buffer_info->skb) {
153 dev_kfree_skb_any(tx_buffer_info->skb);
154 tx_buffer_info->skb = NULL;
155 }
156 tx_buffer_info->time_stamp = 0;
157 /* tx_buffer_info must be completely set up in the transmit path */
158}
159
160static inline bool ixgbevf_check_tx_hang(struct ixgbevf_adapter *adapter,
161 struct ixgbevf_ring *tx_ring,
162 unsigned int eop)
163{
164 struct ixgbe_hw *hw = &adapter->hw;
165 u32 head, tail;
166
167 /* Detect a transmit hang in hardware, this serializes the
168 * check with the clearing of time_stamp and movement of eop */
169 head = readl(hw->hw_addr + tx_ring->head);
170 tail = readl(hw->hw_addr + tx_ring->tail);
171 adapter->detect_tx_hung = false;
172 if ((head != tail) &&
173 tx_ring->tx_buffer_info[eop].time_stamp &&
174 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ)) {
175 /* detected Tx unit hang */
176 union ixgbe_adv_tx_desc *tx_desc;
177 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
178 printk(KERN_ERR "Detected Tx Unit Hang\n"
179 " Tx Queue <%d>\n"
180 " TDH, TDT <%x>, <%x>\n"
181 " next_to_use <%x>\n"
182 " next_to_clean <%x>\n"
183 "tx_buffer_info[next_to_clean]\n"
184 " time_stamp <%lx>\n"
185 " jiffies <%lx>\n",
186 tx_ring->queue_index,
187 head, tail,
188 tx_ring->next_to_use, eop,
189 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
190 return true;
191 }
192
193 return false;
194}
195
196#define IXGBE_MAX_TXD_PWR 14
197#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
198
199/* Tx Descriptors needed, worst case */
200#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
201 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
202#ifdef MAX_SKB_FRAGS
203#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
204 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
205#else
206#define DESC_NEEDED TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD)
207#endif
208
209static void ixgbevf_tx_timeout(struct net_device *netdev);
210
211/**
212 * ixgbevf_clean_tx_irq - Reclaim resources after transmit completes
213 * @adapter: board private structure
214 * @tx_ring: tx ring to clean
215 **/
216static bool ixgbevf_clean_tx_irq(struct ixgbevf_adapter *adapter,
217 struct ixgbevf_ring *tx_ring)
218{
219 struct net_device *netdev = adapter->netdev;
220 struct ixgbe_hw *hw = &adapter->hw;
221 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
222 struct ixgbevf_tx_buffer *tx_buffer_info;
223 unsigned int i, eop, count = 0;
224 unsigned int total_bytes = 0, total_packets = 0;
225
226 i = tx_ring->next_to_clean;
227 eop = tx_ring->tx_buffer_info[i].next_to_watch;
228 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
229
230 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
231 (count < tx_ring->work_limit)) {
232 bool cleaned = false;
233 for ( ; !cleaned; count++) {
234 struct sk_buff *skb;
235 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
236 tx_buffer_info = &tx_ring->tx_buffer_info[i];
237 cleaned = (i == eop);
238 skb = tx_buffer_info->skb;
239
240 if (cleaned && skb) {
241 unsigned int segs, bytecount;
242
243 /* gso_segs is currently only valid for tcp */
244 segs = skb_shinfo(skb)->gso_segs ?: 1;
245 /* multiply data chunks by size of headers */
246 bytecount = ((segs - 1) * skb_headlen(skb)) +
247 skb->len;
248 total_packets += segs;
249 total_bytes += bytecount;
250 }
251
252 ixgbevf_unmap_and_free_tx_resource(adapter,
253 tx_buffer_info);
254
255 tx_desc->wb.status = 0;
256
257 i++;
258 if (i == tx_ring->count)
259 i = 0;
260 }
261
262 eop = tx_ring->tx_buffer_info[i].next_to_watch;
263 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
264 }
265
266 tx_ring->next_to_clean = i;
267
268#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
269 if (unlikely(count && netif_carrier_ok(netdev) &&
270 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
271 /* Make sure that anybody stopping the queue after this
272 * sees the new next_to_clean.
273 */
274 smp_mb();
275#ifdef HAVE_TX_MQ
276 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
277 !test_bit(__IXGBEVF_DOWN, &adapter->state)) {
278 netif_wake_subqueue(netdev, tx_ring->queue_index);
279 ++adapter->restart_queue;
280 }
281#else
282 if (netif_queue_stopped(netdev) &&
283 !test_bit(__IXGBEVF_DOWN, &adapter->state)) {
284 netif_wake_queue(netdev);
285 ++adapter->restart_queue;
286 }
287#endif
288 }
289
290 if (adapter->detect_tx_hung) {
291 if (ixgbevf_check_tx_hang(adapter, tx_ring, i)) {
292 /* schedule immediate reset if we believe we hung */
293 printk(KERN_INFO
294 "tx hang %d detected, resetting adapter\n",
295 adapter->tx_timeout_count + 1);
296 ixgbevf_tx_timeout(adapter->netdev);
297 }
298 }
299
300 /* re-arm the interrupt */
301 if ((count >= tx_ring->work_limit) &&
302 (!test_bit(__IXGBEVF_DOWN, &adapter->state))) {
303 IXGBE_WRITE_REG(hw, IXGBE_VTEICS, tx_ring->v_idx);
304 }
305
306 tx_ring->total_bytes += total_bytes;
307 tx_ring->total_packets += total_packets;
308
309 adapter->net_stats.tx_bytes += total_bytes;
310 adapter->net_stats.tx_packets += total_packets;
311
312 return (count < tx_ring->work_limit);
313}
314
315/**
316 * ixgbevf_receive_skb - Send a completed packet up the stack
317 * @q_vector: structure containing interrupt and ring information
318 * @skb: packet to send up
319 * @status: hardware indication of status of receive
320 * @rx_ring: rx descriptor ring (for a specific queue) to setup
321 * @rx_desc: rx descriptor
322 **/
323static void ixgbevf_receive_skb(struct ixgbevf_q_vector *q_vector,
324 struct sk_buff *skb, u8 status,
325 struct ixgbevf_ring *ring,
326 union ixgbe_adv_rx_desc *rx_desc)
327{
328 struct ixgbevf_adapter *adapter = q_vector->adapter;
329 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
330 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
331 int ret;
332
333 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
334 if (adapter->vlgrp && is_vlan)
335 vlan_gro_receive(&q_vector->napi,
336 adapter->vlgrp,
337 tag, skb);
338 else
339 napi_gro_receive(&q_vector->napi, skb);
340 } else {
341 if (adapter->vlgrp && is_vlan)
342 ret = vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
343 else
344 ret = netif_rx(skb);
345 }
346}
347
348/**
349 * ixgbevf_rx_checksum - indicate in skb if hw indicated a good cksum
350 * @adapter: address of board private structure
351 * @status_err: hardware indication of status of receive
352 * @skb: skb currently being received and modified
353 **/
354static inline void ixgbevf_rx_checksum(struct ixgbevf_adapter *adapter,
355 u32 status_err, struct sk_buff *skb)
356{
357 skb->ip_summed = CHECKSUM_NONE;
358
359 /* Rx csum disabled */
360 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
361 return;
362
363 /* if IP and error */
364 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
365 (status_err & IXGBE_RXDADV_ERR_IPE)) {
366 adapter->hw_csum_rx_error++;
367 return;
368 }
369
370 if (!(status_err & IXGBE_RXD_STAT_L4CS))
371 return;
372
373 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
374 adapter->hw_csum_rx_error++;
375 return;
376 }
377
378 /* It must be a TCP or UDP packet with a valid checksum */
379 skb->ip_summed = CHECKSUM_UNNECESSARY;
380 adapter->hw_csum_rx_good++;
381}
382
383/**
384 * ixgbevf_alloc_rx_buffers - Replace used receive buffers; packet split
385 * @adapter: address of board private structure
386 **/
387static void ixgbevf_alloc_rx_buffers(struct ixgbevf_adapter *adapter,
388 struct ixgbevf_ring *rx_ring,
389 int cleaned_count)
390{
391 struct pci_dev *pdev = adapter->pdev;
392 union ixgbe_adv_rx_desc *rx_desc;
393 struct ixgbevf_rx_buffer *bi;
394 struct sk_buff *skb;
395 unsigned int i;
396 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
397
398 i = rx_ring->next_to_use;
399 bi = &rx_ring->rx_buffer_info[i];
400
401 while (cleaned_count--) {
402 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
403
404 if (!bi->page_dma &&
405 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
406 if (!bi->page) {
407 bi->page = netdev_alloc_page(adapter->netdev);
408 if (!bi->page) {
409 adapter->alloc_rx_page_failed++;
410 goto no_buffers;
411 }
412 bi->page_offset = 0;
413 } else {
414 /* use a half page if we're re-using */
415 bi->page_offset ^= (PAGE_SIZE / 2);
416 }
417
418 bi->page_dma = pci_map_page(pdev, bi->page,
419 bi->page_offset,
420 (PAGE_SIZE / 2),
421 PCI_DMA_FROMDEVICE);
422 }
423
424 skb = bi->skb;
425 if (!skb) {
426 skb = netdev_alloc_skb(adapter->netdev,
427 bufsz);
428
429 if (!skb) {
430 adapter->alloc_rx_buff_failed++;
431 goto no_buffers;
432 }
433
434 /*
435 * Make buffer alignment 2 beyond a 16 byte boundary
436 * this will result in a 16 byte aligned IP header after
437 * the 14 byte MAC header is removed
438 */
439 skb_reserve(skb, NET_IP_ALIGN);
440
441 bi->skb = skb;
442 }
443 if (!bi->dma) {
444 bi->dma = pci_map_single(pdev, skb->data,
445 rx_ring->rx_buf_len,
446 PCI_DMA_FROMDEVICE);
447 }
448 /* Refresh the desc even if buffer_addrs didn't change because
449 * each write-back erases this info. */
450 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
451 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
452 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
453 } else {
454 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
455 }
456
457 i++;
458 if (i == rx_ring->count)
459 i = 0;
460 bi = &rx_ring->rx_buffer_info[i];
461 }
462
463no_buffers:
464 if (rx_ring->next_to_use != i) {
465 rx_ring->next_to_use = i;
466 if (i-- == 0)
467 i = (rx_ring->count - 1);
468
469 ixgbevf_release_rx_desc(&adapter->hw, rx_ring, i);
470 }
471}
472
473static inline void ixgbevf_irq_enable_queues(struct ixgbevf_adapter *adapter,
474 u64 qmask)
475{
476 u32 mask;
477 struct ixgbe_hw *hw = &adapter->hw;
478
479 mask = (qmask & 0xFFFFFFFF);
480 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
481}
482
483static inline u16 ixgbevf_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
484{
485 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
486}
487
488static inline u16 ixgbevf_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
489{
490 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
491}
492
493static bool ixgbevf_clean_rx_irq(struct ixgbevf_q_vector *q_vector,
494 struct ixgbevf_ring *rx_ring,
495 int *work_done, int work_to_do)
496{
497 struct ixgbevf_adapter *adapter = q_vector->adapter;
498 struct pci_dev *pdev = adapter->pdev;
499 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
500 struct ixgbevf_rx_buffer *rx_buffer_info, *next_buffer;
501 struct sk_buff *skb;
502 unsigned int i;
503 u32 len, staterr;
504 u16 hdr_info;
505 bool cleaned = false;
506 int cleaned_count = 0;
507 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
508
509 i = rx_ring->next_to_clean;
510 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512 rx_buffer_info = &rx_ring->rx_buffer_info[i];
513
514 while (staterr & IXGBE_RXD_STAT_DD) {
515 u32 upper_len = 0;
516 if (*work_done >= work_to_do)
517 break;
518 (*work_done)++;
519
520 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
521 hdr_info = le16_to_cpu(ixgbevf_get_hdr_info(rx_desc));
522 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
523 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
524 if (hdr_info & IXGBE_RXDADV_SPH)
525 adapter->rx_hdr_split++;
526 if (len > IXGBEVF_RX_HDR_SIZE)
527 len = IXGBEVF_RX_HDR_SIZE;
528 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
529 } else {
530 len = le16_to_cpu(rx_desc->wb.upper.length);
531 }
532 cleaned = true;
533 skb = rx_buffer_info->skb;
534 prefetch(skb->data - NET_IP_ALIGN);
535 rx_buffer_info->skb = NULL;
536
537 if (rx_buffer_info->dma) {
538 pci_unmap_single(pdev, rx_buffer_info->dma,
539 rx_ring->rx_buf_len,
540 PCI_DMA_FROMDEVICE);
541 rx_buffer_info->dma = 0;
542 skb_put(skb, len);
543 }
544
545 if (upper_len) {
546 pci_unmap_page(pdev, rx_buffer_info->page_dma,
547 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
548 rx_buffer_info->page_dma = 0;
549 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
550 rx_buffer_info->page,
551 rx_buffer_info->page_offset,
552 upper_len);
553
554 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
555 (page_count(rx_buffer_info->page) != 1))
556 rx_buffer_info->page = NULL;
557 else
558 get_page(rx_buffer_info->page);
559
560 skb->len += upper_len;
561 skb->data_len += upper_len;
562 skb->truesize += upper_len;
563 }
564
565 i++;
566 if (i == rx_ring->count)
567 i = 0;
568
569 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
570 prefetch(next_rxd);
571 cleaned_count++;
572
573 next_buffer = &rx_ring->rx_buffer_info[i];
574
575 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
576 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
577 rx_buffer_info->skb = next_buffer->skb;
578 rx_buffer_info->dma = next_buffer->dma;
579 next_buffer->skb = skb;
580 next_buffer->dma = 0;
581 } else {
582 skb->next = next_buffer->skb;
583 skb->next->prev = skb;
584 }
585 adapter->non_eop_descs++;
586 goto next_desc;
587 }
588
589 /* ERR_MASK will only have valid bits if EOP set */
590 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
591 dev_kfree_skb_irq(skb);
592 goto next_desc;
593 }
594
595 ixgbevf_rx_checksum(adapter, staterr, skb);
596
597 /* probably a little skewed due to removing CRC */
598 total_rx_bytes += skb->len;
599 total_rx_packets++;
600
601 /*
602 * Work around issue of some types of VM to VM loop back
603 * packets not getting split correctly
604 */
605 if (staterr & IXGBE_RXD_STAT_LB) {
606 u32 header_fixup_len = skb->len - skb->data_len;
607 if (header_fixup_len < 14)
608 skb_push(skb, header_fixup_len);
609 }
610 skb->protocol = eth_type_trans(skb, adapter->netdev);
611
612 ixgbevf_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
613 adapter->netdev->last_rx = jiffies;
614
615next_desc:
616 rx_desc->wb.upper.status_error = 0;
617
618 /* return some buffers to hardware, one at a time is too slow */
619 if (cleaned_count >= IXGBEVF_RX_BUFFER_WRITE) {
620 ixgbevf_alloc_rx_buffers(adapter, rx_ring,
621 cleaned_count);
622 cleaned_count = 0;
623 }
624
625 /* use prefetched values */
626 rx_desc = next_rxd;
627 rx_buffer_info = &rx_ring->rx_buffer_info[i];
628
629 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
630 }
631
632 rx_ring->next_to_clean = i;
633 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
634
635 if (cleaned_count)
636 ixgbevf_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
637
638 rx_ring->total_packets += total_rx_packets;
639 rx_ring->total_bytes += total_rx_bytes;
640 adapter->net_stats.rx_bytes += total_rx_bytes;
641 adapter->net_stats.rx_packets += total_rx_packets;
642
643 return cleaned;
644}
645
646/**
647 * ixgbevf_clean_rxonly - msix (aka one shot) rx clean routine
648 * @napi: napi struct with our devices info in it
649 * @budget: amount of work driver is allowed to do this pass, in packets
650 *
651 * This function is optimized for cleaning one queue only on a single
652 * q_vector!!!
653 **/
654static int ixgbevf_clean_rxonly(struct napi_struct *napi, int budget)
655{
656 struct ixgbevf_q_vector *q_vector =
657 container_of(napi, struct ixgbevf_q_vector, napi);
658 struct ixgbevf_adapter *adapter = q_vector->adapter;
659 struct ixgbevf_ring *rx_ring = NULL;
660 int work_done = 0;
661 long r_idx;
662
663 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
664 rx_ring = &(adapter->rx_ring[r_idx]);
665
666 ixgbevf_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
667
668 /* If all Rx work done, exit the polling mode */
669 if (work_done < budget) {
670 napi_complete(napi);
671 if (adapter->itr_setting & 1)
672 ixgbevf_set_itr_msix(q_vector);
673 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
674 ixgbevf_irq_enable_queues(adapter, rx_ring->v_idx);
675 }
676
677 return work_done;
678}
679
680/**
681 * ixgbevf_clean_rxonly_many - msix (aka one shot) rx clean routine
682 * @napi: napi struct with our devices info in it
683 * @budget: amount of work driver is allowed to do this pass, in packets
684 *
685 * This function will clean more than one rx queue associated with a
686 * q_vector.
687 **/
688static int ixgbevf_clean_rxonly_many(struct napi_struct *napi, int budget)
689{
690 struct ixgbevf_q_vector *q_vector =
691 container_of(napi, struct ixgbevf_q_vector, napi);
692 struct ixgbevf_adapter *adapter = q_vector->adapter;
693 struct ixgbevf_ring *rx_ring = NULL;
694 int work_done = 0, i;
695 long r_idx;
696 u64 enable_mask = 0;
697
698 /* attempt to distribute budget to each queue fairly, but don't allow
699 * the budget to go below 1 because we'll exit polling */
700 budget /= (q_vector->rxr_count ?: 1);
701 budget = max(budget, 1);
702 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
703 for (i = 0; i < q_vector->rxr_count; i++) {
704 rx_ring = &(adapter->rx_ring[r_idx]);
705 ixgbevf_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
706 enable_mask |= rx_ring->v_idx;
707 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
708 r_idx + 1);
709 }
710
711#ifndef HAVE_NETDEV_NAPI_LIST
712 if (!netif_running(adapter->netdev))
713 work_done = 0;
714
715#endif
716 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
717 rx_ring = &(adapter->rx_ring[r_idx]);
718
719 /* If all Rx work done, exit the polling mode */
720 if (work_done < budget) {
721 napi_complete(napi);
722 if (adapter->itr_setting & 1)
723 ixgbevf_set_itr_msix(q_vector);
724 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
725 ixgbevf_irq_enable_queues(adapter, enable_mask);
726 }
727
728 return work_done;
729}
730
731
732/**
733 * ixgbevf_configure_msix - Configure MSI-X hardware
734 * @adapter: board private structure
735 *
736 * ixgbevf_configure_msix sets up the hardware to properly generate MSI-X
737 * interrupts.
738 **/
739static void ixgbevf_configure_msix(struct ixgbevf_adapter *adapter)
740{
741 struct ixgbevf_q_vector *q_vector;
742 struct ixgbe_hw *hw = &adapter->hw;
743 int i, j, q_vectors, v_idx, r_idx;
744 u32 mask;
745
746 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
747
748 /*
749 * Populate the IVAR table and set the ITR values to the
750 * corresponding register.
751 */
752 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
753 q_vector = adapter->q_vector[v_idx];
754 /* XXX for_each_bit(...) */
755 r_idx = find_first_bit(q_vector->rxr_idx,
756 adapter->num_rx_queues);
757
758 for (i = 0; i < q_vector->rxr_count; i++) {
759 j = adapter->rx_ring[r_idx].reg_idx;
760 ixgbevf_set_ivar(adapter, 0, j, v_idx);
761 r_idx = find_next_bit(q_vector->rxr_idx,
762 adapter->num_rx_queues,
763 r_idx + 1);
764 }
765 r_idx = find_first_bit(q_vector->txr_idx,
766 adapter->num_tx_queues);
767
768 for (i = 0; i < q_vector->txr_count; i++) {
769 j = adapter->tx_ring[r_idx].reg_idx;
770 ixgbevf_set_ivar(adapter, 1, j, v_idx);
771 r_idx = find_next_bit(q_vector->txr_idx,
772 adapter->num_tx_queues,
773 r_idx + 1);
774 }
775
776 /* if this is a tx only vector halve the interrupt rate */
777 if (q_vector->txr_count && !q_vector->rxr_count)
778 q_vector->eitr = (adapter->eitr_param >> 1);
779 else if (q_vector->rxr_count)
780 /* rx only */
781 q_vector->eitr = adapter->eitr_param;
782
783 ixgbevf_write_eitr(adapter, v_idx, q_vector->eitr);
784 }
785
786 ixgbevf_set_ivar(adapter, -1, 1, v_idx);
787
788 /* set up to autoclear timer, and the vectors */
789 mask = IXGBE_EIMS_ENABLE_MASK;
790 mask &= ~IXGBE_EIMS_OTHER;
791 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, mask);
792}
793
794enum latency_range {
795 lowest_latency = 0,
796 low_latency = 1,
797 bulk_latency = 2,
798 latency_invalid = 255
799};
800
801/**
802 * ixgbevf_update_itr - update the dynamic ITR value based on statistics
803 * @adapter: pointer to adapter
804 * @eitr: eitr setting (ints per sec) to give last timeslice
805 * @itr_setting: current throttle rate in ints/second
806 * @packets: the number of packets during this measurement interval
807 * @bytes: the number of bytes during this measurement interval
808 *
809 * Stores a new ITR value based on packets and byte
810 * counts during the last interrupt. The advantage of per interrupt
811 * computation is faster updates and more accurate ITR for the current
812 * traffic pattern. Constants in this function were computed
813 * based on theoretical maximum wire speed and thresholds were set based
814 * on testing data as well as attempting to minimize response time
815 * while increasing bulk throughput.
816 **/
817static u8 ixgbevf_update_itr(struct ixgbevf_adapter *adapter,
818 u32 eitr, u8 itr_setting,
819 int packets, int bytes)
820{
821 unsigned int retval = itr_setting;
822 u32 timepassed_us;
823 u64 bytes_perint;
824
825 if (packets == 0)
826 goto update_itr_done;
827
828
829 /* simple throttlerate management
830 * 0-20MB/s lowest (100000 ints/s)
831 * 20-100MB/s low (20000 ints/s)
832 * 100-1249MB/s bulk (8000 ints/s)
833 */
834 /* what was last interrupt timeslice? */
835 timepassed_us = 1000000/eitr;
836 bytes_perint = bytes / timepassed_us; /* bytes/usec */
837
838 switch (itr_setting) {
839 case lowest_latency:
840 if (bytes_perint > adapter->eitr_low)
841 retval = low_latency;
842 break;
843 case low_latency:
844 if (bytes_perint > adapter->eitr_high)
845 retval = bulk_latency;
846 else if (bytes_perint <= adapter->eitr_low)
847 retval = lowest_latency;
848 break;
849 case bulk_latency:
850 if (bytes_perint <= adapter->eitr_high)
851 retval = low_latency;
852 break;
853 }
854
855update_itr_done:
856 return retval;
857}
858
859/**
860 * ixgbevf_write_eitr - write VTEITR register in hardware specific way
861 * @adapter: pointer to adapter struct
862 * @v_idx: vector index into q_vector array
863 * @itr_reg: new value to be written in *register* format, not ints/s
864 *
865 * This function is made to be called by ethtool and by the driver
866 * when it needs to update VTEITR registers at runtime. Hardware
867 * specific quirks/differences are taken care of here.
868 */
869static void ixgbevf_write_eitr(struct ixgbevf_adapter *adapter, int v_idx,
870 u32 itr_reg)
871{
872 struct ixgbe_hw *hw = &adapter->hw;
873
874 itr_reg = EITR_INTS_PER_SEC_TO_REG(itr_reg);
875
876 /*
877 * set the WDIS bit to not clear the timer bits and cause an
878 * immediate assertion of the interrupt
879 */
880 itr_reg |= IXGBE_EITR_CNT_WDIS;
881
882 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(v_idx), itr_reg);
883}
884
885static void ixgbevf_set_itr_msix(struct ixgbevf_q_vector *q_vector)
886{
887 struct ixgbevf_adapter *adapter = q_vector->adapter;
888 u32 new_itr;
889 u8 current_itr, ret_itr;
890 int i, r_idx, v_idx = q_vector->v_idx;
891 struct ixgbevf_ring *rx_ring, *tx_ring;
892
893 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
894 for (i = 0; i < q_vector->txr_count; i++) {
895 tx_ring = &(adapter->tx_ring[r_idx]);
896 ret_itr = ixgbevf_update_itr(adapter, q_vector->eitr,
897 q_vector->tx_itr,
898 tx_ring->total_packets,
899 tx_ring->total_bytes);
900 /* if the result for this queue would decrease interrupt
901 * rate for this vector then use that result */
902 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
903 q_vector->tx_itr - 1 : ret_itr);
904 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
905 r_idx + 1);
906 }
907
908 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
909 for (i = 0; i < q_vector->rxr_count; i++) {
910 rx_ring = &(adapter->rx_ring[r_idx]);
911 ret_itr = ixgbevf_update_itr(adapter, q_vector->eitr,
912 q_vector->rx_itr,
913 rx_ring->total_packets,
914 rx_ring->total_bytes);
915 /* if the result for this queue would decrease interrupt
916 * rate for this vector then use that result */
917 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
918 q_vector->rx_itr - 1 : ret_itr);
919 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
920 r_idx + 1);
921 }
922
923 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
924
925 switch (current_itr) {
926 /* counts and packets in update_itr are dependent on these numbers */
927 case lowest_latency:
928 new_itr = 100000;
929 break;
930 case low_latency:
931 new_itr = 20000; /* aka hwitr = ~200 */
932 break;
933 case bulk_latency:
934 default:
935 new_itr = 8000;
936 break;
937 }
938
939 if (new_itr != q_vector->eitr) {
940 u32 itr_reg;
941
942 /* save the algorithm value here, not the smoothed one */
943 q_vector->eitr = new_itr;
944 /* do an exponential smoothing */
945 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
946 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
947 ixgbevf_write_eitr(adapter, v_idx, itr_reg);
948 }
949
950 return;
951}
952
953static irqreturn_t ixgbevf_msix_mbx(int irq, void *data)
954{
955 struct net_device *netdev = data;
956 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
957 struct ixgbe_hw *hw = &adapter->hw;
958 u32 eicr;
959 u32 msg;
960
961 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICS);
962 IXGBE_WRITE_REG(hw, IXGBE_VTEICR, eicr);
963
964 hw->mbx.ops.read(hw, &msg, 1);
965
966 if ((msg & IXGBE_MBVFICR_VFREQ_MASK) == IXGBE_PF_CONTROL_MSG)
967 mod_timer(&adapter->watchdog_timer,
968 round_jiffies(jiffies + 10));
969
970 return IRQ_HANDLED;
971}
972
973static irqreturn_t ixgbevf_msix_clean_tx(int irq, void *data)
974{
975 struct ixgbevf_q_vector *q_vector = data;
976 struct ixgbevf_adapter *adapter = q_vector->adapter;
977 struct ixgbevf_ring *tx_ring;
978 int i, r_idx;
979
980 if (!q_vector->txr_count)
981 return IRQ_HANDLED;
982
983 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
984 for (i = 0; i < q_vector->txr_count; i++) {
985 tx_ring = &(adapter->tx_ring[r_idx]);
986 tx_ring->total_bytes = 0;
987 tx_ring->total_packets = 0;
988 ixgbevf_clean_tx_irq(adapter, tx_ring);
989 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
990 r_idx + 1);
991 }
992
993 if (adapter->itr_setting & 1)
994 ixgbevf_set_itr_msix(q_vector);
995
996 return IRQ_HANDLED;
997}
998
999/**
1000 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1001 * @irq: unused
1002 * @data: pointer to our q_vector struct for this interrupt vector
1003 **/
1004static irqreturn_t ixgbevf_msix_clean_rx(int irq, void *data)
1005{
1006 struct ixgbevf_q_vector *q_vector = data;
1007 struct ixgbevf_adapter *adapter = q_vector->adapter;
1008 struct ixgbe_hw *hw = &adapter->hw;
1009 struct ixgbevf_ring *rx_ring;
1010 int r_idx;
1011 int i;
1012
1013 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1014 for (i = 0; i < q_vector->rxr_count; i++) {
1015 rx_ring = &(adapter->rx_ring[r_idx]);
1016 rx_ring->total_bytes = 0;
1017 rx_ring->total_packets = 0;
1018 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1019 r_idx + 1);
1020 }
1021
1022 if (!q_vector->rxr_count)
1023 return IRQ_HANDLED;
1024
1025 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1026 rx_ring = &(adapter->rx_ring[r_idx]);
1027 /* disable interrupts on this vector only */
1028 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, rx_ring->v_idx);
1029 napi_schedule(&q_vector->napi);
1030
1031
1032 return IRQ_HANDLED;
1033}
1034
1035static irqreturn_t ixgbevf_msix_clean_many(int irq, void *data)
1036{
1037 ixgbevf_msix_clean_rx(irq, data);
1038 ixgbevf_msix_clean_tx(irq, data);
1039
1040 return IRQ_HANDLED;
1041}
1042
1043static inline void map_vector_to_rxq(struct ixgbevf_adapter *a, int v_idx,
1044 int r_idx)
1045{
1046 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
1047
1048 set_bit(r_idx, q_vector->rxr_idx);
1049 q_vector->rxr_count++;
1050 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1051}
1052
1053static inline void map_vector_to_txq(struct ixgbevf_adapter *a, int v_idx,
1054 int t_idx)
1055{
1056 struct ixgbevf_q_vector *q_vector = a->q_vector[v_idx];
1057
1058 set_bit(t_idx, q_vector->txr_idx);
1059 q_vector->txr_count++;
1060 a->tx_ring[t_idx].v_idx = 1 << v_idx;
1061}
1062
1063/**
1064 * ixgbevf_map_rings_to_vectors - Maps descriptor rings to vectors
1065 * @adapter: board private structure to initialize
1066 *
1067 * This function maps descriptor rings to the queue-specific vectors
1068 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1069 * one vector per ring/queue, but on a constrained vector budget, we
1070 * group the rings as "efficiently" as possible. You would add new
1071 * mapping configurations in here.
1072 **/
1073static int ixgbevf_map_rings_to_vectors(struct ixgbevf_adapter *adapter)
1074{
1075 int q_vectors;
1076 int v_start = 0;
1077 int rxr_idx = 0, txr_idx = 0;
1078 int rxr_remaining = adapter->num_rx_queues;
1079 int txr_remaining = adapter->num_tx_queues;
1080 int i, j;
1081 int rqpv, tqpv;
1082 int err = 0;
1083
1084 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1085
1086 /*
1087 * The ideal configuration...
1088 * We have enough vectors to map one per queue.
1089 */
1090 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1091 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1092 map_vector_to_rxq(adapter, v_start, rxr_idx);
1093
1094 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1095 map_vector_to_txq(adapter, v_start, txr_idx);
1096 goto out;
1097 }
1098
1099 /*
1100 * If we don't have enough vectors for a 1-to-1
1101 * mapping, we'll have to group them so there are
1102 * multiple queues per vector.
1103 */
1104 /* Re-adjusting *qpv takes care of the remainder. */
1105 for (i = v_start; i < q_vectors; i++) {
1106 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
1107 for (j = 0; j < rqpv; j++) {
1108 map_vector_to_rxq(adapter, i, rxr_idx);
1109 rxr_idx++;
1110 rxr_remaining--;
1111 }
1112 }
1113 for (i = v_start; i < q_vectors; i++) {
1114 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
1115 for (j = 0; j < tqpv; j++) {
1116 map_vector_to_txq(adapter, i, txr_idx);
1117 txr_idx++;
1118 txr_remaining--;
1119 }
1120 }
1121
1122out:
1123 return err;
1124}
1125
1126/**
1127 * ixgbevf_request_msix_irqs - Initialize MSI-X interrupts
1128 * @adapter: board private structure
1129 *
1130 * ixgbevf_request_msix_irqs allocates MSI-X vectors and requests
1131 * interrupts from the kernel.
1132 **/
1133static int ixgbevf_request_msix_irqs(struct ixgbevf_adapter *adapter)
1134{
1135 struct net_device *netdev = adapter->netdev;
1136 irqreturn_t (*handler)(int, void *);
1137 int i, vector, q_vectors, err;
1138 int ri = 0, ti = 0;
1139
1140 /* Decrement for Other and TCP Timer vectors */
1141 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1142
1143#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
1144 ? &ixgbevf_msix_clean_many : \
1145 (_v)->rxr_count ? &ixgbevf_msix_clean_rx : \
1146 (_v)->txr_count ? &ixgbevf_msix_clean_tx : \
1147 NULL)
1148 for (vector = 0; vector < q_vectors; vector++) {
1149 handler = SET_HANDLER(adapter->q_vector[vector]);
1150
1151 if (handler == &ixgbevf_msix_clean_rx) {
1152 sprintf(adapter->name[vector], "%s-%s-%d",
1153 netdev->name, "rx", ri++);
1154 } else if (handler == &ixgbevf_msix_clean_tx) {
1155 sprintf(adapter->name[vector], "%s-%s-%d",
1156 netdev->name, "tx", ti++);
1157 } else if (handler == &ixgbevf_msix_clean_many) {
1158 sprintf(adapter->name[vector], "%s-%s-%d",
1159 netdev->name, "TxRx", vector);
1160 } else {
1161 /* skip this unused q_vector */
1162 continue;
1163 }
1164 err = request_irq(adapter->msix_entries[vector].vector,
1165 handler, 0, adapter->name[vector],
1166 adapter->q_vector[vector]);
1167 if (err) {
1168 hw_dbg(&adapter->hw,
1169 "request_irq failed for MSIX interrupt "
1170 "Error: %d\n", err);
1171 goto free_queue_irqs;
1172 }
1173 }
1174
1175 sprintf(adapter->name[vector], "%s:mbx", netdev->name);
1176 err = request_irq(adapter->msix_entries[vector].vector,
1177 &ixgbevf_msix_mbx, 0, adapter->name[vector], netdev);
1178 if (err) {
1179 hw_dbg(&adapter->hw,
1180 "request_irq for msix_mbx failed: %d\n", err);
1181 goto free_queue_irqs;
1182 }
1183
1184 return 0;
1185
1186free_queue_irqs:
1187 for (i = vector - 1; i >= 0; i--)
1188 free_irq(adapter->msix_entries[--vector].vector,
1189 &(adapter->q_vector[i]));
1190 pci_disable_msix(adapter->pdev);
1191 kfree(adapter->msix_entries);
1192 adapter->msix_entries = NULL;
1193 return err;
1194}
1195
1196static inline void ixgbevf_reset_q_vectors(struct ixgbevf_adapter *adapter)
1197{
1198 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1199
1200 for (i = 0; i < q_vectors; i++) {
1201 struct ixgbevf_q_vector *q_vector = adapter->q_vector[i];
1202 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1203 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1204 q_vector->rxr_count = 0;
1205 q_vector->txr_count = 0;
1206 q_vector->eitr = adapter->eitr_param;
1207 }
1208}
1209
1210/**
1211 * ixgbevf_request_irq - initialize interrupts
1212 * @adapter: board private structure
1213 *
1214 * Attempts to configure interrupts using the best available
1215 * capabilities of the hardware and kernel.
1216 **/
1217static int ixgbevf_request_irq(struct ixgbevf_adapter *adapter)
1218{
1219 int err = 0;
1220
1221 err = ixgbevf_request_msix_irqs(adapter);
1222
1223 if (err)
1224 hw_dbg(&adapter->hw,
1225 "request_irq failed, Error %d\n", err);
1226
1227 return err;
1228}
1229
1230static void ixgbevf_free_irq(struct ixgbevf_adapter *adapter)
1231{
1232 struct net_device *netdev = adapter->netdev;
1233 int i, q_vectors;
1234
1235 q_vectors = adapter->num_msix_vectors;
1236
1237 i = q_vectors - 1;
1238
1239 free_irq(adapter->msix_entries[i].vector, netdev);
1240 i--;
1241
1242 for (; i >= 0; i--) {
1243 free_irq(adapter->msix_entries[i].vector,
1244 adapter->q_vector[i]);
1245 }
1246
1247 ixgbevf_reset_q_vectors(adapter);
1248}
1249
1250/**
1251 * ixgbevf_irq_disable - Mask off interrupt generation on the NIC
1252 * @adapter: board private structure
1253 **/
1254static inline void ixgbevf_irq_disable(struct ixgbevf_adapter *adapter)
1255{
1256 int i;
1257 struct ixgbe_hw *hw = &adapter->hw;
1258
1259 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, ~0);
1260
1261 IXGBE_WRITE_FLUSH(hw);
1262
1263 for (i = 0; i < adapter->num_msix_vectors; i++)
1264 synchronize_irq(adapter->msix_entries[i].vector);
1265}
1266
1267/**
1268 * ixgbevf_irq_enable - Enable default interrupt generation settings
1269 * @adapter: board private structure
1270 **/
1271static inline void ixgbevf_irq_enable(struct ixgbevf_adapter *adapter,
1272 bool queues, bool flush)
1273{
1274 struct ixgbe_hw *hw = &adapter->hw;
1275 u32 mask;
1276 u64 qmask;
1277
1278 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1279 qmask = ~0;
1280
1281 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
1282
1283 if (queues)
1284 ixgbevf_irq_enable_queues(adapter, qmask);
1285
1286 if (flush)
1287 IXGBE_WRITE_FLUSH(hw);
1288}
1289
1290/**
1291 * ixgbevf_configure_tx - Configure 82599 VF Transmit Unit after Reset
1292 * @adapter: board private structure
1293 *
1294 * Configure the Tx unit of the MAC after a reset.
1295 **/
1296static void ixgbevf_configure_tx(struct ixgbevf_adapter *adapter)
1297{
1298 u64 tdba;
1299 struct ixgbe_hw *hw = &adapter->hw;
1300 u32 i, j, tdlen, txctrl;
1301
1302 /* Setup the HW Tx Head and Tail descriptor pointers */
1303 for (i = 0; i < adapter->num_tx_queues; i++) {
1304 struct ixgbevf_ring *ring = &adapter->tx_ring[i];
1305 j = ring->reg_idx;
1306 tdba = ring->dma;
1307 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1308 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(j),
1309 (tdba & DMA_BIT_MASK(32)));
1310 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(j), (tdba >> 32));
1311 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(j), tdlen);
1312 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(j), 0);
1313 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(j), 0);
1314 adapter->tx_ring[i].head = IXGBE_VFTDH(j);
1315 adapter->tx_ring[i].tail = IXGBE_VFTDT(j);
1316 /* Disable Tx Head Writeback RO bit, since this hoses
1317 * bookkeeping if things aren't delivered in order.
1318 */
1319 txctrl = IXGBE_READ_REG(hw, IXGBE_VFDCA_TXCTRL(j));
1320 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1321 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(j), txctrl);
1322 }
1323}
1324
1325#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1326
1327static void ixgbevf_configure_srrctl(struct ixgbevf_adapter *adapter, int index)
1328{
1329 struct ixgbevf_ring *rx_ring;
1330 struct ixgbe_hw *hw = &adapter->hw;
1331 u32 srrctl;
1332
1333 rx_ring = &adapter->rx_ring[index];
1334
1335 srrctl = IXGBE_SRRCTL_DROP_EN;
1336
1337 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1338 u16 bufsz = IXGBEVF_RXBUFFER_2048;
1339 /* grow the amount we can receive on large page machines */
1340 if (bufsz < (PAGE_SIZE / 2))
1341 bufsz = (PAGE_SIZE / 2);
1342 /* cap the bufsz at our largest descriptor size */
1343 bufsz = min((u16)IXGBEVF_MAX_RXBUFFER, bufsz);
1344
1345 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1346 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1347 srrctl |= ((IXGBEVF_RX_HDR_SIZE <<
1348 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1349 IXGBE_SRRCTL_BSIZEHDR_MASK);
1350 } else {
1351 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1352
1353 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1354 srrctl |= IXGBEVF_RXBUFFER_2048 >>
1355 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1356 else
1357 srrctl |= rx_ring->rx_buf_len >>
1358 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1359 }
1360 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(index), srrctl);
1361}
1362
1363/**
1364 * ixgbevf_configure_rx - Configure 82599 VF Receive Unit after Reset
1365 * @adapter: board private structure
1366 *
1367 * Configure the Rx unit of the MAC after a reset.
1368 **/
1369static void ixgbevf_configure_rx(struct ixgbevf_adapter *adapter)
1370{
1371 u64 rdba;
1372 struct ixgbe_hw *hw = &adapter->hw;
1373 struct net_device *netdev = adapter->netdev;
1374 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1375 int i, j;
1376 u32 rdlen;
1377 int rx_buf_len;
1378
1379 /* Decide whether to use packet split mode or not */
1380 if (netdev->mtu > ETH_DATA_LEN) {
1381 if (adapter->flags & IXGBE_FLAG_RX_PS_CAPABLE)
1382 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1383 else
1384 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1385 } else {
1386 if (adapter->flags & IXGBE_FLAG_RX_1BUF_CAPABLE)
1387 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1388 else
1389 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1390 }
1391
1392 /* Set the RX buffer length according to the mode */
1393 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1394 /* PSRTYPE must be initialized in 82599 */
1395 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1396 IXGBE_PSRTYPE_UDPHDR |
1397 IXGBE_PSRTYPE_IPV4HDR |
1398 IXGBE_PSRTYPE_IPV6HDR |
1399 IXGBE_PSRTYPE_L2HDR;
1400 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
1401 rx_buf_len = IXGBEVF_RX_HDR_SIZE;
1402 } else {
1403 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);
1404 if (netdev->mtu <= ETH_DATA_LEN)
1405 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1406 else
1407 rx_buf_len = ALIGN(max_frame, 1024);
1408 }
1409
1410 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1411 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1412 * the Base and Length of the Rx Descriptor Ring */
1413 for (i = 0; i < adapter->num_rx_queues; i++) {
1414 rdba = adapter->rx_ring[i].dma;
1415 j = adapter->rx_ring[i].reg_idx;
1416 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(j),
1417 (rdba & DMA_BIT_MASK(32)));
1418 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(j), (rdba >> 32));
1419 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(j), rdlen);
1420 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(j), 0);
1421 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(j), 0);
1422 adapter->rx_ring[i].head = IXGBE_VFRDH(j);
1423 adapter->rx_ring[i].tail = IXGBE_VFRDT(j);
1424 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1425
1426 ixgbevf_configure_srrctl(adapter, j);
1427 }
1428}
1429
1430static void ixgbevf_vlan_rx_register(struct net_device *netdev,
1431 struct vlan_group *grp)
1432{
1433 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1434 struct ixgbe_hw *hw = &adapter->hw;
1435 int i, j;
1436 u32 ctrl;
1437
1438 adapter->vlgrp = grp;
1439
1440 for (i = 0; i < adapter->num_rx_queues; i++) {
1441 j = adapter->rx_ring[i].reg_idx;
1442 ctrl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j));
1443 ctrl |= IXGBE_RXDCTL_VME;
1444 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(j), ctrl);
1445 }
1446}
1447
1448static void ixgbevf_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1449{
1450 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1451 struct ixgbe_hw *hw = &adapter->hw;
1452 struct net_device *v_netdev;
1453
1454 /* add VID to filter table */
1455 if (hw->mac.ops.set_vfta)
1456 hw->mac.ops.set_vfta(hw, vid, 0, true);
1457 /*
1458 * Copy feature flags from netdev to the vlan netdev for this vid.
1459 * This allows things like TSO to bubble down to our vlan device.
1460 */
1461 v_netdev = vlan_group_get_device(adapter->vlgrp, vid);
1462 v_netdev->features |= adapter->netdev->features;
1463 vlan_group_set_device(adapter->vlgrp, vid, v_netdev);
1464}
1465
1466static void ixgbevf_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1467{
1468 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1469 struct ixgbe_hw *hw = &adapter->hw;
1470
1471 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
1472 ixgbevf_irq_disable(adapter);
1473
1474 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1475
1476 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
1477 ixgbevf_irq_enable(adapter, true, true);
1478
1479 /* remove VID from filter table */
1480 if (hw->mac.ops.set_vfta)
1481 hw->mac.ops.set_vfta(hw, vid, 0, false);
1482}
1483
1484static void ixgbevf_restore_vlan(struct ixgbevf_adapter *adapter)
1485{
1486 ixgbevf_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1487
1488 if (adapter->vlgrp) {
1489 u16 vid;
1490 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1491 if (!vlan_group_get_device(adapter->vlgrp, vid))
1492 continue;
1493 ixgbevf_vlan_rx_add_vid(adapter->netdev, vid);
1494 }
1495 }
1496}
1497
1498static u8 *ixgbevf_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr,
1499 u32 *vmdq)
1500{
1501 struct dev_mc_list *mc_ptr;
1502 u8 *addr = *mc_addr_ptr;
1503 *vmdq = 0;
1504
1505 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1506 if (mc_ptr->next)
1507 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1508 else
1509 *mc_addr_ptr = NULL;
1510
1511 return addr;
1512}
1513
1514/**
1515 * ixgbevf_set_rx_mode - Multicast set
1516 * @netdev: network interface device structure
1517 *
1518 * The set_rx_method entry point is called whenever the multicast address
1519 * list or the network interface flags are updated. This routine is
1520 * responsible for configuring the hardware for proper multicast mode.
1521 **/
1522static void ixgbevf_set_rx_mode(struct net_device *netdev)
1523{
1524 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
1525 struct ixgbe_hw *hw = &adapter->hw;
1526 u8 *addr_list = NULL;
1527 int addr_count = 0;
1528
1529 /* reprogram multicast list */
1530 addr_count = netdev_mc_count(netdev);
1531 if (addr_count)
1532 addr_list = netdev->mc_list->dmi_addr;
1533 if (hw->mac.ops.update_mc_addr_list)
1534 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1535 ixgbevf_addr_list_itr);
1536}
1537
1538static void ixgbevf_napi_enable_all(struct ixgbevf_adapter *adapter)
1539{
1540 int q_idx;
1541 struct ixgbevf_q_vector *q_vector;
1542 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1543
1544 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1545 struct napi_struct *napi;
1546 q_vector = adapter->q_vector[q_idx];
1547 if (!q_vector->rxr_count)
1548 continue;
1549 napi = &q_vector->napi;
1550 if (q_vector->rxr_count > 1)
1551 napi->poll = &ixgbevf_clean_rxonly_many;
1552
1553 napi_enable(napi);
1554 }
1555}
1556
1557static void ixgbevf_napi_disable_all(struct ixgbevf_adapter *adapter)
1558{
1559 int q_idx;
1560 struct ixgbevf_q_vector *q_vector;
1561 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1562
1563 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1564 q_vector = adapter->q_vector[q_idx];
1565 if (!q_vector->rxr_count)
1566 continue;
1567 napi_disable(&q_vector->napi);
1568 }
1569}
1570
1571static void ixgbevf_configure(struct ixgbevf_adapter *adapter)
1572{
1573 struct net_device *netdev = adapter->netdev;
1574 int i;
1575
1576 ixgbevf_set_rx_mode(netdev);
1577
1578 ixgbevf_restore_vlan(adapter);
1579
1580 ixgbevf_configure_tx(adapter);
1581 ixgbevf_configure_rx(adapter);
1582 for (i = 0; i < adapter->num_rx_queues; i++) {
1583 struct ixgbevf_ring *ring = &adapter->rx_ring[i];
1584 ixgbevf_alloc_rx_buffers(adapter, ring, ring->count);
1585 ring->next_to_use = ring->count - 1;
1586 writel(ring->next_to_use, adapter->hw.hw_addr + ring->tail);
1587 }
1588}
1589
1590#define IXGBE_MAX_RX_DESC_POLL 10
1591static inline void ixgbevf_rx_desc_queue_enable(struct ixgbevf_adapter *adapter,
1592 int rxr)
1593{
1594 struct ixgbe_hw *hw = &adapter->hw;
1595 int j = adapter->rx_ring[rxr].reg_idx;
1596 int k;
1597
1598 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
1599 if (IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1600 break;
1601 else
1602 msleep(1);
1603 }
1604 if (k >= IXGBE_MAX_RX_DESC_POLL) {
1605 hw_dbg(hw, "RXDCTL.ENABLE on Rx queue %d "
1606 "not set within the polling period\n", rxr);
1607 }
1608
1609 ixgbevf_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
1610 (adapter->rx_ring[rxr].count - 1));
1611}
1612
1613static int ixgbevf_up_complete(struct ixgbevf_adapter *adapter)
1614{
1615 struct net_device *netdev = adapter->netdev;
1616 struct ixgbe_hw *hw = &adapter->hw;
1617 int i, j = 0;
1618 int num_rx_rings = adapter->num_rx_queues;
1619 u32 txdctl, rxdctl;
1620
1621 for (i = 0; i < adapter->num_tx_queues; i++) {
1622 j = adapter->tx_ring[i].reg_idx;
1623 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1624 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1625 txdctl |= (8 << 16);
1626 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
1627 }
1628
1629 for (i = 0; i < adapter->num_tx_queues; i++) {
1630 j = adapter->tx_ring[i].reg_idx;
1631 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1632 txdctl |= IXGBE_TXDCTL_ENABLE;
1633 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl);
1634 }
1635
1636 for (i = 0; i < num_rx_rings; i++) {
1637 j = adapter->rx_ring[i].reg_idx;
1638 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(j));
1639 rxdctl |= IXGBE_RXDCTL_ENABLE;
1640 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(j), rxdctl);
1641 ixgbevf_rx_desc_queue_enable(adapter, i);
1642 }
1643
1644 ixgbevf_configure_msix(adapter);
1645
1646 if (hw->mac.ops.set_rar) {
1647 if (is_valid_ether_addr(hw->mac.addr))
1648 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
1649 else
1650 hw->mac.ops.set_rar(hw, 0, hw->mac.perm_addr, 0);
1651 }
1652
1653 clear_bit(__IXGBEVF_DOWN, &adapter->state);
1654 ixgbevf_napi_enable_all(adapter);
1655
1656 /* enable transmits */
1657 netif_tx_start_all_queues(netdev);
1658
1659 /* bring the link up in the watchdog, this could race with our first
1660 * link up interrupt but shouldn't be a problem */
1661 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1662 adapter->link_check_timeout = jiffies;
1663 mod_timer(&adapter->watchdog_timer, jiffies);
1664 return 0;
1665}
1666
1667int ixgbevf_up(struct ixgbevf_adapter *adapter)
1668{
1669 int err;
1670 struct ixgbe_hw *hw = &adapter->hw;
1671
1672 ixgbevf_configure(adapter);
1673
1674 err = ixgbevf_up_complete(adapter);
1675
1676 /* clear any pending interrupts, may auto mask */
1677 IXGBE_READ_REG(hw, IXGBE_VTEICR);
1678
1679 ixgbevf_irq_enable(adapter, true, true);
1680
1681 return err;
1682}
1683
1684/**
1685 * ixgbevf_clean_rx_ring - Free Rx Buffers per Queue
1686 * @adapter: board private structure
1687 * @rx_ring: ring to free buffers from
1688 **/
1689static void ixgbevf_clean_rx_ring(struct ixgbevf_adapter *adapter,
1690 struct ixgbevf_ring *rx_ring)
1691{
1692 struct pci_dev *pdev = adapter->pdev;
1693 unsigned long size;
1694 unsigned int i;
1695
1696 if (!rx_ring->rx_buffer_info)
1697 return;
1698
1699 /* Free all the Rx ring sk_buffs */
1700 for (i = 0; i < rx_ring->count; i++) {
1701 struct ixgbevf_rx_buffer *rx_buffer_info;
1702
1703 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1704 if (rx_buffer_info->dma) {
1705 pci_unmap_single(pdev, rx_buffer_info->dma,
1706 rx_ring->rx_buf_len,
1707 PCI_DMA_FROMDEVICE);
1708 rx_buffer_info->dma = 0;
1709 }
1710 if (rx_buffer_info->skb) {
1711 struct sk_buff *skb = rx_buffer_info->skb;
1712 rx_buffer_info->skb = NULL;
1713 do {
1714 struct sk_buff *this = skb;
1715 skb = skb->prev;
1716 dev_kfree_skb(this);
1717 } while (skb);
1718 }
1719 if (!rx_buffer_info->page)
1720 continue;
1721 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
1722 PCI_DMA_FROMDEVICE);
1723 rx_buffer_info->page_dma = 0;
1724 put_page(rx_buffer_info->page);
1725 rx_buffer_info->page = NULL;
1726 rx_buffer_info->page_offset = 0;
1727 }
1728
1729 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
1730 memset(rx_ring->rx_buffer_info, 0, size);
1731
1732 /* Zero out the descriptor ring */
1733 memset(rx_ring->desc, 0, rx_ring->size);
1734
1735 rx_ring->next_to_clean = 0;
1736 rx_ring->next_to_use = 0;
1737
1738 if (rx_ring->head)
1739 writel(0, adapter->hw.hw_addr + rx_ring->head);
1740 if (rx_ring->tail)
1741 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1742}
1743
1744/**
1745 * ixgbevf_clean_tx_ring - Free Tx Buffers
1746 * @adapter: board private structure
1747 * @tx_ring: ring to be cleaned
1748 **/
1749static void ixgbevf_clean_tx_ring(struct ixgbevf_adapter *adapter,
1750 struct ixgbevf_ring *tx_ring)
1751{
1752 struct ixgbevf_tx_buffer *tx_buffer_info;
1753 unsigned long size;
1754 unsigned int i;
1755
1756 if (!tx_ring->tx_buffer_info)
1757 return;
1758
1759 /* Free all the Tx ring sk_buffs */
1760
1761 for (i = 0; i < tx_ring->count; i++) {
1762 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1763 ixgbevf_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1764 }
1765
1766 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
1767 memset(tx_ring->tx_buffer_info, 0, size);
1768
1769 memset(tx_ring->desc, 0, tx_ring->size);
1770
1771 tx_ring->next_to_use = 0;
1772 tx_ring->next_to_clean = 0;
1773
1774 if (tx_ring->head)
1775 writel(0, adapter->hw.hw_addr + tx_ring->head);
1776 if (tx_ring->tail)
1777 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1778}
1779
1780/**
1781 * ixgbevf_clean_all_rx_rings - Free Rx Buffers for all queues
1782 * @adapter: board private structure
1783 **/
1784static void ixgbevf_clean_all_rx_rings(struct ixgbevf_adapter *adapter)
1785{
1786 int i;
1787
1788 for (i = 0; i < adapter->num_rx_queues; i++)
1789 ixgbevf_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1790}
1791
1792/**
1793 * ixgbevf_clean_all_tx_rings - Free Tx Buffers for all queues
1794 * @adapter: board private structure
1795 **/
1796static void ixgbevf_clean_all_tx_rings(struct ixgbevf_adapter *adapter)
1797{
1798 int i;
1799
1800 for (i = 0; i < adapter->num_tx_queues; i++)
1801 ixgbevf_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1802}
1803
1804void ixgbevf_down(struct ixgbevf_adapter *adapter)
1805{
1806 struct net_device *netdev = adapter->netdev;
1807 struct ixgbe_hw *hw = &adapter->hw;
1808 u32 txdctl;
1809 int i, j;
1810
1811 /* signal that we are down to the interrupt handler */
1812 set_bit(__IXGBEVF_DOWN, &adapter->state);
1813 /* disable receives */
1814
1815 netif_tx_disable(netdev);
1816
1817 msleep(10);
1818
1819 netif_tx_stop_all_queues(netdev);
1820
1821 ixgbevf_irq_disable(adapter);
1822
1823 ixgbevf_napi_disable_all(adapter);
1824
1825 del_timer_sync(&adapter->watchdog_timer);
1826 /* can't call flush scheduled work here because it can deadlock
1827 * if linkwatch_event tries to acquire the rtnl_lock which we are
1828 * holding */
1829 while (adapter->flags & IXGBE_FLAG_IN_WATCHDOG_TASK)
1830 msleep(1);
1831
1832 /* disable transmits in the hardware now that interrupts are off */
1833 for (i = 0; i < adapter->num_tx_queues; i++) {
1834 j = adapter->tx_ring[i].reg_idx;
1835 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(j));
1836 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j),
1837 (txdctl & ~IXGBE_TXDCTL_ENABLE));
1838 }
1839
1840 netif_carrier_off(netdev);
1841
1842 if (!pci_channel_offline(adapter->pdev))
1843 ixgbevf_reset(adapter);
1844
1845 ixgbevf_clean_all_tx_rings(adapter);
1846 ixgbevf_clean_all_rx_rings(adapter);
1847}
1848
1849void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter)
1850{
1851 struct ixgbe_hw *hw = &adapter->hw;
1852
1853 WARN_ON(in_interrupt());
1854
1855 while (test_and_set_bit(__IXGBEVF_RESETTING, &adapter->state))
1856 msleep(1);
1857
1858 /*
1859 * Check if PF is up before re-init. If not then skip until
1860 * later when the PF is up and ready to service requests from
1861 * the VF via mailbox. If the VF is up and running then the
1862 * watchdog task will continue to schedule reset tasks until
1863 * the PF is up and running.
1864 */
1865 if (!hw->mac.ops.reset_hw(hw)) {
1866 ixgbevf_down(adapter);
1867 ixgbevf_up(adapter);
1868 }
1869
1870 clear_bit(__IXGBEVF_RESETTING, &adapter->state);
1871}
1872
1873void ixgbevf_reset(struct ixgbevf_adapter *adapter)
1874{
1875 struct ixgbe_hw *hw = &adapter->hw;
1876 struct net_device *netdev = adapter->netdev;
1877
1878 if (hw->mac.ops.reset_hw(hw))
1879 hw_dbg(hw, "PF still resetting\n");
1880 else
1881 hw->mac.ops.init_hw(hw);
1882
1883 if (is_valid_ether_addr(adapter->hw.mac.addr)) {
1884 memcpy(netdev->dev_addr, adapter->hw.mac.addr,
1885 netdev->addr_len);
1886 memcpy(netdev->perm_addr, adapter->hw.mac.addr,
1887 netdev->addr_len);
1888 }
1889}
1890
1891static void ixgbevf_acquire_msix_vectors(struct ixgbevf_adapter *adapter,
1892 int vectors)
1893{
1894 int err, vector_threshold;
1895
1896 /* We'll want at least 3 (vector_threshold):
1897 * 1) TxQ[0] Cleanup
1898 * 2) RxQ[0] Cleanup
1899 * 3) Other (Link Status Change, etc.)
1900 */
1901 vector_threshold = MIN_MSIX_COUNT;
1902
1903 /* The more we get, the more we will assign to Tx/Rx Cleanup
1904 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
1905 * Right now, we simply care about how many we'll get; we'll
1906 * set them up later while requesting irq's.
1907 */
1908 while (vectors >= vector_threshold) {
1909 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1910 vectors);
1911 if (!err) /* Success in acquiring all requested vectors. */
1912 break;
1913 else if (err < 0)
1914 vectors = 0; /* Nasty failure, quit now */
1915 else /* err == number of vectors we should try again with */
1916 vectors = err;
1917 }
1918
1919 if (vectors < vector_threshold) {
1920 /* Can't allocate enough MSI-X interrupts? Oh well.
1921 * This just means we'll go with either a single MSI
1922 * vector or fall back to legacy interrupts.
1923 */
1924 hw_dbg(&adapter->hw,
1925 "Unable to allocate MSI-X interrupts\n");
1926 kfree(adapter->msix_entries);
1927 adapter->msix_entries = NULL;
1928 } else {
1929 /*
1930 * Adjust for only the vectors we'll use, which is minimum
1931 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
1932 * vectors we were allocated.
1933 */
1934 adapter->num_msix_vectors = vectors;
1935 }
1936}
1937
1938/*
1939 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
1940 * @adapter: board private structure to initialize
1941 *
1942 * This is the top level queue allocation routine. The order here is very
1943 * important, starting with the "most" number of features turned on at once,
1944 * and ending with the smallest set of features. This way large combinations
1945 * can be allocated if they're turned on, and smaller combinations are the
1946 * fallthrough conditions.
1947 *
1948 **/
1949static void ixgbevf_set_num_queues(struct ixgbevf_adapter *adapter)
1950{
1951 /* Start with base case */
1952 adapter->num_rx_queues = 1;
1953 adapter->num_tx_queues = 1;
1954 adapter->num_rx_pools = adapter->num_rx_queues;
1955 adapter->num_rx_queues_per_pool = 1;
1956}
1957
1958/**
1959 * ixgbevf_alloc_queues - Allocate memory for all rings
1960 * @adapter: board private structure to initialize
1961 *
1962 * We allocate one ring per queue at run-time since we don't know the
1963 * number of queues at compile-time. The polling_netdev array is
1964 * intended for Multiqueue, but should work fine with a single queue.
1965 **/
1966static int ixgbevf_alloc_queues(struct ixgbevf_adapter *adapter)
1967{
1968 int i;
1969
1970 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1971 sizeof(struct ixgbevf_ring), GFP_KERNEL);
1972 if (!adapter->tx_ring)
1973 goto err_tx_ring_allocation;
1974
1975 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1976 sizeof(struct ixgbevf_ring), GFP_KERNEL);
1977 if (!adapter->rx_ring)
1978 goto err_rx_ring_allocation;
1979
1980 for (i = 0; i < adapter->num_tx_queues; i++) {
1981 adapter->tx_ring[i].count = adapter->tx_ring_count;
1982 adapter->tx_ring[i].queue_index = i;
1983 adapter->tx_ring[i].reg_idx = i;
1984 }
1985
1986 for (i = 0; i < adapter->num_rx_queues; i++) {
1987 adapter->rx_ring[i].count = adapter->rx_ring_count;
1988 adapter->rx_ring[i].queue_index = i;
1989 adapter->rx_ring[i].reg_idx = i;
1990 }
1991
1992 return 0;
1993
1994err_rx_ring_allocation:
1995 kfree(adapter->tx_ring);
1996err_tx_ring_allocation:
1997 return -ENOMEM;
1998}
1999
2000/**
2001 * ixgbevf_set_interrupt_capability - set MSI-X or FAIL if not supported
2002 * @adapter: board private structure to initialize
2003 *
2004 * Attempt to configure the interrupts using the best available
2005 * capabilities of the hardware and the kernel.
2006 **/
2007static int ixgbevf_set_interrupt_capability(struct ixgbevf_adapter *adapter)
2008{
2009 int err = 0;
2010 int vector, v_budget;
2011
2012 /*
2013 * It's easy to be greedy for MSI-X vectors, but it really
2014 * doesn't do us much good if we have a lot more vectors
2015 * than CPU's. So let's be conservative and only ask for
2016 * (roughly) twice the number of vectors as there are CPU's.
2017 */
2018 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2019 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2020
2021 /* A failure in MSI-X entry allocation isn't fatal, but it does
2022 * mean we disable MSI-X capabilities of the adapter. */
2023 adapter->msix_entries = kcalloc(v_budget,
2024 sizeof(struct msix_entry), GFP_KERNEL);
2025 if (!adapter->msix_entries) {
2026 err = -ENOMEM;
2027 goto out;
2028 }
2029
2030 for (vector = 0; vector < v_budget; vector++)
2031 adapter->msix_entries[vector].entry = vector;
2032
2033 ixgbevf_acquire_msix_vectors(adapter, v_budget);
2034
2035out:
2036 return err;
2037}
2038
2039/**
2040 * ixgbevf_alloc_q_vectors - Allocate memory for interrupt vectors
2041 * @adapter: board private structure to initialize
2042 *
2043 * We allocate one q_vector per queue interrupt. If allocation fails we
2044 * return -ENOMEM.
2045 **/
2046static int ixgbevf_alloc_q_vectors(struct ixgbevf_adapter *adapter)
2047{
2048 int q_idx, num_q_vectors;
2049 struct ixgbevf_q_vector *q_vector;
2050 int napi_vectors;
2051 int (*poll)(struct napi_struct *, int);
2052
2053 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2054 napi_vectors = adapter->num_rx_queues;
2055 poll = &ixgbevf_clean_rxonly;
2056
2057 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
2058 q_vector = kzalloc(sizeof(struct ixgbevf_q_vector), GFP_KERNEL);
2059 if (!q_vector)
2060 goto err_out;
2061 q_vector->adapter = adapter;
2062 q_vector->v_idx = q_idx;
2063 q_vector->eitr = adapter->eitr_param;
2064 if (q_idx < napi_vectors)
2065 netif_napi_add(adapter->netdev, &q_vector->napi,
2066 (*poll), 64);
2067 adapter->q_vector[q_idx] = q_vector;
2068 }
2069
2070 return 0;
2071
2072err_out:
2073 while (q_idx) {
2074 q_idx--;
2075 q_vector = adapter->q_vector[q_idx];
2076 netif_napi_del(&q_vector->napi);
2077 kfree(q_vector);
2078 adapter->q_vector[q_idx] = NULL;
2079 }
2080 return -ENOMEM;
2081}
2082
2083/**
2084 * ixgbevf_free_q_vectors - Free memory allocated for interrupt vectors
2085 * @adapter: board private structure to initialize
2086 *
2087 * This function frees the memory allocated to the q_vectors. In addition if
2088 * NAPI is enabled it will delete any references to the NAPI struct prior
2089 * to freeing the q_vector.
2090 **/
2091static void ixgbevf_free_q_vectors(struct ixgbevf_adapter *adapter)
2092{
2093 int q_idx, num_q_vectors;
2094 int napi_vectors;
2095
2096 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2097 napi_vectors = adapter->num_rx_queues;
2098
2099 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
2100 struct ixgbevf_q_vector *q_vector = adapter->q_vector[q_idx];
2101
2102 adapter->q_vector[q_idx] = NULL;
2103 if (q_idx < napi_vectors)
2104 netif_napi_del(&q_vector->napi);
2105 kfree(q_vector);
2106 }
2107}
2108
2109/**
2110 * ixgbevf_reset_interrupt_capability - Reset MSIX setup
2111 * @adapter: board private structure
2112 *
2113 **/
2114static void ixgbevf_reset_interrupt_capability(struct ixgbevf_adapter *adapter)
2115{
2116 pci_disable_msix(adapter->pdev);
2117 kfree(adapter->msix_entries);
2118 adapter->msix_entries = NULL;
2119
2120 return;
2121}
2122
2123/**
2124 * ixgbevf_init_interrupt_scheme - Determine if MSIX is supported and init
2125 * @adapter: board private structure to initialize
2126 *
2127 **/
2128static int ixgbevf_init_interrupt_scheme(struct ixgbevf_adapter *adapter)
2129{
2130 int err;
2131
2132 /* Number of supported queues */
2133 ixgbevf_set_num_queues(adapter);
2134
2135 err = ixgbevf_set_interrupt_capability(adapter);
2136 if (err) {
2137 hw_dbg(&adapter->hw,
2138 "Unable to setup interrupt capabilities\n");
2139 goto err_set_interrupt;
2140 }
2141
2142 err = ixgbevf_alloc_q_vectors(adapter);
2143 if (err) {
2144 hw_dbg(&adapter->hw, "Unable to allocate memory for queue "
2145 "vectors\n");
2146 goto err_alloc_q_vectors;
2147 }
2148
2149 err = ixgbevf_alloc_queues(adapter);
2150 if (err) {
2151 printk(KERN_ERR "Unable to allocate memory for queues\n");
2152 goto err_alloc_queues;
2153 }
2154
2155 hw_dbg(&adapter->hw, "Multiqueue %s: Rx Queue count = %u, "
2156 "Tx Queue count = %u\n",
2157 (adapter->num_rx_queues > 1) ? "Enabled" :
2158 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2159
2160 set_bit(__IXGBEVF_DOWN, &adapter->state);
2161
2162 return 0;
2163err_alloc_queues:
2164 ixgbevf_free_q_vectors(adapter);
2165err_alloc_q_vectors:
2166 ixgbevf_reset_interrupt_capability(adapter);
2167err_set_interrupt:
2168 return err;
2169}
2170
2171/**
2172 * ixgbevf_sw_init - Initialize general software structures
2173 * (struct ixgbevf_adapter)
2174 * @adapter: board private structure to initialize
2175 *
2176 * ixgbevf_sw_init initializes the Adapter private data structure.
2177 * Fields are initialized based on PCI device information and
2178 * OS network device settings (MTU size).
2179 **/
2180static int __devinit ixgbevf_sw_init(struct ixgbevf_adapter *adapter)
2181{
2182 struct ixgbe_hw *hw = &adapter->hw;
2183 struct pci_dev *pdev = adapter->pdev;
2184 int err;
2185
2186 /* PCI config space info */
2187
2188 hw->vendor_id = pdev->vendor;
2189 hw->device_id = pdev->device;
2190 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
2191 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2192 hw->subsystem_device_id = pdev->subsystem_device;
2193
2194 hw->mbx.ops.init_params(hw);
2195 hw->mac.max_tx_queues = MAX_TX_QUEUES;
2196 hw->mac.max_rx_queues = MAX_RX_QUEUES;
2197 err = hw->mac.ops.reset_hw(hw);
2198 if (err) {
2199 dev_info(&pdev->dev,
2200 "PF still in reset state, assigning new address\n");
2201 random_ether_addr(hw->mac.addr);
2202 } else {
2203 err = hw->mac.ops.init_hw(hw);
2204 if (err) {
2205 printk(KERN_ERR "init_shared_code failed: %d\n", err);
2206 goto out;
2207 }
2208 }
2209
2210 /* Enable dynamic interrupt throttling rates */
2211 adapter->eitr_param = 20000;
2212 adapter->itr_setting = 1;
2213
2214 /* set defaults for eitr in MegaBytes */
2215 adapter->eitr_low = 10;
2216 adapter->eitr_high = 20;
2217
2218 /* set default ring sizes */
2219 adapter->tx_ring_count = IXGBEVF_DEFAULT_TXD;
2220 adapter->rx_ring_count = IXGBEVF_DEFAULT_RXD;
2221
2222 /* enable rx csum by default */
2223 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2224
2225 set_bit(__IXGBEVF_DOWN, &adapter->state);
2226
2227out:
2228 return err;
2229}
2230
2231static void ixgbevf_init_last_counter_stats(struct ixgbevf_adapter *adapter)
2232{
2233 struct ixgbe_hw *hw = &adapter->hw;
2234
2235 adapter->stats.last_vfgprc = IXGBE_READ_REG(hw, IXGBE_VFGPRC);
2236 adapter->stats.last_vfgorc = IXGBE_READ_REG(hw, IXGBE_VFGORC_LSB);
2237 adapter->stats.last_vfgorc |=
2238 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGORC_MSB))) << 32);
2239 adapter->stats.last_vfgptc = IXGBE_READ_REG(hw, IXGBE_VFGPTC);
2240 adapter->stats.last_vfgotc = IXGBE_READ_REG(hw, IXGBE_VFGOTC_LSB);
2241 adapter->stats.last_vfgotc |=
2242 (((u64)(IXGBE_READ_REG(hw, IXGBE_VFGOTC_MSB))) << 32);
2243 adapter->stats.last_vfmprc = IXGBE_READ_REG(hw, IXGBE_VFMPRC);
2244
2245 adapter->stats.base_vfgprc = adapter->stats.last_vfgprc;
2246 adapter->stats.base_vfgorc = adapter->stats.last_vfgorc;
2247 adapter->stats.base_vfgptc = adapter->stats.last_vfgptc;
2248 adapter->stats.base_vfgotc = adapter->stats.last_vfgotc;
2249 adapter->stats.base_vfmprc = adapter->stats.last_vfmprc;
2250}
2251
2252#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter) \
2253 { \
2254 u32 current_counter = IXGBE_READ_REG(hw, reg); \
2255 if (current_counter < last_counter) \
2256 counter += 0x100000000LL; \
2257 last_counter = current_counter; \
2258 counter &= 0xFFFFFFFF00000000LL; \
2259 counter |= current_counter; \
2260 }
2261
2262#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2263 { \
2264 u64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb); \
2265 u64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb); \
2266 u64 current_counter = (current_counter_msb << 32) | \
2267 current_counter_lsb; \
2268 if (current_counter < last_counter) \
2269 counter += 0x1000000000LL; \
2270 last_counter = current_counter; \
2271 counter &= 0xFFFFFFF000000000LL; \
2272 counter |= current_counter; \
2273 }
2274/**
2275 * ixgbevf_update_stats - Update the board statistics counters.
2276 * @adapter: board private structure
2277 **/
2278void ixgbevf_update_stats(struct ixgbevf_adapter *adapter)
2279{
2280 struct ixgbe_hw *hw = &adapter->hw;
2281
2282 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPRC, adapter->stats.last_vfgprc,
2283 adapter->stats.vfgprc);
2284 UPDATE_VF_COUNTER_32bit(IXGBE_VFGPTC, adapter->stats.last_vfgptc,
2285 adapter->stats.vfgptc);
2286 UPDATE_VF_COUNTER_36bit(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2287 adapter->stats.last_vfgorc,
2288 adapter->stats.vfgorc);
2289 UPDATE_VF_COUNTER_36bit(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2290 adapter->stats.last_vfgotc,
2291 adapter->stats.vfgotc);
2292 UPDATE_VF_COUNTER_32bit(IXGBE_VFMPRC, adapter->stats.last_vfmprc,
2293 adapter->stats.vfmprc);
2294
2295 /* Fill out the OS statistics structure */
2296 adapter->net_stats.multicast = adapter->stats.vfmprc -
2297 adapter->stats.base_vfmprc;
2298}
2299
2300/**
2301 * ixgbevf_watchdog - Timer Call-back
2302 * @data: pointer to adapter cast into an unsigned long
2303 **/
2304static void ixgbevf_watchdog(unsigned long data)
2305{
2306 struct ixgbevf_adapter *adapter = (struct ixgbevf_adapter *)data;
2307 struct ixgbe_hw *hw = &adapter->hw;
2308 u64 eics = 0;
2309 int i;
2310
2311 /*
2312 * Do the watchdog outside of interrupt context due to the lovely
2313 * delays that some of the newer hardware requires
2314 */
2315
2316 if (test_bit(__IXGBEVF_DOWN, &adapter->state))
2317 goto watchdog_short_circuit;
2318
2319 /* get one bit for every active tx/rx interrupt vector */
2320 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
2321 struct ixgbevf_q_vector *qv = adapter->q_vector[i];
2322 if (qv->rxr_count || qv->txr_count)
2323 eics |= (1 << i);
2324 }
2325
2326 IXGBE_WRITE_REG(hw, IXGBE_VTEICS, (u32)eics);
2327
2328watchdog_short_circuit:
2329 schedule_work(&adapter->watchdog_task);
2330}
2331
2332/**
2333 * ixgbevf_tx_timeout - Respond to a Tx Hang
2334 * @netdev: network interface device structure
2335 **/
2336static void ixgbevf_tx_timeout(struct net_device *netdev)
2337{
2338 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2339
2340 /* Do the reset outside of interrupt context */
2341 schedule_work(&adapter->reset_task);
2342}
2343
2344static void ixgbevf_reset_task(struct work_struct *work)
2345{
2346 struct ixgbevf_adapter *adapter;
2347 adapter = container_of(work, struct ixgbevf_adapter, reset_task);
2348
2349 /* If we're already down or resetting, just bail */
2350 if (test_bit(__IXGBEVF_DOWN, &adapter->state) ||
2351 test_bit(__IXGBEVF_RESETTING, &adapter->state))
2352 return;
2353
2354 adapter->tx_timeout_count++;
2355
2356 ixgbevf_reinit_locked(adapter);
2357}
2358
2359/**
2360 * ixgbevf_watchdog_task - worker thread to bring link up
2361 * @work: pointer to work_struct containing our data
2362 **/
2363static void ixgbevf_watchdog_task(struct work_struct *work)
2364{
2365 struct ixgbevf_adapter *adapter = container_of(work,
2366 struct ixgbevf_adapter,
2367 watchdog_task);
2368 struct net_device *netdev = adapter->netdev;
2369 struct ixgbe_hw *hw = &adapter->hw;
2370 u32 link_speed = adapter->link_speed;
2371 bool link_up = adapter->link_up;
2372
2373 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
2374
2375 /*
2376 * Always check the link on the watchdog because we have
2377 * no LSC interrupt
2378 */
2379 if (hw->mac.ops.check_link) {
2380 if ((hw->mac.ops.check_link(hw, &link_speed,
2381 &link_up, false)) != 0) {
2382 adapter->link_up = link_up;
2383 adapter->link_speed = link_speed;
2384 netif_carrier_off(netdev);
2385 netif_tx_stop_all_queues(netdev);
2386 schedule_work(&adapter->reset_task);
2387 goto pf_has_reset;
2388 }
2389 } else {
2390 /* always assume link is up, if no check link
2391 * function */
2392 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
2393 link_up = true;
2394 }
2395 adapter->link_up = link_up;
2396 adapter->link_speed = link_speed;
2397
2398 if (link_up) {
2399 if (!netif_carrier_ok(netdev)) {
2400 hw_dbg(&adapter->hw, "NIC Link is Up %s, ",
2401 ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
2402 "10 Gbps" : "1 Gbps"));
2403 netif_carrier_on(netdev);
2404 netif_tx_wake_all_queues(netdev);
2405 } else {
2406 /* Force detection of hung controller */
2407 adapter->detect_tx_hung = true;
2408 }
2409 } else {
2410 adapter->link_up = false;
2411 adapter->link_speed = 0;
2412 if (netif_carrier_ok(netdev)) {
2413 hw_dbg(&adapter->hw, "NIC Link is Down\n");
2414 netif_carrier_off(netdev);
2415 netif_tx_stop_all_queues(netdev);
2416 }
2417 }
2418
2419pf_has_reset:
2420 ixgbevf_update_stats(adapter);
2421
2422 /* Force detection of hung controller every watchdog period */
2423 adapter->detect_tx_hung = true;
2424
2425 /* Reset the timer */
2426 if (!test_bit(__IXGBEVF_DOWN, &adapter->state))
2427 mod_timer(&adapter->watchdog_timer,
2428 round_jiffies(jiffies + (2 * HZ)));
2429
2430 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
2431}
2432
2433/**
2434 * ixgbevf_free_tx_resources - Free Tx Resources per Queue
2435 * @adapter: board private structure
2436 * @tx_ring: Tx descriptor ring for a specific queue
2437 *
2438 * Free all transmit software resources
2439 **/
2440void ixgbevf_free_tx_resources(struct ixgbevf_adapter *adapter,
2441 struct ixgbevf_ring *tx_ring)
2442{
2443 struct pci_dev *pdev = adapter->pdev;
2444
2445 ixgbevf_clean_tx_ring(adapter, tx_ring);
2446
2447 vfree(tx_ring->tx_buffer_info);
2448 tx_ring->tx_buffer_info = NULL;
2449
2450 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2451
2452 tx_ring->desc = NULL;
2453}
2454
2455/**
2456 * ixgbevf_free_all_tx_resources - Free Tx Resources for All Queues
2457 * @adapter: board private structure
2458 *
2459 * Free all transmit software resources
2460 **/
2461static void ixgbevf_free_all_tx_resources(struct ixgbevf_adapter *adapter)
2462{
2463 int i;
2464
2465 for (i = 0; i < adapter->num_tx_queues; i++)
2466 if (adapter->tx_ring[i].desc)
2467 ixgbevf_free_tx_resources(adapter,
2468 &adapter->tx_ring[i]);
2469
2470}
2471
2472/**
2473 * ixgbevf_setup_tx_resources - allocate Tx resources (Descriptors)
2474 * @adapter: board private structure
2475 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2476 *
2477 * Return 0 on success, negative on failure
2478 **/
2479int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *adapter,
2480 struct ixgbevf_ring *tx_ring)
2481{
2482 struct pci_dev *pdev = adapter->pdev;
2483 int size;
2484
2485 size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
2486 tx_ring->tx_buffer_info = vmalloc(size);
2487 if (!tx_ring->tx_buffer_info)
2488 goto err;
2489 memset(tx_ring->tx_buffer_info, 0, size);
2490
2491 /* round up to nearest 4K */
2492 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
2493 tx_ring->size = ALIGN(tx_ring->size, 4096);
2494
2495 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2496 &tx_ring->dma);
2497 if (!tx_ring->desc)
2498 goto err;
2499
2500 tx_ring->next_to_use = 0;
2501 tx_ring->next_to_clean = 0;
2502 tx_ring->work_limit = tx_ring->count;
2503 return 0;
2504
2505err:
2506 vfree(tx_ring->tx_buffer_info);
2507 tx_ring->tx_buffer_info = NULL;
2508 hw_dbg(&adapter->hw, "Unable to allocate memory for the transmit "
2509 "descriptor ring\n");
2510 return -ENOMEM;
2511}
2512
2513/**
2514 * ixgbevf_setup_all_tx_resources - allocate all queues Tx resources
2515 * @adapter: board private structure
2516 *
2517 * If this function returns with an error, then it's possible one or
2518 * more of the rings is populated (while the rest are not). It is the
2519 * callers duty to clean those orphaned rings.
2520 *
2521 * Return 0 on success, negative on failure
2522 **/
2523static int ixgbevf_setup_all_tx_resources(struct ixgbevf_adapter *adapter)
2524{
2525 int i, err = 0;
2526
2527 for (i = 0; i < adapter->num_tx_queues; i++) {
2528 err = ixgbevf_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2529 if (!err)
2530 continue;
2531 hw_dbg(&adapter->hw,
2532 "Allocation for Tx Queue %u failed\n", i);
2533 break;
2534 }
2535
2536 return err;
2537}
2538
2539/**
2540 * ixgbevf_setup_rx_resources - allocate Rx resources (Descriptors)
2541 * @adapter: board private structure
2542 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2543 *
2544 * Returns 0 on success, negative on failure
2545 **/
2546int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter,
2547 struct ixgbevf_ring *rx_ring)
2548{
2549 struct pci_dev *pdev = adapter->pdev;
2550 int size;
2551
2552 size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
2553 rx_ring->rx_buffer_info = vmalloc(size);
2554 if (!rx_ring->rx_buffer_info) {
2555 hw_dbg(&adapter->hw,
2556 "Unable to vmalloc buffer memory for "
2557 "the receive descriptor ring\n");
2558 goto alloc_failed;
2559 }
2560 memset(rx_ring->rx_buffer_info, 0, size);
2561
2562 /* Round up to nearest 4K */
2563 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2564 rx_ring->size = ALIGN(rx_ring->size, 4096);
2565
2566 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2567 &rx_ring->dma);
2568
2569 if (!rx_ring->desc) {
2570 hw_dbg(&adapter->hw,
2571 "Unable to allocate memory for "
2572 "the receive descriptor ring\n");
2573 vfree(rx_ring->rx_buffer_info);
2574 rx_ring->rx_buffer_info = NULL;
2575 goto alloc_failed;
2576 }
2577
2578 rx_ring->next_to_clean = 0;
2579 rx_ring->next_to_use = 0;
2580
2581 return 0;
2582alloc_failed:
2583 return -ENOMEM;
2584}
2585
2586/**
2587 * ixgbevf_setup_all_rx_resources - allocate all queues Rx resources
2588 * @adapter: board private structure
2589 *
2590 * If this function returns with an error, then it's possible one or
2591 * more of the rings is populated (while the rest are not). It is the
2592 * callers duty to clean those orphaned rings.
2593 *
2594 * Return 0 on success, negative on failure
2595 **/
2596static int ixgbevf_setup_all_rx_resources(struct ixgbevf_adapter *adapter)
2597{
2598 int i, err = 0;
2599
2600 for (i = 0; i < adapter->num_rx_queues; i++) {
2601 err = ixgbevf_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2602 if (!err)
2603 continue;
2604 hw_dbg(&adapter->hw,
2605 "Allocation for Rx Queue %u failed\n", i);
2606 break;
2607 }
2608 return err;
2609}
2610
2611/**
2612 * ixgbevf_free_rx_resources - Free Rx Resources
2613 * @adapter: board private structure
2614 * @rx_ring: ring to clean the resources from
2615 *
2616 * Free all receive software resources
2617 **/
2618void ixgbevf_free_rx_resources(struct ixgbevf_adapter *adapter,
2619 struct ixgbevf_ring *rx_ring)
2620{
2621 struct pci_dev *pdev = adapter->pdev;
2622
2623 ixgbevf_clean_rx_ring(adapter, rx_ring);
2624
2625 vfree(rx_ring->rx_buffer_info);
2626 rx_ring->rx_buffer_info = NULL;
2627
2628 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2629
2630 rx_ring->desc = NULL;
2631}
2632
2633/**
2634 * ixgbevf_free_all_rx_resources - Free Rx Resources for All Queues
2635 * @adapter: board private structure
2636 *
2637 * Free all receive software resources
2638 **/
2639static void ixgbevf_free_all_rx_resources(struct ixgbevf_adapter *adapter)
2640{
2641 int i;
2642
2643 for (i = 0; i < adapter->num_rx_queues; i++)
2644 if (adapter->rx_ring[i].desc)
2645 ixgbevf_free_rx_resources(adapter,
2646 &adapter->rx_ring[i]);
2647}
2648
2649/**
2650 * ixgbevf_open - Called when a network interface is made active
2651 * @netdev: network interface device structure
2652 *
2653 * Returns 0 on success, negative value on failure
2654 *
2655 * The open entry point is called when a network interface is made
2656 * active by the system (IFF_UP). At this point all resources needed
2657 * for transmit and receive operations are allocated, the interrupt
2658 * handler is registered with the OS, the watchdog timer is started,
2659 * and the stack is notified that the interface is ready.
2660 **/
2661static int ixgbevf_open(struct net_device *netdev)
2662{
2663 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2664 struct ixgbe_hw *hw = &adapter->hw;
2665 int err;
2666
2667 /* disallow open during test */
2668 if (test_bit(__IXGBEVF_TESTING, &adapter->state))
2669 return -EBUSY;
2670
2671 if (hw->adapter_stopped) {
2672 ixgbevf_reset(adapter);
2673 /* if adapter is still stopped then PF isn't up and
2674 * the vf can't start. */
2675 if (hw->adapter_stopped) {
2676 err = IXGBE_ERR_MBX;
2677 printk(KERN_ERR "Unable to start - perhaps the PF"
2678 "Driver isn't up yet\n");
2679 goto err_setup_reset;
2680 }
2681 }
2682
2683 /* allocate transmit descriptors */
2684 err = ixgbevf_setup_all_tx_resources(adapter);
2685 if (err)
2686 goto err_setup_tx;
2687
2688 /* allocate receive descriptors */
2689 err = ixgbevf_setup_all_rx_resources(adapter);
2690 if (err)
2691 goto err_setup_rx;
2692
2693 ixgbevf_configure(adapter);
2694
2695 /*
2696 * Map the Tx/Rx rings to the vectors we were allotted.
2697 * if request_irq will be called in this function map_rings
2698 * must be called *before* up_complete
2699 */
2700 ixgbevf_map_rings_to_vectors(adapter);
2701
2702 err = ixgbevf_up_complete(adapter);
2703 if (err)
2704 goto err_up;
2705
2706 /* clear any pending interrupts, may auto mask */
2707 IXGBE_READ_REG(hw, IXGBE_VTEICR);
2708 err = ixgbevf_request_irq(adapter);
2709 if (err)
2710 goto err_req_irq;
2711
2712 ixgbevf_irq_enable(adapter, true, true);
2713
2714 return 0;
2715
2716err_req_irq:
2717 ixgbevf_down(adapter);
2718err_up:
2719 ixgbevf_free_irq(adapter);
2720err_setup_rx:
2721 ixgbevf_free_all_rx_resources(adapter);
2722err_setup_tx:
2723 ixgbevf_free_all_tx_resources(adapter);
2724 ixgbevf_reset(adapter);
2725
2726err_setup_reset:
2727
2728 return err;
2729}
2730
2731/**
2732 * ixgbevf_close - Disables a network interface
2733 * @netdev: network interface device structure
2734 *
2735 * Returns 0, this is not allowed to fail
2736 *
2737 * The close entry point is called when an interface is de-activated
2738 * by the OS. The hardware is still under the drivers control, but
2739 * needs to be disabled. A global MAC reset is issued to stop the
2740 * hardware, and all transmit and receive resources are freed.
2741 **/
2742static int ixgbevf_close(struct net_device *netdev)
2743{
2744 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
2745
2746 ixgbevf_down(adapter);
2747 ixgbevf_free_irq(adapter);
2748
2749 ixgbevf_free_all_tx_resources(adapter);
2750 ixgbevf_free_all_rx_resources(adapter);
2751
2752 return 0;
2753}
2754
2755static int ixgbevf_tso(struct ixgbevf_adapter *adapter,
2756 struct ixgbevf_ring *tx_ring,
2757 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2758{
2759 struct ixgbe_adv_tx_context_desc *context_desc;
2760 unsigned int i;
2761 int err;
2762 struct ixgbevf_tx_buffer *tx_buffer_info;
2763 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
2764 u32 mss_l4len_idx, l4len;
2765
2766 if (skb_is_gso(skb)) {
2767 if (skb_header_cloned(skb)) {
2768 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2769 if (err)
2770 return err;
2771 }
2772 l4len = tcp_hdrlen(skb);
2773 *hdr_len += l4len;
2774
2775 if (skb->protocol == htons(ETH_P_IP)) {
2776 struct iphdr *iph = ip_hdr(skb);
2777 iph->tot_len = 0;
2778 iph->check = 0;
2779 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2780 iph->daddr, 0,
2781 IPPROTO_TCP,
2782 0);
2783 adapter->hw_tso_ctxt++;
2784 } else if (skb_is_gso_v6(skb)) {
2785 ipv6_hdr(skb)->payload_len = 0;
2786 tcp_hdr(skb)->check =
2787 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2788 &ipv6_hdr(skb)->daddr,
2789 0, IPPROTO_TCP, 0);
2790 adapter->hw_tso6_ctxt++;
2791 }
2792
2793 i = tx_ring->next_to_use;
2794
2795 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2796 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2797
2798 /* VLAN MACLEN IPLEN */
2799 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2800 vlan_macip_lens |=
2801 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
2802 vlan_macip_lens |= ((skb_network_offset(skb)) <<
2803 IXGBE_ADVTXD_MACLEN_SHIFT);
2804 *hdr_len += skb_network_offset(skb);
2805 vlan_macip_lens |=
2806 (skb_transport_header(skb) - skb_network_header(skb));
2807 *hdr_len +=
2808 (skb_transport_header(skb) - skb_network_header(skb));
2809 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2810 context_desc->seqnum_seed = 0;
2811
2812 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2813 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
2814 IXGBE_ADVTXD_DTYP_CTXT);
2815
2816 if (skb->protocol == htons(ETH_P_IP))
2817 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2818 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
2819 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2820
2821 /* MSS L4LEN IDX */
2822 mss_l4len_idx =
2823 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
2824 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
2825 /* use index 1 for TSO */
2826 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
2827 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2828
2829 tx_buffer_info->time_stamp = jiffies;
2830 tx_buffer_info->next_to_watch = i;
2831
2832 i++;
2833 if (i == tx_ring->count)
2834 i = 0;
2835 tx_ring->next_to_use = i;
2836
2837 return true;
2838 }
2839
2840 return false;
2841}
2842
2843static bool ixgbevf_tx_csum(struct ixgbevf_adapter *adapter,
2844 struct ixgbevf_ring *tx_ring,
2845 struct sk_buff *skb, u32 tx_flags)
2846{
2847 struct ixgbe_adv_tx_context_desc *context_desc;
2848 unsigned int i;
2849 struct ixgbevf_tx_buffer *tx_buffer_info;
2850 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2851
2852 if (skb->ip_summed == CHECKSUM_PARTIAL ||
2853 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
2854 i = tx_ring->next_to_use;
2855 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2856 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2857
2858 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2859 vlan_macip_lens |= (tx_flags &
2860 IXGBE_TX_FLAGS_VLAN_MASK);
2861 vlan_macip_lens |= (skb_network_offset(skb) <<
2862 IXGBE_ADVTXD_MACLEN_SHIFT);
2863 if (skb->ip_summed == CHECKSUM_PARTIAL)
2864 vlan_macip_lens |= (skb_transport_header(skb) -
2865 skb_network_header(skb));
2866
2867 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2868 context_desc->seqnum_seed = 0;
2869
2870 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
2871 IXGBE_ADVTXD_DTYP_CTXT);
2872
2873 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2874 switch (skb->protocol) {
2875 case __constant_htons(ETH_P_IP):
2876 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2877 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2878 type_tucmd_mlhl |=
2879 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2880 break;
2881 case __constant_htons(ETH_P_IPV6):
2882 /* XXX what about other V6 headers?? */
2883 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2884 type_tucmd_mlhl |=
2885 IXGBE_ADVTXD_TUCMD_L4T_TCP;
2886 break;
2887 default:
2888 if (unlikely(net_ratelimit())) {
2889 printk(KERN_WARNING
2890 "partial checksum but "
2891 "proto=%x!\n",
2892 skb->protocol);
2893 }
2894 break;
2895 }
2896 }
2897
2898 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2899 /* use index zero for tx checksum offload */
2900 context_desc->mss_l4len_idx = 0;
2901
2902 tx_buffer_info->time_stamp = jiffies;
2903 tx_buffer_info->next_to_watch = i;
2904
2905 adapter->hw_csum_tx_good++;
2906 i++;
2907 if (i == tx_ring->count)
2908 i = 0;
2909 tx_ring->next_to_use = i;
2910
2911 return true;
2912 }
2913
2914 return false;
2915}
2916
2917static int ixgbevf_tx_map(struct ixgbevf_adapter *adapter,
2918 struct ixgbevf_ring *tx_ring,
2919 struct sk_buff *skb, u32 tx_flags,
2920 unsigned int first)
2921{
2922 struct pci_dev *pdev = adapter->pdev;
2923 struct ixgbevf_tx_buffer *tx_buffer_info;
2924 unsigned int len;
2925 unsigned int total = skb->len;
2926 unsigned int offset = 0, size, count = 0, i;
2927 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2928 unsigned int f;
2929
2930 i = tx_ring->next_to_use;
2931
2932 len = min(skb_headlen(skb), total);
2933 while (len) {
2934 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2935 size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD);
2936
2937 tx_buffer_info->length = size;
2938 tx_buffer_info->mapped_as_page = false;
2939 tx_buffer_info->dma = pci_map_single(adapter->pdev,
2940 skb->data + offset,
2941 size, PCI_DMA_TODEVICE);
2942 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
2943 goto dma_error;
2944 tx_buffer_info->time_stamp = jiffies;
2945 tx_buffer_info->next_to_watch = i;
2946
2947 len -= size;
2948 total -= size;
2949 offset += size;
2950 count++;
2951 i++;
2952 if (i == tx_ring->count)
2953 i = 0;
2954 }
2955
2956 for (f = 0; f < nr_frags; f++) {
2957 struct skb_frag_struct *frag;
2958
2959 frag = &skb_shinfo(skb)->frags[f];
2960 len = min((unsigned int)frag->size, total);
2961 offset = frag->page_offset;
2962
2963 while (len) {
2964 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2965 size = min(len, (unsigned int)IXGBE_MAX_DATA_PER_TXD);
2966
2967 tx_buffer_info->length = size;
2968 tx_buffer_info->dma = pci_map_page(adapter->pdev,
2969 frag->page,
2970 offset,
2971 size,
2972 PCI_DMA_TODEVICE);
2973 tx_buffer_info->mapped_as_page = true;
2974 if (pci_dma_mapping_error(pdev, tx_buffer_info->dma))
2975 goto dma_error;
2976 tx_buffer_info->time_stamp = jiffies;
2977 tx_buffer_info->next_to_watch = i;
2978
2979 len -= size;
2980 total -= size;
2981 offset += size;
2982 count++;
2983 i++;
2984 if (i == tx_ring->count)
2985 i = 0;
2986 }
2987 if (total == 0)
2988 break;
2989 }
2990
2991 if (i == 0)
2992 i = tx_ring->count - 1;
2993 else
2994 i = i - 1;
2995 tx_ring->tx_buffer_info[i].skb = skb;
2996 tx_ring->tx_buffer_info[first].next_to_watch = i;
2997
2998 return count;
2999
3000dma_error:
3001 dev_err(&pdev->dev, "TX DMA map failed\n");
3002
3003 /* clear timestamp and dma mappings for failed tx_buffer_info map */
3004 tx_buffer_info->dma = 0;
3005 tx_buffer_info->time_stamp = 0;
3006 tx_buffer_info->next_to_watch = 0;
3007 count--;
3008
3009 /* clear timestamp and dma mappings for remaining portion of packet */
3010 while (count >= 0) {
3011 count--;
3012 i--;
3013 if (i < 0)
3014 i += tx_ring->count;
3015 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3016 ixgbevf_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3017 }
3018
3019 return count;
3020}
3021
3022static void ixgbevf_tx_queue(struct ixgbevf_adapter *adapter,
3023 struct ixgbevf_ring *tx_ring, int tx_flags,
3024 int count, u32 paylen, u8 hdr_len)
3025{
3026 union ixgbe_adv_tx_desc *tx_desc = NULL;
3027 struct ixgbevf_tx_buffer *tx_buffer_info;
3028 u32 olinfo_status = 0, cmd_type_len = 0;
3029 unsigned int i;
3030
3031 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3032
3033 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3034
3035 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3036
3037 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3038 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3039
3040 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3041 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3042
3043 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3044 IXGBE_ADVTXD_POPTS_SHIFT;
3045
3046 /* use index 1 context for tso */
3047 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3048 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3049 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3050 IXGBE_ADVTXD_POPTS_SHIFT;
3051
3052 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3053 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3054 IXGBE_ADVTXD_POPTS_SHIFT;
3055
3056 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3057
3058 i = tx_ring->next_to_use;
3059 while (count--) {
3060 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3061 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3062 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3063 tx_desc->read.cmd_type_len =
3064 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3065 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3066 i++;
3067 if (i == tx_ring->count)
3068 i = 0;
3069 }
3070
3071 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3072
3073 /*
3074 * Force memory writes to complete before letting h/w
3075 * know there are new descriptors to fetch. (Only
3076 * applicable for weak-ordered memory model archs,
3077 * such as IA-64).
3078 */
3079 wmb();
3080
3081 tx_ring->next_to_use = i;
3082 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3083}
3084
3085static int __ixgbevf_maybe_stop_tx(struct net_device *netdev,
3086 struct ixgbevf_ring *tx_ring, int size)
3087{
3088 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3089
3090 netif_stop_subqueue(netdev, tx_ring->queue_index);
3091 /* Herbert's original patch had:
3092 * smp_mb__after_netif_stop_queue();
3093 * but since that doesn't exist yet, just open code it. */
3094 smp_mb();
3095
3096 /* We need to check again in a case another CPU has just
3097 * made room available. */
3098 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3099 return -EBUSY;
3100
3101 /* A reprieve! - use start_queue because it doesn't call schedule */
3102 netif_start_subqueue(netdev, tx_ring->queue_index);
3103 ++adapter->restart_queue;
3104 return 0;
3105}
3106
3107static int ixgbevf_maybe_stop_tx(struct net_device *netdev,
3108 struct ixgbevf_ring *tx_ring, int size)
3109{
3110 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3111 return 0;
3112 return __ixgbevf_maybe_stop_tx(netdev, tx_ring, size);
3113}
3114
3115static int ixgbevf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3116{
3117 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3118 struct ixgbevf_ring *tx_ring;
3119 unsigned int first;
3120 unsigned int tx_flags = 0;
3121 u8 hdr_len = 0;
3122 int r_idx = 0, tso;
3123 int count = 0;
3124
3125 unsigned int f;
3126
3127 tx_ring = &adapter->tx_ring[r_idx];
3128
3129 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3130 tx_flags |= vlan_tx_tag_get(skb);
3131 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3132 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3133 }
3134
3135 /* four things can cause us to need a context descriptor */
3136 if (skb_is_gso(skb) ||
3137 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3138 (tx_flags & IXGBE_TX_FLAGS_VLAN))
3139 count++;
3140
3141 count += TXD_USE_COUNT(skb_headlen(skb));
3142 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
3143 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3144
3145 if (ixgbevf_maybe_stop_tx(netdev, tx_ring, count)) {
3146 adapter->tx_busy++;
3147 return NETDEV_TX_BUSY;
3148 }
3149
3150 first = tx_ring->next_to_use;
3151
3152 if (skb->protocol == htons(ETH_P_IP))
3153 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3154 tso = ixgbevf_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3155 if (tso < 0) {
3156 dev_kfree_skb_any(skb);
3157 return NETDEV_TX_OK;
3158 }
3159
3160 if (tso)
3161 tx_flags |= IXGBE_TX_FLAGS_TSO;
3162 else if (ixgbevf_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3163 (skb->ip_summed == CHECKSUM_PARTIAL))
3164 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3165
3166 ixgbevf_tx_queue(adapter, tx_ring, tx_flags,
3167 ixgbevf_tx_map(adapter, tx_ring, skb, tx_flags, first),
3168 skb->len, hdr_len);
3169
3170 netdev->trans_start = jiffies;
3171
3172 ixgbevf_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
3173
3174 return NETDEV_TX_OK;
3175}
3176
3177/**
3178 * ixgbevf_get_stats - Get System Network Statistics
3179 * @netdev: network interface device structure
3180 *
3181 * Returns the address of the device statistics structure.
3182 * The statistics are actually updated from the timer callback.
3183 **/
3184static struct net_device_stats *ixgbevf_get_stats(struct net_device *netdev)
3185{
3186 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3187
3188 /* only return the current stats */
3189 return &adapter->net_stats;
3190}
3191
3192/**
3193 * ixgbevf_set_mac - Change the Ethernet Address of the NIC
3194 * @netdev: network interface device structure
3195 * @p: pointer to an address structure
3196 *
3197 * Returns 0 on success, negative on failure
3198 **/
3199static int ixgbevf_set_mac(struct net_device *netdev, void *p)
3200{
3201 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3202 struct ixgbe_hw *hw = &adapter->hw;
3203 struct sockaddr *addr = p;
3204
3205 if (!is_valid_ether_addr(addr->sa_data))
3206 return -EADDRNOTAVAIL;
3207
3208 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3209 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3210
3211 if (hw->mac.ops.set_rar)
3212 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0);
3213
3214 return 0;
3215}
3216
3217/**
3218 * ixgbevf_change_mtu - Change the Maximum Transfer Unit
3219 * @netdev: network interface device structure
3220 * @new_mtu: new value for maximum frame size
3221 *
3222 * Returns 0 on success, negative on failure
3223 **/
3224static int ixgbevf_change_mtu(struct net_device *netdev, int new_mtu)
3225{
3226 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3227 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3228
3229 /* MTU < 68 is an error and causes problems on some kernels */
3230 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
3231 return -EINVAL;
3232
3233 hw_dbg(&adapter->hw, "changing MTU from %d to %d\n",
3234 netdev->mtu, new_mtu);
3235 /* must set new MTU before calling down or up */
3236 netdev->mtu = new_mtu;
3237
3238 if (netif_running(netdev))
3239 ixgbevf_reinit_locked(adapter);
3240
3241 return 0;
3242}
3243
3244static void ixgbevf_shutdown(struct pci_dev *pdev)
3245{
3246 struct net_device *netdev = pci_get_drvdata(pdev);
3247 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3248
3249 netif_device_detach(netdev);
3250
3251 if (netif_running(netdev)) {
3252 ixgbevf_down(adapter);
3253 ixgbevf_free_irq(adapter);
3254 ixgbevf_free_all_tx_resources(adapter);
3255 ixgbevf_free_all_rx_resources(adapter);
3256 }
3257
3258#ifdef CONFIG_PM
3259 pci_save_state(pdev);
3260#endif
3261
3262 pci_disable_device(pdev);
3263}
3264
3265static const struct net_device_ops ixgbe_netdev_ops = {
3266 .ndo_open = &ixgbevf_open,
3267 .ndo_stop = &ixgbevf_close,
3268 .ndo_start_xmit = &ixgbevf_xmit_frame,
3269 .ndo_get_stats = &ixgbevf_get_stats,
3270 .ndo_set_rx_mode = &ixgbevf_set_rx_mode,
3271 .ndo_set_multicast_list = &ixgbevf_set_rx_mode,
3272 .ndo_validate_addr = eth_validate_addr,
3273 .ndo_set_mac_address = &ixgbevf_set_mac,
3274 .ndo_change_mtu = &ixgbevf_change_mtu,
3275 .ndo_tx_timeout = &ixgbevf_tx_timeout,
3276 .ndo_vlan_rx_register = &ixgbevf_vlan_rx_register,
3277 .ndo_vlan_rx_add_vid = &ixgbevf_vlan_rx_add_vid,
3278 .ndo_vlan_rx_kill_vid = &ixgbevf_vlan_rx_kill_vid,
3279};
3280
3281static void ixgbevf_assign_netdev_ops(struct net_device *dev)
3282{
3283 struct ixgbevf_adapter *adapter;
3284 adapter = netdev_priv(dev);
3285 dev->netdev_ops = &ixgbe_netdev_ops;
3286 ixgbevf_set_ethtool_ops(dev);
3287 dev->watchdog_timeo = 5 * HZ;
3288}
3289
3290/**
3291 * ixgbevf_probe - Device Initialization Routine
3292 * @pdev: PCI device information struct
3293 * @ent: entry in ixgbevf_pci_tbl
3294 *
3295 * Returns 0 on success, negative on failure
3296 *
3297 * ixgbevf_probe initializes an adapter identified by a pci_dev structure.
3298 * The OS initialization, configuring of the adapter private structure,
3299 * and a hardware reset occur.
3300 **/
3301static int __devinit ixgbevf_probe(struct pci_dev *pdev,
3302 const struct pci_device_id *ent)
3303{
3304 struct net_device *netdev;
3305 struct ixgbevf_adapter *adapter = NULL;
3306 struct ixgbe_hw *hw = NULL;
3307 const struct ixgbevf_info *ii = ixgbevf_info_tbl[ent->driver_data];
3308 static int cards_found;
3309 int err, pci_using_dac;
3310
3311 err = pci_enable_device(pdev);
3312 if (err)
3313 return err;
3314
3315 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
3316 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
3317 pci_using_dac = 1;
3318 } else {
3319 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3320 if (err) {
3321 err = pci_set_consistent_dma_mask(pdev,
3322 DMA_BIT_MASK(32));
3323 if (err) {
3324 dev_err(&pdev->dev, "No usable DMA "
3325 "configuration, aborting\n");
3326 goto err_dma;
3327 }
3328 }
3329 pci_using_dac = 0;
3330 }
3331
3332 err = pci_request_regions(pdev, ixgbevf_driver_name);
3333 if (err) {
3334 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3335 goto err_pci_reg;
3336 }
3337
3338 pci_set_master(pdev);
3339
3340#ifdef HAVE_TX_MQ
3341 netdev = alloc_etherdev_mq(sizeof(struct ixgbevf_adapter),
3342 MAX_TX_QUEUES);
3343#else
3344 netdev = alloc_etherdev(sizeof(struct ixgbevf_adapter));
3345#endif
3346 if (!netdev) {
3347 err = -ENOMEM;
3348 goto err_alloc_etherdev;
3349 }
3350
3351 SET_NETDEV_DEV(netdev, &pdev->dev);
3352
3353 pci_set_drvdata(pdev, netdev);
3354 adapter = netdev_priv(netdev);
3355
3356 adapter->netdev = netdev;
3357 adapter->pdev = pdev;
3358 hw = &adapter->hw;
3359 hw->back = adapter;
3360 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3361
3362 /*
3363 * call save state here in standalone driver because it relies on
3364 * adapter struct to exist, and needs to call netdev_priv
3365 */
3366 pci_save_state(pdev);
3367
3368 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3369 pci_resource_len(pdev, 0));
3370 if (!hw->hw_addr) {
3371 err = -EIO;
3372 goto err_ioremap;
3373 }
3374
3375 ixgbevf_assign_netdev_ops(netdev);
3376
3377 adapter->bd_number = cards_found;
3378
3379 /* Setup hw api */
3380 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
3381 hw->mac.type = ii->mac;
3382
3383 memcpy(&hw->mbx.ops, &ixgbevf_mbx_ops,
3384 sizeof(struct ixgbe_mac_operations));
3385
3386 adapter->flags &= ~IXGBE_FLAG_RX_PS_CAPABLE;
3387 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3388 adapter->flags |= IXGBE_FLAG_RX_1BUF_CAPABLE;
3389
3390 /* setup the private structure */
3391 err = ixgbevf_sw_init(adapter);
3392
3393 ixgbevf_init_last_counter_stats(adapter);
3394
3395#ifdef MAX_SKB_FRAGS
3396 netdev->features = NETIF_F_SG |
3397 NETIF_F_IP_CSUM |
3398 NETIF_F_HW_VLAN_TX |
3399 NETIF_F_HW_VLAN_RX |
3400 NETIF_F_HW_VLAN_FILTER;
3401
3402 netdev->features |= NETIF_F_IPV6_CSUM;
3403 netdev->features |= NETIF_F_TSO;
3404 netdev->features |= NETIF_F_TSO6;
3405 netdev->vlan_features |= NETIF_F_TSO;
3406 netdev->vlan_features |= NETIF_F_TSO6;
3407 netdev->vlan_features |= NETIF_F_IP_CSUM;
3408 netdev->vlan_features |= NETIF_F_SG;
3409
3410 if (pci_using_dac)
3411 netdev->features |= NETIF_F_HIGHDMA;
3412
3413#endif /* MAX_SKB_FRAGS */
3414
3415 /* The HW MAC address was set and/or determined in sw_init */
3416 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
3417 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
3418
3419 if (!is_valid_ether_addr(netdev->dev_addr)) {
3420 printk(KERN_ERR "invalid MAC address\n");
3421 err = -EIO;
3422 goto err_sw_init;
3423 }
3424
3425 init_timer(&adapter->watchdog_timer);
3426 adapter->watchdog_timer.function = &ixgbevf_watchdog;
3427 adapter->watchdog_timer.data = (unsigned long)adapter;
3428
3429 INIT_WORK(&adapter->reset_task, ixgbevf_reset_task);
3430 INIT_WORK(&adapter->watchdog_task, ixgbevf_watchdog_task);
3431
3432 err = ixgbevf_init_interrupt_scheme(adapter);
3433 if (err)
3434 goto err_sw_init;
3435
3436 /* pick up the PCI bus settings for reporting later */
3437 if (hw->mac.ops.get_bus_info)
3438 hw->mac.ops.get_bus_info(hw);
3439
3440
3441 netif_carrier_off(netdev);
3442 netif_tx_stop_all_queues(netdev);
3443
3444 strcpy(netdev->name, "eth%d");
3445
3446 err = register_netdev(netdev);
3447 if (err)
3448 goto err_register;
3449
3450 adapter->netdev_registered = true;
3451
3452 /* print the MAC address */
3453 hw_dbg(hw, "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
3454 netdev->dev_addr[0],
3455 netdev->dev_addr[1],
3456 netdev->dev_addr[2],
3457 netdev->dev_addr[3],
3458 netdev->dev_addr[4],
3459 netdev->dev_addr[5]);
3460
3461 hw_dbg(hw, "MAC: %d\n", hw->mac.type);
3462
3463 hw_dbg(hw, "LRO is disabled \n");
3464
3465 hw_dbg(hw, "Intel(R) 82599 Virtual Function\n");
3466 cards_found++;
3467 return 0;
3468
3469err_register:
3470err_sw_init:
3471 ixgbevf_reset_interrupt_capability(adapter);
3472 iounmap(hw->hw_addr);
3473err_ioremap:
3474 free_netdev(netdev);
3475err_alloc_etherdev:
3476 pci_release_regions(pdev);
3477err_pci_reg:
3478err_dma:
3479 pci_disable_device(pdev);
3480 return err;
3481}
3482
3483/**
3484 * ixgbevf_remove - Device Removal Routine
3485 * @pdev: PCI device information struct
3486 *
3487 * ixgbevf_remove is called by the PCI subsystem to alert the driver
3488 * that it should release a PCI device. The could be caused by a
3489 * Hot-Plug event, or because the driver is going to be removed from
3490 * memory.
3491 **/
3492static void __devexit ixgbevf_remove(struct pci_dev *pdev)
3493{
3494 struct net_device *netdev = pci_get_drvdata(pdev);
3495 struct ixgbevf_adapter *adapter = netdev_priv(netdev);
3496
3497 set_bit(__IXGBEVF_DOWN, &adapter->state);
3498
3499 del_timer_sync(&adapter->watchdog_timer);
3500
3501 cancel_work_sync(&adapter->watchdog_task);
3502
3503 flush_scheduled_work();
3504
3505 if (adapter->netdev_registered) {
3506 unregister_netdev(netdev);
3507 adapter->netdev_registered = false;
3508 }
3509
3510 ixgbevf_reset_interrupt_capability(adapter);
3511
3512 iounmap(adapter->hw.hw_addr);
3513 pci_release_regions(pdev);
3514
3515 hw_dbg(&adapter->hw, "Remove complete\n");
3516
3517 kfree(adapter->tx_ring);
3518 kfree(adapter->rx_ring);
3519
3520 free_netdev(netdev);
3521
3522 pci_disable_device(pdev);
3523}
3524
3525static struct pci_driver ixgbevf_driver = {
3526 .name = ixgbevf_driver_name,
3527 .id_table = ixgbevf_pci_tbl,
3528 .probe = ixgbevf_probe,
3529 .remove = __devexit_p(ixgbevf_remove),
3530 .shutdown = ixgbevf_shutdown,
3531};
3532
3533/**
3534 * ixgbe_init_module - Driver Registration Routine
3535 *
3536 * ixgbe_init_module is the first routine called when the driver is
3537 * loaded. All it does is register with the PCI subsystem.
3538 **/
3539static int __init ixgbevf_init_module(void)
3540{
3541 int ret;
3542 printk(KERN_INFO "ixgbevf: %s - version %s\n", ixgbevf_driver_string,
3543 ixgbevf_driver_version);
3544
3545 printk(KERN_INFO "%s\n", ixgbevf_copyright);
3546
3547 ret = pci_register_driver(&ixgbevf_driver);
3548 return ret;
3549}
3550
3551module_init(ixgbevf_init_module);
3552
3553/**
3554 * ixgbe_exit_module - Driver Exit Cleanup Routine
3555 *
3556 * ixgbe_exit_module is called just before the driver is removed
3557 * from memory.
3558 **/
3559static void __exit ixgbevf_exit_module(void)
3560{
3561 pci_unregister_driver(&ixgbevf_driver);
3562}
3563
3564#ifdef DEBUG
3565/**
3566 * ixgbe_get_hw_dev_name - return device name string
3567 * used by hardware layer to print debugging information
3568 **/
3569char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw)
3570{
3571 struct ixgbevf_adapter *adapter = hw->back;
3572 return adapter->netdev->name;
3573}
3574
3575#endif
3576module_exit(ixgbevf_exit_module);
3577
3578/* ixgbevf_main.c */
diff --git a/drivers/net/ixgbevf/mbx.c b/drivers/net/ixgbevf/mbx.c
new file mode 100644
index 000000000000..b8143501e6fc
--- /dev/null
+++ b/drivers/net/ixgbevf/mbx.c
@@ -0,0 +1,341 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include "mbx.h"
29
30/**
31 * ixgbevf_poll_for_msg - Wait for message notification
32 * @hw: pointer to the HW structure
33 *
34 * returns 0 if it successfully received a message notification
35 **/
36static s32 ixgbevf_poll_for_msg(struct ixgbe_hw *hw)
37{
38 struct ixgbe_mbx_info *mbx = &hw->mbx;
39 int countdown = mbx->timeout;
40
41 while (countdown && mbx->ops.check_for_msg(hw)) {
42 countdown--;
43 udelay(mbx->udelay);
44 }
45
46 /* if we failed, all future posted messages fail until reset */
47 if (!countdown)
48 mbx->timeout = 0;
49
50 return countdown ? 0 : IXGBE_ERR_MBX;
51}
52
53/**
54 * ixgbevf_poll_for_ack - Wait for message acknowledgement
55 * @hw: pointer to the HW structure
56 *
57 * returns 0 if it successfully received a message acknowledgement
58 **/
59static s32 ixgbevf_poll_for_ack(struct ixgbe_hw *hw)
60{
61 struct ixgbe_mbx_info *mbx = &hw->mbx;
62 int countdown = mbx->timeout;
63
64 while (countdown && mbx->ops.check_for_ack(hw)) {
65 countdown--;
66 udelay(mbx->udelay);
67 }
68
69 /* if we failed, all future posted messages fail until reset */
70 if (!countdown)
71 mbx->timeout = 0;
72
73 return countdown ? 0 : IXGBE_ERR_MBX;
74}
75
76/**
77 * ixgbevf_read_posted_mbx - Wait for message notification and receive message
78 * @hw: pointer to the HW structure
79 * @msg: The message buffer
80 * @size: Length of buffer
81 *
82 * returns 0 if it successfully received a message notification and
83 * copied it into the receive buffer.
84 **/
85static s32 ixgbevf_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size)
86{
87 struct ixgbe_mbx_info *mbx = &hw->mbx;
88 s32 ret_val = IXGBE_ERR_MBX;
89
90 ret_val = ixgbevf_poll_for_msg(hw);
91
92 /* if ack received read message, otherwise we timed out */
93 if (!ret_val)
94 ret_val = mbx->ops.read(hw, msg, size);
95
96 return ret_val;
97}
98
99/**
100 * ixgbevf_write_posted_mbx - Write a message to the mailbox, wait for ack
101 * @hw: pointer to the HW structure
102 * @msg: The message buffer
103 * @size: Length of buffer
104 *
105 * returns 0 if it successfully copied message into the buffer and
106 * received an ack to that message within delay * timeout period
107 **/
108static s32 ixgbevf_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size)
109{
110 struct ixgbe_mbx_info *mbx = &hw->mbx;
111 s32 ret_val;
112
113 /* send msg */
114 ret_val = mbx->ops.write(hw, msg, size);
115
116 /* if msg sent wait until we receive an ack */
117 if (!ret_val)
118 ret_val = ixgbevf_poll_for_ack(hw);
119
120 return ret_val;
121}
122
123/**
124 * ixgbevf_read_v2p_mailbox - read v2p mailbox
125 * @hw: pointer to the HW structure
126 *
127 * This function is used to read the v2p mailbox without losing the read to
128 * clear status bits.
129 **/
130static u32 ixgbevf_read_v2p_mailbox(struct ixgbe_hw *hw)
131{
132 u32 v2p_mailbox = IXGBE_READ_REG(hw, IXGBE_VFMAILBOX);
133
134 v2p_mailbox |= hw->mbx.v2p_mailbox;
135 hw->mbx.v2p_mailbox |= v2p_mailbox & IXGBE_VFMAILBOX_R2C_BITS;
136
137 return v2p_mailbox;
138}
139
140/**
141 * ixgbevf_check_for_bit_vf - Determine if a status bit was set
142 * @hw: pointer to the HW structure
143 * @mask: bitmask for bits to be tested and cleared
144 *
145 * This function is used to check for the read to clear bits within
146 * the V2P mailbox.
147 **/
148static s32 ixgbevf_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask)
149{
150 u32 v2p_mailbox = ixgbevf_read_v2p_mailbox(hw);
151 s32 ret_val = IXGBE_ERR_MBX;
152
153 if (v2p_mailbox & mask)
154 ret_val = 0;
155
156 hw->mbx.v2p_mailbox &= ~mask;
157
158 return ret_val;
159}
160
161/**
162 * ixgbevf_check_for_msg_vf - checks to see if the PF has sent mail
163 * @hw: pointer to the HW structure
164 *
165 * returns 0 if the PF has set the Status bit or else ERR_MBX
166 **/
167static s32 ixgbevf_check_for_msg_vf(struct ixgbe_hw *hw)
168{
169 s32 ret_val = IXGBE_ERR_MBX;
170
171 if (!ixgbevf_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFSTS)) {
172 ret_val = 0;
173 hw->mbx.stats.reqs++;
174 }
175
176 return ret_val;
177}
178
179/**
180 * ixgbevf_check_for_ack_vf - checks to see if the PF has ACK'd
181 * @hw: pointer to the HW structure
182 *
183 * returns 0 if the PF has set the ACK bit or else ERR_MBX
184 **/
185static s32 ixgbevf_check_for_ack_vf(struct ixgbe_hw *hw)
186{
187 s32 ret_val = IXGBE_ERR_MBX;
188
189 if (!ixgbevf_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFACK)) {
190 ret_val = 0;
191 hw->mbx.stats.acks++;
192 }
193
194 return ret_val;
195}
196
197/**
198 * ixgbevf_check_for_rst_vf - checks to see if the PF has reset
199 * @hw: pointer to the HW structure
200 *
201 * returns true if the PF has set the reset done bit or else false
202 **/
203static s32 ixgbevf_check_for_rst_vf(struct ixgbe_hw *hw)
204{
205 s32 ret_val = IXGBE_ERR_MBX;
206
207 if (!ixgbevf_check_for_bit_vf(hw, (IXGBE_VFMAILBOX_RSTD |
208 IXGBE_VFMAILBOX_RSTI))) {
209 ret_val = 0;
210 hw->mbx.stats.rsts++;
211 }
212
213 return ret_val;
214}
215
216/**
217 * ixgbevf_obtain_mbx_lock_vf - obtain mailbox lock
218 * @hw: pointer to the HW structure
219 *
220 * return 0 if we obtained the mailbox lock
221 **/
222static s32 ixgbevf_obtain_mbx_lock_vf(struct ixgbe_hw *hw)
223{
224 s32 ret_val = IXGBE_ERR_MBX;
225
226 /* Take ownership of the buffer */
227 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_VFU);
228
229 /* reserve mailbox for vf use */
230 if (ixgbevf_read_v2p_mailbox(hw) & IXGBE_VFMAILBOX_VFU)
231 ret_val = 0;
232
233 return ret_val;
234}
235
236/**
237 * ixgbevf_write_mbx_vf - Write a message to the mailbox
238 * @hw: pointer to the HW structure
239 * @msg: The message buffer
240 * @size: Length of buffer
241 *
242 * returns 0 if it successfully copied message into the buffer
243 **/
244static s32 ixgbevf_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size)
245{
246 s32 ret_val;
247 u16 i;
248
249
250 /* lock the mailbox to prevent pf/vf race condition */
251 ret_val = ixgbevf_obtain_mbx_lock_vf(hw);
252 if (ret_val)
253 goto out_no_write;
254
255 /* flush msg and acks as we are overwriting the message buffer */
256 ixgbevf_check_for_msg_vf(hw);
257 ixgbevf_check_for_ack_vf(hw);
258
259 /* copy the caller specified message to the mailbox memory buffer */
260 for (i = 0; i < size; i++)
261 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_VFMBMEM, i, msg[i]);
262
263 /* update stats */
264 hw->mbx.stats.msgs_tx++;
265
266 /* Drop VFU and interrupt the PF to tell it a message has been sent */
267 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_REQ);
268
269out_no_write:
270 return ret_val;
271}
272
273/**
274 * ixgbevf_read_mbx_vf - Reads a message from the inbox intended for vf
275 * @hw: pointer to the HW structure
276 * @msg: The message buffer
277 * @size: Length of buffer
278 *
279 * returns 0 if it successfuly read message from buffer
280 **/
281static s32 ixgbevf_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size)
282{
283 s32 ret_val = 0;
284 u16 i;
285
286 /* lock the mailbox to prevent pf/vf race condition */
287 ret_val = ixgbevf_obtain_mbx_lock_vf(hw);
288 if (ret_val)
289 goto out_no_read;
290
291 /* copy the message from the mailbox memory buffer */
292 for (i = 0; i < size; i++)
293 msg[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_VFMBMEM, i);
294
295 /* Acknowledge receipt and release mailbox, then we're done */
296 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_ACK);
297
298 /* update stats */
299 hw->mbx.stats.msgs_rx++;
300
301out_no_read:
302 return ret_val;
303}
304
305/**
306 * ixgbevf_init_mbx_params_vf - set initial values for vf mailbox
307 * @hw: pointer to the HW structure
308 *
309 * Initializes the hw->mbx struct to correct values for vf mailbox
310 */
311s32 ixgbevf_init_mbx_params_vf(struct ixgbe_hw *hw)
312{
313 struct ixgbe_mbx_info *mbx = &hw->mbx;
314
315 /* start mailbox as timed out and let the reset_hw call set the timeout
316 * value to begin communications */
317 mbx->timeout = 0;
318 mbx->udelay = IXGBE_VF_MBX_INIT_DELAY;
319
320 mbx->size = IXGBE_VFMAILBOX_SIZE;
321
322 mbx->stats.msgs_tx = 0;
323 mbx->stats.msgs_rx = 0;
324 mbx->stats.reqs = 0;
325 mbx->stats.acks = 0;
326 mbx->stats.rsts = 0;
327
328 return 0;
329}
330
331struct ixgbe_mbx_operations ixgbevf_mbx_ops = {
332 .init_params = ixgbevf_init_mbx_params_vf,
333 .read = ixgbevf_read_mbx_vf,
334 .write = ixgbevf_write_mbx_vf,
335 .read_posted = ixgbevf_read_posted_mbx,
336 .write_posted = ixgbevf_write_posted_mbx,
337 .check_for_msg = ixgbevf_check_for_msg_vf,
338 .check_for_ack = ixgbevf_check_for_ack_vf,
339 .check_for_rst = ixgbevf_check_for_rst_vf,
340};
341
diff --git a/drivers/net/ixgbevf/mbx.h b/drivers/net/ixgbevf/mbx.h
new file mode 100644
index 000000000000..1b0e0bf4c0f5
--- /dev/null
+++ b/drivers/net/ixgbevf/mbx.h
@@ -0,0 +1,100 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_MBX_H_
29#define _IXGBE_MBX_H_
30
31#include "vf.h"
32
33#define IXGBE_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
34#define IXGBE_ERR_MBX -100
35
36#define IXGBE_VFMAILBOX 0x002FC
37#define IXGBE_VFMBMEM 0x00200
38
39/* Define mailbox register bits */
40#define IXGBE_VFMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */
41#define IXGBE_VFMAILBOX_ACK 0x00000002 /* Ack PF message received */
42#define IXGBE_VFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
43#define IXGBE_VFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
44#define IXGBE_VFMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */
45#define IXGBE_VFMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */
46#define IXGBE_VFMAILBOX_RSTI 0x00000040 /* PF has reset indication */
47#define IXGBE_VFMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */
48#define IXGBE_VFMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */
49
50#define IXGBE_PFMAILBOX(x) (0x04B00 + (4 * x))
51#define IXGBE_PFMBMEM(vfn) (0x13000 + (64 * vfn))
52
53#define IXGBE_PFMAILBOX_STS 0x00000001 /* Initiate message send to VF */
54#define IXGBE_PFMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */
55#define IXGBE_PFMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
56#define IXGBE_PFMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
57#define IXGBE_PFMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */
58
59#define IXGBE_MBVFICR_VFREQ_MASK 0x0000FFFF /* bits for VF messages */
60#define IXGBE_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */
61#define IXGBE_MBVFICR_VFACK_MASK 0xFFFF0000 /* bits for VF acks */
62#define IXGBE_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */
63
64
65/* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the
66 * PF. The reverse is true if it is IXGBE_PF_*.
67 * Message ACK's are the value or'd with 0xF0000000
68 */
69#define IXGBE_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with
70 * this are the ACK */
71#define IXGBE_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with
72 * this are the NACK */
73#define IXGBE_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still
74 * clear to send requests */
75#define IXGBE_VT_MSGINFO_SHIFT 16
76/* bits 23:16 are used for exra info for certain messages */
77#define IXGBE_VT_MSGINFO_MASK (0xFF << IXGBE_VT_MSGINFO_SHIFT)
78
79#define IXGBE_VF_RESET 0x01 /* VF requests reset */
80#define IXGBE_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */
81#define IXGBE_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */
82#define IXGBE_VF_SET_VLAN 0x04 /* VF requests PF to set VLAN */
83#define IXGBE_VF_SET_LPE 0x05 /* VF requests PF to set VMOLR.LPE */
84
85/* length of permanent address message returned from PF */
86#define IXGBE_VF_PERMADDR_MSG_LEN 4
87/* word in permanent address message with the current multicast type */
88#define IXGBE_VF_MC_TYPE_WORD 3
89
90#define IXGBE_PF_CONTROL_MSG 0x0100 /* PF control message */
91
92#define IXGBE_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */
93#define IXGBE_VF_MBX_INIT_DELAY 500 /* microseconds between retries */
94
95/* forward declaration of the HW struct */
96struct ixgbe_hw;
97
98s32 ixgbevf_init_mbx_params_vf(struct ixgbe_hw *);
99
100#endif /* _IXGBE_MBX_H_ */
diff --git a/drivers/net/ixgbevf/regs.h b/drivers/net/ixgbevf/regs.h
new file mode 100644
index 000000000000..12f75960aec1
--- /dev/null
+++ b/drivers/net/ixgbevf/regs.h
@@ -0,0 +1,85 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBEVF_REGS_H_
29#define _IXGBEVF_REGS_H_
30
31#define IXGBE_VFCTRL 0x00000
32#define IXGBE_VFSTATUS 0x00008
33#define IXGBE_VFLINKS 0x00010
34#define IXGBE_VFRTIMER 0x00048
35#define IXGBE_VFRXMEMWRAP 0x03190
36#define IXGBE_VTEICR 0x00100
37#define IXGBE_VTEICS 0x00104
38#define IXGBE_VTEIMS 0x00108
39#define IXGBE_VTEIMC 0x0010C
40#define IXGBE_VTEIAC 0x00110
41#define IXGBE_VTEIAM 0x00114
42#define IXGBE_VTEITR(x) (0x00820 + (4 * x))
43#define IXGBE_VTIVAR(x) (0x00120 + (4 * x))
44#define IXGBE_VTIVAR_MISC 0x00140
45#define IXGBE_VTRSCINT(x) (0x00180 + (4 * x))
46#define IXGBE_VFRDBAL(x) (0x01000 + (0x40 * x))
47#define IXGBE_VFRDBAH(x) (0x01004 + (0x40 * x))
48#define IXGBE_VFRDLEN(x) (0x01008 + (0x40 * x))
49#define IXGBE_VFRDH(x) (0x01010 + (0x40 * x))
50#define IXGBE_VFRDT(x) (0x01018 + (0x40 * x))
51#define IXGBE_VFRXDCTL(x) (0x01028 + (0x40 * x))
52#define IXGBE_VFSRRCTL(x) (0x01014 + (0x40 * x))
53#define IXGBE_VFRSCCTL(x) (0x0102C + (0x40 * x))
54#define IXGBE_VFPSRTYPE 0x00300
55#define IXGBE_VFTDBAL(x) (0x02000 + (0x40 * x))
56#define IXGBE_VFTDBAH(x) (0x02004 + (0x40 * x))
57#define IXGBE_VFTDLEN(x) (0x02008 + (0x40 * x))
58#define IXGBE_VFTDH(x) (0x02010 + (0x40 * x))
59#define IXGBE_VFTDT(x) (0x02018 + (0x40 * x))
60#define IXGBE_VFTXDCTL(x) (0x02028 + (0x40 * x))
61#define IXGBE_VFTDWBAL(x) (0x02038 + (0x40 * x))
62#define IXGBE_VFTDWBAH(x) (0x0203C + (0x40 * x))
63#define IXGBE_VFDCA_RXCTRL(x) (0x0100C + (0x40 * x))
64#define IXGBE_VFDCA_TXCTRL(x) (0x0200c + (0x40 * x))
65#define IXGBE_VFGPRC 0x0101C
66#define IXGBE_VFGPTC 0x0201C
67#define IXGBE_VFGORC_LSB 0x01020
68#define IXGBE_VFGORC_MSB 0x01024
69#define IXGBE_VFGOTC_LSB 0x02020
70#define IXGBE_VFGOTC_MSB 0x02024
71#define IXGBE_VFMPRC 0x01034
72
73#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
74
75#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
76
77#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
78 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
79
80#define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \
81 readl((a)->hw_addr + (reg) + ((offset) << 2)))
82
83#define IXGBE_WRITE_FLUSH(a) (IXGBE_READ_REG(a, IXGBE_VFSTATUS))
84
85#endif /* _IXGBEVF_REGS_H_ */
diff --git a/drivers/net/ixgbevf/vf.c b/drivers/net/ixgbevf/vf.c
new file mode 100644
index 000000000000..4b5dec0ec140
--- /dev/null
+++ b/drivers/net/ixgbevf/vf.c
@@ -0,0 +1,387 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include "vf.h"
29
30/**
31 * ixgbevf_start_hw_vf - Prepare hardware for Tx/Rx
32 * @hw: pointer to hardware structure
33 *
34 * Starts the hardware by filling the bus info structure and media type, clears
35 * all on chip counters, initializes receive address registers, multicast
36 * table, VLAN filter table, calls routine to set up link and flow control
37 * settings, and leaves transmit and receive units disabled and uninitialized
38 **/
39static s32 ixgbevf_start_hw_vf(struct ixgbe_hw *hw)
40{
41 /* Clear adapter stopped flag */
42 hw->adapter_stopped = false;
43
44 return 0;
45}
46
47/**
48 * ixgbevf_init_hw_vf - virtual function hardware initialization
49 * @hw: pointer to hardware structure
50 *
51 * Initialize the hardware by resetting the hardware and then starting
52 * the hardware
53 **/
54static s32 ixgbevf_init_hw_vf(struct ixgbe_hw *hw)
55{
56 s32 status = hw->mac.ops.start_hw(hw);
57
58 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
59
60 return status;
61}
62
63/**
64 * ixgbevf_reset_hw_vf - Performs hardware reset
65 * @hw: pointer to hardware structure
66 *
67 * Resets the hardware by reseting the transmit and receive units, masks and
68 * clears all interrupts.
69 **/
70static s32 ixgbevf_reset_hw_vf(struct ixgbe_hw *hw)
71{
72 struct ixgbe_mbx_info *mbx = &hw->mbx;
73 u32 timeout = IXGBE_VF_INIT_TIMEOUT;
74 s32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR;
75 u32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN];
76 u8 *addr = (u8 *)(&msgbuf[1]);
77
78 /* Call adapter stop to disable tx/rx and clear interrupts */
79 hw->mac.ops.stop_adapter(hw);
80
81 IXGBE_WRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST);
82 IXGBE_WRITE_FLUSH(hw);
83
84 /* we cannot reset while the RSTI / RSTD bits are asserted */
85 while (!mbx->ops.check_for_rst(hw) && timeout) {
86 timeout--;
87 udelay(5);
88 }
89
90 if (!timeout)
91 return IXGBE_ERR_RESET_FAILED;
92
93 /* mailbox timeout can now become active */
94 mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT;
95
96 msgbuf[0] = IXGBE_VF_RESET;
97 mbx->ops.write_posted(hw, msgbuf, 1);
98
99 msleep(10);
100
101 /* set our "perm_addr" based on info provided by PF */
102 /* also set up the mc_filter_type which is piggy backed
103 * on the mac address in word 3 */
104 ret_val = mbx->ops.read_posted(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN);
105 if (ret_val)
106 return ret_val;
107
108 if (msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK))
109 return IXGBE_ERR_INVALID_MAC_ADDR;
110
111 memcpy(hw->mac.perm_addr, addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
112 hw->mac.mc_filter_type = msgbuf[IXGBE_VF_MC_TYPE_WORD];
113
114 return 0;
115}
116
117/**
118 * ixgbevf_stop_hw_vf - Generic stop Tx/Rx units
119 * @hw: pointer to hardware structure
120 *
121 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
122 * disables transmit and receive units. The adapter_stopped flag is used by
123 * the shared code and drivers to determine if the adapter is in a stopped
124 * state and should not touch the hardware.
125 **/
126static s32 ixgbevf_stop_hw_vf(struct ixgbe_hw *hw)
127{
128 u32 number_of_queues;
129 u32 reg_val;
130 u16 i;
131
132 /*
133 * Set the adapter_stopped flag so other driver functions stop touching
134 * the hardware
135 */
136 hw->adapter_stopped = true;
137
138 /* Disable the receive unit by stopped each queue */
139 number_of_queues = hw->mac.max_rx_queues;
140 for (i = 0; i < number_of_queues; i++) {
141 reg_val = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
142 if (reg_val & IXGBE_RXDCTL_ENABLE) {
143 reg_val &= ~IXGBE_RXDCTL_ENABLE;
144 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);
145 }
146 }
147
148 IXGBE_WRITE_FLUSH(hw);
149
150 /* Clear interrupt mask to stop from interrupts being generated */
151 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
152
153 /* Clear any pending interrupts */
154 IXGBE_READ_REG(hw, IXGBE_VTEICR);
155
156 /* Disable the transmit unit. Each queue must be disabled. */
157 number_of_queues = hw->mac.max_tx_queues;
158 for (i = 0; i < number_of_queues; i++) {
159 reg_val = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
160 if (reg_val & IXGBE_TXDCTL_ENABLE) {
161 reg_val &= ~IXGBE_TXDCTL_ENABLE;
162 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), reg_val);
163 }
164 }
165
166 return 0;
167}
168
169/**
170 * ixgbevf_mta_vector - Determines bit-vector in multicast table to set
171 * @hw: pointer to hardware structure
172 * @mc_addr: the multicast address
173 *
174 * Extracts the 12 bits, from a multicast address, to determine which
175 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
176 * incoming rx multicast addresses, to determine the bit-vector to check in
177 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
178 * by the MO field of the MCSTCTRL. The MO field is set during initialization
179 * to mc_filter_type.
180 **/
181static s32 ixgbevf_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
182{
183 u32 vector = 0;
184
185 switch (hw->mac.mc_filter_type) {
186 case 0: /* use bits [47:36] of the address */
187 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
188 break;
189 case 1: /* use bits [46:35] of the address */
190 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
191 break;
192 case 2: /* use bits [45:34] of the address */
193 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
194 break;
195 case 3: /* use bits [43:32] of the address */
196 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
197 break;
198 default: /* Invalid mc_filter_type */
199 break;
200 }
201
202 /* vector can only be 12-bits or boundary will be exceeded */
203 vector &= 0xFFF;
204 return vector;
205}
206
207/**
208 * ixgbevf_get_mac_addr_vf - Read device MAC address
209 * @hw: pointer to the HW structure
210 * @mac_addr: pointer to storage for retrieved MAC address
211 **/
212static s32 ixgbevf_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr)
213{
214 memcpy(mac_addr, hw->mac.perm_addr, IXGBE_ETH_LENGTH_OF_ADDRESS);
215
216 return 0;
217}
218
219/**
220 * ixgbevf_set_rar_vf - set device MAC address
221 * @hw: pointer to hardware structure
222 * @index: Receive address register to write
223 * @addr: Address to put into receive address register
224 * @vmdq: Unused in this implementation
225 **/
226static s32 ixgbevf_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr,
227 u32 vmdq)
228{
229 struct ixgbe_mbx_info *mbx = &hw->mbx;
230 u32 msgbuf[3];
231 u8 *msg_addr = (u8 *)(&msgbuf[1]);
232 s32 ret_val;
233
234 memset(msgbuf, 0, sizeof(msgbuf));
235 msgbuf[0] = IXGBE_VF_SET_MAC_ADDR;
236 memcpy(msg_addr, addr, 6);
237 ret_val = mbx->ops.write_posted(hw, msgbuf, 3);
238
239 if (!ret_val)
240 ret_val = mbx->ops.read_posted(hw, msgbuf, 3);
241
242 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
243
244 /* if nacked the address was rejected, use "perm_addr" */
245 if (!ret_val &&
246 (msgbuf[0] == (IXGBE_VF_SET_MAC_ADDR | IXGBE_VT_MSGTYPE_NACK)))
247 ixgbevf_get_mac_addr_vf(hw, hw->mac.addr);
248
249 return ret_val;
250}
251
252/**
253 * ixgbevf_update_mc_addr_list_vf - Update Multicast addresses
254 * @hw: pointer to the HW structure
255 * @mc_addr_list: array of multicast addresses to program
256 * @mc_addr_count: number of multicast addresses to program
257 * @next: caller supplied function to return next address in list
258 *
259 * Updates the Multicast Table Array.
260 **/
261static s32 ixgbevf_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list,
262 u32 mc_addr_count,
263 ixgbe_mc_addr_itr next)
264{
265 struct ixgbe_mbx_info *mbx = &hw->mbx;
266 u32 msgbuf[IXGBE_VFMAILBOX_SIZE];
267 u16 *vector_list = (u16 *)&msgbuf[1];
268 u32 vector;
269 u32 cnt, i;
270 u32 vmdq;
271
272 /* Each entry in the list uses 1 16 bit word. We have 30
273 * 16 bit words available in our HW msg buffer (minus 1 for the
274 * msg type). That's 30 hash values if we pack 'em right. If
275 * there are more than 30 MC addresses to add then punt the
276 * extras for now and then add code to handle more than 30 later.
277 * It would be unusual for a server to request that many multi-cast
278 * addresses except for in large enterprise network environments.
279 */
280
281 cnt = (mc_addr_count > 30) ? 30 : mc_addr_count;
282 msgbuf[0] = IXGBE_VF_SET_MULTICAST;
283 msgbuf[0] |= cnt << IXGBE_VT_MSGINFO_SHIFT;
284
285 for (i = 0; i < cnt; i++) {
286 vector = ixgbevf_mta_vector(hw, next(hw, &mc_addr_list, &vmdq));
287 vector_list[i] = vector;
288 }
289
290 mbx->ops.write_posted(hw, msgbuf, IXGBE_VFMAILBOX_SIZE);
291
292 return 0;
293}
294
295/**
296 * ixgbevf_set_vfta_vf - Set/Unset vlan filter table address
297 * @hw: pointer to the HW structure
298 * @vlan: 12 bit VLAN ID
299 * @vind: unused by VF drivers
300 * @vlan_on: if true then set bit, else clear bit
301 **/
302static s32 ixgbevf_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
303 bool vlan_on)
304{
305 struct ixgbe_mbx_info *mbx = &hw->mbx;
306 u32 msgbuf[2];
307
308 msgbuf[0] = IXGBE_VF_SET_VLAN;
309 msgbuf[1] = vlan;
310 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
311 msgbuf[0] |= vlan_on << IXGBE_VT_MSGINFO_SHIFT;
312
313 return mbx->ops.write_posted(hw, msgbuf, 2);
314}
315
316/**
317 * ixgbevf_setup_mac_link_vf - Setup MAC link settings
318 * @hw: pointer to hardware structure
319 * @speed: Unused in this implementation
320 * @autoneg: Unused in this implementation
321 * @autoneg_wait_to_complete: Unused in this implementation
322 *
323 * Do nothing and return success. VF drivers are not allowed to change
324 * global settings. Maintained for driver compatibility.
325 **/
326static s32 ixgbevf_setup_mac_link_vf(struct ixgbe_hw *hw,
327 ixgbe_link_speed speed, bool autoneg,
328 bool autoneg_wait_to_complete)
329{
330 return 0;
331}
332
333/**
334 * ixgbevf_check_mac_link_vf - Get link/speed status
335 * @hw: pointer to hardware structure
336 * @speed: pointer to link speed
337 * @link_up: true is link is up, false otherwise
338 * @autoneg_wait_to_complete: true when waiting for completion is needed
339 *
340 * Reads the links register to determine if link is up and the current speed
341 **/
342static s32 ixgbevf_check_mac_link_vf(struct ixgbe_hw *hw,
343 ixgbe_link_speed *speed,
344 bool *link_up,
345 bool autoneg_wait_to_complete)
346{
347 u32 links_reg;
348
349 if (!(hw->mbx.ops.check_for_rst(hw))) {
350 *link_up = false;
351 *speed = 0;
352 return -1;
353 }
354
355 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
356
357 if (links_reg & IXGBE_LINKS_UP)
358 *link_up = true;
359 else
360 *link_up = false;
361
362 if (links_reg & IXGBE_LINKS_SPEED)
363 *speed = IXGBE_LINK_SPEED_10GB_FULL;
364 else
365 *speed = IXGBE_LINK_SPEED_1GB_FULL;
366
367 return 0;
368}
369
370struct ixgbe_mac_operations ixgbevf_mac_ops = {
371 .init_hw = ixgbevf_init_hw_vf,
372 .reset_hw = ixgbevf_reset_hw_vf,
373 .start_hw = ixgbevf_start_hw_vf,
374 .get_mac_addr = ixgbevf_get_mac_addr_vf,
375 .stop_adapter = ixgbevf_stop_hw_vf,
376 .setup_link = ixgbevf_setup_mac_link_vf,
377 .check_link = ixgbevf_check_mac_link_vf,
378 .set_rar = ixgbevf_set_rar_vf,
379 .update_mc_addr_list = ixgbevf_update_mc_addr_list_vf,
380 .set_vfta = ixgbevf_set_vfta_vf,
381};
382
383struct ixgbevf_info ixgbevf_vf_info = {
384 .mac = ixgbe_mac_82599_vf,
385 .mac_ops = &ixgbevf_mac_ops,
386};
387
diff --git a/drivers/net/ixgbevf/vf.h b/drivers/net/ixgbevf/vf.h
new file mode 100644
index 000000000000..799600e92700
--- /dev/null
+++ b/drivers/net/ixgbevf/vf.h
@@ -0,0 +1,168 @@
1/*******************************************************************************
2
3 Intel 82599 Virtual Function driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef __IXGBE_VF_H__
29#define __IXGBE_VF_H__
30
31#include <linux/pci.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
34#include <linux/if_ether.h>
35
36#include "defines.h"
37#include "regs.h"
38#include "mbx.h"
39
40struct ixgbe_hw;
41
42/* iterator type for walking multicast address lists */
43typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
44 u32 *vmdq);
45struct ixgbe_mac_operations {
46 s32 (*init_hw)(struct ixgbe_hw *);
47 s32 (*reset_hw)(struct ixgbe_hw *);
48 s32 (*start_hw)(struct ixgbe_hw *);
49 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
50 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
51 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
52 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
53 s32 (*stop_adapter)(struct ixgbe_hw *);
54 s32 (*get_bus_info)(struct ixgbe_hw *);
55
56 /* Link */
57 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
58 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
59 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
60 bool *);
61
62 /* RAR, Multicast, VLAN */
63 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32);
64 s32 (*init_rx_addrs)(struct ixgbe_hw *);
65 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
66 ixgbe_mc_addr_itr);
67 s32 (*enable_mc)(struct ixgbe_hw *);
68 s32 (*disable_mc)(struct ixgbe_hw *);
69 s32 (*clear_vfta)(struct ixgbe_hw *);
70 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
71};
72
73enum ixgbe_mac_type {
74 ixgbe_mac_unknown = 0,
75 ixgbe_mac_82599_vf,
76 ixgbe_num_macs
77};
78
79struct ixgbe_mac_info {
80 struct ixgbe_mac_operations ops;
81 u8 addr[6];
82 u8 perm_addr[6];
83
84 enum ixgbe_mac_type type;
85
86 s32 mc_filter_type;
87
88 bool get_link_status;
89 u32 max_tx_queues;
90 u32 max_rx_queues;
91 u32 max_msix_vectors;
92};
93
94struct ixgbe_mbx_operations {
95 s32 (*init_params)(struct ixgbe_hw *hw);
96 s32 (*read)(struct ixgbe_hw *, u32 *, u16);
97 s32 (*write)(struct ixgbe_hw *, u32 *, u16);
98 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16);
99 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16);
100 s32 (*check_for_msg)(struct ixgbe_hw *);
101 s32 (*check_for_ack)(struct ixgbe_hw *);
102 s32 (*check_for_rst)(struct ixgbe_hw *);
103};
104
105struct ixgbe_mbx_stats {
106 u32 msgs_tx;
107 u32 msgs_rx;
108
109 u32 acks;
110 u32 reqs;
111 u32 rsts;
112};
113
114struct ixgbe_mbx_info {
115 struct ixgbe_mbx_operations ops;
116 struct ixgbe_mbx_stats stats;
117 u32 timeout;
118 u32 udelay;
119 u32 v2p_mailbox;
120 u16 size;
121};
122
123struct ixgbe_hw {
124 void *back;
125
126 u8 __iomem *hw_addr;
127 u8 *flash_address;
128 unsigned long io_base;
129
130 struct ixgbe_mac_info mac;
131 struct ixgbe_mbx_info mbx;
132
133 u16 device_id;
134 u16 subsystem_vendor_id;
135 u16 subsystem_device_id;
136 u16 vendor_id;
137
138 u8 revision_id;
139 bool adapter_stopped;
140};
141
142struct ixgbevf_hw_stats {
143 u64 base_vfgprc;
144 u64 base_vfgptc;
145 u64 base_vfgorc;
146 u64 base_vfgotc;
147 u64 base_vfmprc;
148
149 u64 last_vfgprc;
150 u64 last_vfgptc;
151 u64 last_vfgorc;
152 u64 last_vfgotc;
153 u64 last_vfmprc;
154
155 u64 vfgprc;
156 u64 vfgptc;
157 u64 vfgorc;
158 u64 vfgotc;
159 u64 vfmprc;
160};
161
162struct ixgbevf_info {
163 enum ixgbe_mac_type mac;
164 struct ixgbe_mac_operations *mac_ops;
165};
166
167#endif /* __IXGBE_VF_H__ */
168
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-10 10:36:04 -0400