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authorJohn Fastabend <john.r.fastabend@intel.com>2011-04-04 00:29:41 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-04-13 22:26:43 -0400
commite09ad236fc85b1d6e010138f59aba76f6c9a295b (patch)
tree7f05239838d579f23a71106d1880155e2359d882 /drivers/net/ixgbe
parentb776d1043510c60f59220eb5e58b524f5a7f0e52 (diff)
ixgbe: DCB, misallocated packet buffer size with X540 device
The X540 device has a smaller packet buffer but the DCB configuration never took this into account. Under stress this can result in the DMA engine hanging and TX Unit hang occurring to reset the device. This patch reworks the packet buffer allocation routine used for DCB on 82599 and X540 devices to account for RX packet buffer sizes. This fixes the immediate hang. We should consolidate the various hardware specific routines for configuring features into a single routine. This will make it much harder to miss feature cases like this. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Tested-by: Evan Swanson <evan.swanson@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ixgbe')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c3
-rw-r--r--drivers/net/ixgbe/ixgbe_82599.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.c68
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82599.h2
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h1
-rw-r--r--drivers/net/ixgbe/ixgbe_x540.c3
6 files changed, 52 insertions, 27 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index af4054a1a133..7a64f50435cf 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -37,6 +37,7 @@
37#define IXGBE_82598_RAR_ENTRIES 16 37#define IXGBE_82598_RAR_ENTRIES 16
38#define IXGBE_82598_MC_TBL_SIZE 128 38#define IXGBE_82598_MC_TBL_SIZE 128
39#define IXGBE_82598_VFT_TBL_SIZE 128 39#define IXGBE_82598_VFT_TBL_SIZE 128
40#define IXGBE_82598_RX_PB_SIZE 512
40 41
41static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, 42static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed, 43 ixgbe_link_speed speed,
@@ -224,6 +225,8 @@ static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
224 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 225 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
225 } 226 }
226 227
228 hw->mac.rx_pb_size = IXGBE_82598_RX_PB_SIZE;
229
227 /* set the completion timeout for interface */ 230 /* set the completion timeout for interface */
228 if (ret_val == 0) 231 if (ret_val == 0)
229 ixgbe_set_pcie_completion_timeout(hw); 232 ixgbe_set_pcie_completion_timeout(hw);
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index e4323055347b..b341ed8ef84f 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -38,6 +38,7 @@
38#define IXGBE_82599_RAR_ENTRIES 128 38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128 39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128 40#define IXGBE_82599_VFT_TBL_SIZE 128
41#define IXGBE_82599_RX_PB_SIZE 512
41 42
42static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 43static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 44static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
@@ -1765,6 +1766,7 @@ static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1765 1766
1766 /* We need to run link autotry after the driver loads */ 1767 /* We need to run link autotry after the driver loads */
1767 hw->mac.autotry_restart = true; 1768 hw->mac.autotry_restart = true;
1769 hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
1768 1770
1769 if (ret_val == 0) 1771 if (ret_val == 0)
1770 ret_val = ixgbe_verify_fw_version_82599(hw); 1772 ret_val = ixgbe_verify_fw_version_82599(hw);
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index 025af8c53ddb..865ddd82b268 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -39,36 +39,52 @@
39 */ 39 */
40static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, u8 rx_pba) 40static s32 ixgbe_dcb_config_packet_buffers_82599(struct ixgbe_hw *hw, u8 rx_pba)
41{ 41{
42 s32 ret_val = 0; 42 int num_tcs = IXGBE_MAX_PACKET_BUFFERS;
43 u32 value = IXGBE_RXPBSIZE_64KB; 43 u32 rx_pb_size = hw->mac.rx_pb_size << IXGBE_RXPBSIZE_SHIFT;
44 u32 rxpktsize;
45 u32 txpktsize;
46 u32 txpbthresh;
44 u8 i = 0; 47 u8 i = 0;
45 48
46 /* Setup Rx packet buffer sizes */ 49 /*
47 switch (rx_pba) { 50 * This really means configure the first half of the TCs
48 case pba_80_48: 51 * (Traffic Classes) to use 5/8 of the Rx packet buffer
49 /* Setup the first four at 80KB */ 52 * space. To determine the size of the buffer for each TC,
50 value = IXGBE_RXPBSIZE_80KB; 53 * we are multiplying the average size by 5/4 and applying
51 for (; i < 4; i++) 54 * it to half of the traffic classes.
52 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value); 55 */
53 /* Setup the last four at 48KB...don't re-init i */ 56 if (rx_pba == pba_80_48) {
54 value = IXGBE_RXPBSIZE_48KB; 57 rxpktsize = (rx_pb_size * 5) / (num_tcs * 4);
55 /* Fall Through */ 58 rx_pb_size -= rxpktsize * (num_tcs / 2);
56 case pba_equal: 59 for (; i < (num_tcs / 2); i++)
57 default: 60 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
58 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++) 61 }
59 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), value); 62
60 63 /* Divide the remaining Rx packet buffer evenly among the TCs */
61 /* Setup Tx packet buffer sizes */ 64 rxpktsize = rx_pb_size / (num_tcs - i);
62 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) { 65 for (; i < num_tcs; i++)
63 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 66 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
64 IXGBE_TXPBSIZE_20KB); 67
65 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 68 /*
66 IXGBE_TXPBTHRESH_DCB); 69 * Setup Tx packet buffer and threshold equally for all TCs
67 } 70 * TXPBTHRESH register is set in K so divide by 1024 and subtract
68 break; 71 * 10 since the largest packet we support is just over 9K.
72 */
73 txpktsize = IXGBE_TXPBSIZE_MAX / num_tcs;
74 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
75 for (i = 0; i < num_tcs; i++) {
76 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
77 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
69 } 78 }
70 79
71 return ret_val; 80 /* Clear unused TCs, if any, to zero buffer size*/
81 for (; i < MAX_TRAFFIC_CLASS; i++) {
82 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
83 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
84 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
85 }
86
87 return 0;
72} 88}
73 89
74/** 90/**
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.h b/drivers/net/ixgbe/ixgbe_dcb_82599.h
index 148fd8b477a9..2de71a503153 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.h
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.h
@@ -92,8 +92,10 @@
92#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 92#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
93#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 93#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
94#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 94#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
95#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer*/
95 96
96#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */ 97#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */
98#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
97 99
98/* SECTXMINIFG DCB */ 100/* SECTXMINIFG DCB */
99#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer IFG */ 101#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer IFG */
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 15580d687aee..7d0b37d2ab7b 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -2606,6 +2606,7 @@ struct ixgbe_mac_info {
2606 u32 vft_size; 2606 u32 vft_size;
2607 u32 num_rar_entries; 2607 u32 num_rar_entries;
2608 u32 rar_highwater; 2608 u32 rar_highwater;
2609 u32 rx_pb_size;
2609 u32 max_tx_queues; 2610 u32 max_tx_queues;
2610 u32 max_rx_queues; 2611 u32 max_rx_queues;
2611 u32 max_msix_vectors; 2612 u32 max_msix_vectors;
diff --git a/drivers/net/ixgbe/ixgbe_x540.c b/drivers/net/ixgbe/ixgbe_x540.c
index 05f8e9cddef4..932394fce439 100644
--- a/drivers/net/ixgbe/ixgbe_x540.c
+++ b/drivers/net/ixgbe/ixgbe_x540.c
@@ -37,6 +37,7 @@
37#define IXGBE_X540_RAR_ENTRIES 128 37#define IXGBE_X540_RAR_ENTRIES 128
38#define IXGBE_X540_MC_TBL_SIZE 128 38#define IXGBE_X540_MC_TBL_SIZE 128
39#define IXGBE_X540_VFT_TBL_SIZE 128 39#define IXGBE_X540_VFT_TBL_SIZE 128
40#define IXGBE_X540_RX_PB_SIZE 384
40 41
41static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); 42static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
42static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 43static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
@@ -242,7 +243,7 @@ static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
242 goto out; 243 goto out;
243 244
244 ret_val = ixgbe_start_hw_gen2(hw); 245 ret_val = ixgbe_start_hw_gen2(hw);
245 246 hw->mac.rx_pb_size = IXGBE_X540_RX_PB_SIZE;
246out: 247out:
247 return ret_val; 248 return ret_val;
248} 249}