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authorEmil Tantilov <emil.s.tantilov@intel.com>2011-03-18 21:32:46 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-04-13 22:22:18 -0400
commit3d5c520727ce3dbf418eec38e431856708f946f8 (patch)
tree50b944c1a794b0a5b178ca04063fa8f4631ee268 /drivers/net/ixgbe
parent7184b7cf555f5bc08e34994147c341abb07d1dbb (diff)
ixgbe: move disabling of relaxed ordering in start_hw()
Relaxed ordering can lead to issues with some chipsets. This patch makes sure that it is disabled by default and not only when DCA is on. Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Tested-by: Evan Swanson <evan.swanson@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ixgbe')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c21
-rw-r--r--drivers/net/ixgbe/ixgbe_common.c15
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c4
3 files changed, 35 insertions, 5 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index c9b6574cdd72..a93275fd260f 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -197,14 +197,33 @@ out:
197 * @hw: pointer to hardware structure 197 * @hw: pointer to hardware structure
198 * 198 *
199 * Starts the hardware using the generic start_hw function. 199 * Starts the hardware using the generic start_hw function.
200 * Then set pcie completion timeout 200 * Disables relaxed ordering Then set pcie completion timeout
201 *
201 **/ 202 **/
202static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw) 203static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
203{ 204{
205 u32 regval;
206 u32 i;
204 s32 ret_val = 0; 207 s32 ret_val = 0;
205 208
206 ret_val = ixgbe_start_hw_generic(hw); 209 ret_val = ixgbe_start_hw_generic(hw);
207 210
211 /* Disable relaxed ordering */
212 for (i = 0; ((i < hw->mac.max_tx_queues) &&
213 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
214 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
215 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
216 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
217 }
218
219 for (i = 0; ((i < hw->mac.max_rx_queues) &&
220 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
221 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
222 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
223 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
224 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
225 }
226
208 /* set the completion timeout for interface */ 227 /* set the completion timeout for interface */
209 if (ret_val == 0) 228 if (ret_val == 0)
210 ixgbe_set_pcie_completion_timeout(hw); 229 ixgbe_set_pcie_completion_timeout(hw);
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index c66fd957578c..1b8b3cd1664f 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -108,6 +108,7 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
108s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 108s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
109{ 109{
110 u32 i; 110 u32 i;
111 u32 regval;
111 112
112 /* Clear the rate limiters */ 113 /* Clear the rate limiters */
113 for (i = 0; i < hw->mac.max_tx_queues; i++) { 114 for (i = 0; i < hw->mac.max_tx_queues; i++) {
@@ -116,6 +117,20 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
116 } 117 }
117 IXGBE_WRITE_FLUSH(hw); 118 IXGBE_WRITE_FLUSH(hw);
118 119
120 /* Disable relaxed ordering */
121 for (i = 0; i < hw->mac.max_tx_queues; i++) {
122 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
123 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
124 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
125 }
126
127 for (i = 0; i < hw->mac.max_rx_queues; i++) {
128 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
129 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
130 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
131 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
132 }
133
119 return 0; 134 return 0;
120} 135}
121 136
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 3dbe6896b2c3..3148e2182e92 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -947,8 +947,6 @@ static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
947 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; 947 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
948 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; 948 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
949 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); 949 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
950 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
951 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
952 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 950 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
953} 951}
954 952
@@ -966,7 +964,6 @@ static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
966 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; 964 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
967 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); 965 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
968 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; 966 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
969 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
970 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl); 967 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
971 break; 968 break;
972 case ixgbe_mac_82599EB: 969 case ixgbe_mac_82599EB:
@@ -976,7 +973,6 @@ static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
976 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << 973 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
977 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); 974 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
978 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; 975 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
979 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
980 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl); 976 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
981 break; 977 break;
982 default: 978 default: