ixgbe: add device support for 82598AT (copper 10GbE) adapters

Intel is currently shipping support for adapters with a phy
that does 10GBase-T (copper), which is 10 Gigabit ethernet
over standard Category 6 cabling.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>

1 files changed, 68 insertions, 0 deletions

diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index 764035a8c9a1..981e6d849592 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -121,6 +121,9 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
         enum ixgbe_phy_type phy_type;
 
         switch (phy_id) {
+        case TN1010_PHY_ID:
+                phy_type = ixgbe_phy_tn;
+                break;
         case QT2022_PHY_ID:
                 phy_type = ixgbe_phy_qt;
                 break;
@@ -426,3 +429,68 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
         return 0;
 }
 
+/**
+ *  ixgbe_check_phy_link_tnx - Determine link and speed status
+ *  @hw: pointer to hardware structure
+ *
+ *  Reads the VS1 register to determine if link is up and the current speed for
+ *  the PHY.
+ **/
+s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                             bool *link_up)
+{
+        s32 status = 0;
+        u32 time_out;
+        u32 max_time_out = 10;
+        u16 phy_link = 0;
+        u16 phy_speed = 0;
+        u16 phy_data = 0;
+
+        /* Initialize speed and link to default case */
+        *link_up = false;
+        *speed = IXGBE_LINK_SPEED_10GB_FULL;
+
+        /*
+         * Check current speed and link status of the PHY register.
+         * This is a vendor specific register and may have to
+         * be changed for other copper PHYs.
+         */
+        for (time_out = 0; time_out < max_time_out; time_out++) {
+                udelay(10);
+                status = hw->phy.ops.read_reg(hw,
+                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
+                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
+                                        &phy_data);
+                phy_link = phy_data &
+                           IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
+                phy_speed = phy_data &
+                            IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
+                if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
+                        *link_up = true;
+                        if (phy_speed ==
+                            IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
+                                *speed = IXGBE_LINK_SPEED_1GB_FULL;
+                        break;
+                }
+        }
+
+        return status;
+}
+
+/**
+ *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
+ *  @hw: pointer to hardware structure
+ *  @firmware_version: pointer to the PHY Firmware Version
+ **/
+s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
+                                       u16 *firmware_version)
+{
+        s32 status = 0;
+
+        status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
+                                      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
+                                      firmware_version);
+
+        return status;
+}
+