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authorJesse Brandeburg <jesse.brandeburg@intel.com>2010-04-26 21:37:20 -0400
committerDavid S. Miller <davem@davemloft.net>2010-04-27 15:53:27 -0400
commitf8d1dcaf88bddc7f282722ec1fdddbcb06a72f18 (patch)
tree3bd62a02d6a024cf022a4a129607ca08716e26d0 /drivers/net/ixgbe/ixgbe_main.c
parentec857fd40da41d7c50d9a97e07e364c93b8b8e05 (diff)
ixgbe: enable extremely low latency
82598/82599 can support EITR == 0, which allows for the absolutely lowest latency setting in the hardware. This disables writeback batching and anything else that relies upon a delayed interrupt. This patch enables the feature of "override" when a user sets rx-usecs to zero, the driver will respect that setting over using RSC, and automatically disable RSC. If rx-usecs is used to set the EITR value to 0, then the driver should disable LRO (aka RSC) internally until EITR is set to non-zero again. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_main.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 32781b3f8964..0c4ca6822b70 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -1190,6 +1190,15 @@ void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1190 itr_reg |= (itr_reg << 16); 1190 itr_reg |= (itr_reg << 16);
1191 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { 1191 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1192 /* 1192 /*
1193 * 82599 can support a value of zero, so allow it for
1194 * max interrupt rate, but there is an errata where it can
1195 * not be zero with RSC
1196 */
1197 if (itr_reg == 8 &&
1198 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1199 itr_reg = 0;
1200
1201 /*
1193 * set the WDIS bit to not clear the timer bits and cause an 1202 * set the WDIS bit to not clear the timer bits and cause an
1194 * immediate assertion of the interrupt 1203 * immediate assertion of the interrupt
1195 */ 1204 */