ixgbe: setup per CPU PCI pool for FCoE DDP

Currently single PCI pool used across all CPUs and that
doesn't scales up as number of CPU increases, so this
patch adds per CPU PCI pool to setup udl and that aligns
well from FCoE stack as that already has per CPU exch locking.

Adds per CPU PCI alloc setup and free in
ixgbe_fcoe_ddp_pools_alloc and ixgbe_fcoe_ddp_pools_free,
use CPU specific pool during DDP setup.

Re-arranged ixgbe_fcoe struct to have fewer holes
along with adding pools ptr using pahole.

Signed-off-by: Vasu Dev <vasu.dev@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 7 insertions, 6 deletions

diff --git a/drivers/net/ixgbe/ixgbe_fcoe.h b/drivers/net/ixgbe/ixgbe_fcoe.h
index 5a650a4ace66..d876e7ac2257 100644
--- a/drivers/net/ixgbe/ixgbe_fcoe.h
+++ b/drivers/net/ixgbe/ixgbe_fcoe.h
@@ -62,20 +62,21 @@ struct ixgbe_fcoe_ddp {
         struct scatterlist *sgl;
         dma_addr_t udp;
         u64 *udl;
+        struct pci_pool *pool;
 };
 
 struct ixgbe_fcoe {
-#ifdef CONFIG_IXGBE_DCB
-        u8 tc;
-        u8 up;
-#endif
-        unsigned long mode;
+        struct pci_pool **pool;
         atomic_t refcnt;
         spinlock_t lock;
-        struct pci_pool *pool;
         struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX];
         unsigned char *extra_ddp_buffer;
         dma_addr_t extra_ddp_buffer_dma;
+        unsigned long mode;
+#ifdef CONFIG_IXGBE_DCB
+        u8 tc;
+        u8 up;
+#endif
 };
 
 #endif /* _IXGBE_FCOE_H */