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authorYi Zou <yi.zou@intel.com>2009-09-03 10:55:50 -0400
committerDavid S. Miller <davem@davemloft.net>2009-09-03 23:01:51 -0400
commit8de8b2e63490fe7e90128299983198d09d1679c9 (patch)
tree480782ed477329516f583a08d3ce6dd0eac21d01 /drivers/net/ixgbe/ixgbe_dcb_nl.c
parentae641bdc264a5998b7872622c86f0690a5b1c5b5 (diff)
ixgbe: Add support for multiple Tx queues for FCoE in 82599
This patch adds support for multiple transmit queues to the Fiber Channel over Ethernet (FCoE) feature found in 82599. Currently, FCoE has multiple Rx queues available, along with a redirection table, that helps distribute the I/O load across multiple CPUs based on the FC exchange ID. To make this the most effective, we need to provide the same layout of transmit queues to match receive. Particularly, when Data Center Bridging (DCB) is enabled, the designated traffic class for FCoE can have dedicated queues for just FCoE traffic, while not affecting any other type of traffic flow. Signed-off-by: Yi Zou <yi.zou@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_dcb_nl.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_nl.c37
1 files changed, 31 insertions, 6 deletions
diff --git a/drivers/net/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ixgbe/ixgbe_dcb_nl.c
index 47d9dde82a8a..a6bc1ef28f92 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_nl.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_nl.c
@@ -36,6 +36,7 @@
36#define BIT_PFC 0x02 36#define BIT_PFC 0x02
37#define BIT_PG_RX 0x04 37#define BIT_PG_RX 0x04
38#define BIT_PG_TX 0x08 38#define BIT_PG_TX 0x08
39#define BIT_APP_UPCHG 0x10
39#define BIT_RESETLINK 0x40 40#define BIT_RESETLINK 0x40
40#define BIT_LINKSPEED 0x80 41#define BIT_LINKSPEED 0x80
41 42
@@ -348,8 +349,14 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
348 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 349 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
349 msleep(1); 350 msleep(1);
350 351
351 if (netif_running(netdev)) 352 if (adapter->dcb_set_bitmap & BIT_APP_UPCHG) {
352 ixgbe_down(adapter); 353 if (netif_running(netdev))
354 netdev->netdev_ops->ndo_stop(netdev);
355 ixgbe_clear_interrupt_scheme(adapter);
356 } else {
357 if (netif_running(netdev))
358 ixgbe_down(adapter);
359 }
353 } 360 }
354 361
355 ret = ixgbe_copy_dcb_cfg(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 362 ret = ixgbe_copy_dcb_cfg(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
@@ -373,8 +380,14 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
373 } 380 }
374 381
375 if (adapter->dcb_set_bitmap & BIT_RESETLINK) { 382 if (adapter->dcb_set_bitmap & BIT_RESETLINK) {
376 if (netif_running(netdev)) 383 if (adapter->dcb_set_bitmap & BIT_APP_UPCHG) {
377 ixgbe_up(adapter); 384 ixgbe_init_interrupt_scheme(adapter);
385 if (netif_running(netdev))
386 netdev->netdev_ops->ndo_open(netdev);
387 } else {
388 if (netif_running(netdev))
389 ixgbe_up(adapter);
390 }
378 ret = DCB_HW_CHG_RST; 391 ret = DCB_HW_CHG_RST;
379 } else if (adapter->dcb_set_bitmap & BIT_PFC) { 392 } else if (adapter->dcb_set_bitmap & BIT_PFC) {
380 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 393 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
@@ -526,8 +539,20 @@ static u8 ixgbe_dcbnl_setapp(struct net_device *netdev,
526 switch (idtype) { 539 switch (idtype) {
527 case DCB_APP_IDTYPE_ETHTYPE: 540 case DCB_APP_IDTYPE_ETHTYPE:
528#ifdef IXGBE_FCOE 541#ifdef IXGBE_FCOE
529 if (id == ETH_P_FCOE) 542 if (id == ETH_P_FCOE) {
530 rval = ixgbe_fcoe_setapp(netdev_priv(netdev), up); 543 u8 tc;
544 struct ixgbe_adapter *adapter;
545
546 adapter = netdev_priv(netdev);
547 tc = adapter->fcoe.tc;
548 rval = ixgbe_fcoe_setapp(adapter, up);
549 if ((!rval) && (tc != adapter->fcoe.tc) &&
550 (adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
551 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
552 adapter->dcb_set_bitmap |= BIT_APP_UPCHG;
553 adapter->dcb_set_bitmap |= BIT_RESETLINK;
554 }
555 }
531#endif 556#endif
532 break; 557 break;
533 case DCB_APP_IDTYPE_PORTNUM: 558 case DCB_APP_IDTYPE_PORTNUM: