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authorPeter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>2009-05-17 08:35:16 -0400
committerDavid S. Miller <davem@davemloft.net>2009-05-18 00:04:13 -0400
commit264857b8fe8a16fc95f12e898951fc6bd4bdaa7a (patch)
treeefb090175b49f72170555eab18cdcf1156ed2a4a /drivers/net/ixgbe/ixgbe_dcb_82598.c
parent70b77628d8d943b27cc0f72002b5884028aee38c (diff)
ixgbe: Allow link flow control in DCB mode for 82599 adapters
82599 supports using either link flow control or priority flow control when in DCB mode. The dcbnl interface already supports sending down configurations through rtnetlink that can enable LFC when DCB is enabled, so the driver should take advantage of this. 82598 does not support using LFC when DCB is enabled, so explicitly disable it when we're in DCB mode. This means we always run in PFC mode when DCB is enabled. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_dcb_82598.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb_82598.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ixgbe/ixgbe_dcb_82598.c
index 62206273d888..f30263898ebc 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c
@@ -294,6 +294,9 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
294 u32 reg, rx_pba_size; 294 u32 reg, rx_pba_size;
295 u8 i; 295 u8 i;
296 296
297 if (!dcb_config->pfc_mode_enable)
298 goto out;
299
297 /* Enable Transmit Priority Flow Control */ 300 /* Enable Transmit Priority Flow Control */
298 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 301 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
299 reg &= ~IXGBE_RMCS_TFCE_802_3X; 302 reg &= ~IXGBE_RMCS_TFCE_802_3X;
@@ -341,6 +344,7 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
341 /* Configure flow control refresh threshold value */ 344 /* Configure flow control refresh threshold value */
342 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400); 345 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, 0x3400);
343 346
347out:
344 return 0; 348 return 0;
345} 349}
346 350