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authorJohn Fastabend <john.r.fastabend@intel.com>2011-02-23 00:58:19 -0500
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-03-12 07:12:54 -0500
commit17049d30c2dec6f26d6165cc135578f9e41d53d3 (patch)
treeb58a6c005d89c15a58213cc2e62e9d4de81d8c37 /drivers/net/ixgbe/ixgbe_dcb.c
parent3b97fd695453ced96f22bdf1a84453f6744d25cc (diff)
ixgbe: IEEE 802.1Qaz, implement priority assignment table
This patch adds support to use the priority assignment table in the ieee_ets structure to map priorities to traffic classes. Previously ixgbe only supported a 1:1 mapping. Now we can enable and disable hardware DCB support when multiple traffic classes are actually being used. This allows the default case all priorities mapped to traffic class 0 to work in normal hardware mode and utilize the full packet buffer. This patch does not address putting the hardware in 4TC mode so packet buffer space may be underutilized in this case. A follow up patch can address this optimization. But at least we have the hooks to do this now. Also CEE will behave as it always has and map priorities 1:1 with traffic classes. Signed-off-by: John Fastabend <john.r.fastabend@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_dcb.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_dcb.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/net/ixgbe/ixgbe_dcb.c b/drivers/net/ixgbe/ixgbe_dcb.c
index e2e7a292525d..e7b551af573d 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.c
+++ b/drivers/net/ixgbe/ixgbe_dcb.c
@@ -246,6 +246,8 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
246 u8 bwgid[MAX_TRAFFIC_CLASS]; 246 u8 bwgid[MAX_TRAFFIC_CLASS];
247 u16 refill[MAX_TRAFFIC_CLASS]; 247 u16 refill[MAX_TRAFFIC_CLASS];
248 u16 max[MAX_TRAFFIC_CLASS]; 248 u16 max[MAX_TRAFFIC_CLASS];
249 /* CEE does not define a priority to tc mapping so map 1:1 */
250 u8 prio_tc[MAX_TRAFFIC_CLASS] = {0, 1, 2, 3, 4, 5, 6, 7};
249 251
250 /* Unpack CEE standard containers */ 252 /* Unpack CEE standard containers */
251 ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en); 253 ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en);
@@ -264,7 +266,7 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
264 case ixgbe_mac_X540: 266 case ixgbe_mac_X540:
265 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg, 267 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->rx_pba_cfg,
266 pfc_en, refill, max, bwgid, 268 pfc_en, refill, max, bwgid,
267 ptype); 269 ptype, prio_tc);
268 break; 270 break;
269 default: 271 default:
270 break; 272 break;
@@ -292,7 +294,8 @@ s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en)
292} 294}
293 295
294s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, 296s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
295 u16 *refill, u16 *max, u8 *bwg_id, u8 *prio_type) 297 u16 *refill, u16 *max, u8 *bwg_id,
298 u8 *prio_type, u8 *prio_tc)
296{ 299{
297 switch (hw->mac.type) { 300 switch (hw->mac.type) {
298 case ixgbe_mac_82598EB: 301 case ixgbe_mac_82598EB:
@@ -306,11 +309,11 @@ s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
306 case ixgbe_mac_82599EB: 309 case ixgbe_mac_82599EB:
307 case ixgbe_mac_X540: 310 case ixgbe_mac_X540:
308 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, 311 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
309 bwg_id, prio_type); 312 bwg_id, prio_type, prio_tc);
310 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 313 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
311 bwg_id, prio_type); 314 bwg_id, prio_type);
312 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 315 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
313 bwg_id, prio_type); 316 prio_type, prio_tc);
314 break; 317 break;
315 default: 318 default:
316 break; 319 break;