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authorWaskiewicz Jr, Peter P <peter.p.waskiewicz.jr@intel.com>2009-04-23 07:15:18 -0400
committerDavid S. Miller <davem@davemloft.net>2009-04-27 06:14:48 -0400
commit495dce123ceabbae035552437fcaa0f69247ff08 (patch)
tree7b5cd7c1f8f8c77d7e1e9def4be9638b34ec3bab /drivers/net/ixgbe/ixgbe_common.c
parentae0e8e82205c903978a79ebf5e31c670b61fa5b4 (diff)
ixgbe: Fix WoL functionality for 82599 KX4 devices
The current code writes the PME enabled bit in PCI config space which is wrong. This was needed for pre-release hardware, and was not removed from the driver. Also, we need to clear the WUS (wake up status) after we resume. Otherwise we can't wake for the same event again since it's still asserted in the hardware. Plus, the multicast lists were being written improperly, causing multicast WoL to fail. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_common.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_common.c51
1 files changed, 2 insertions, 49 deletions
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index 5567519676d5..186a65069b33 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -50,7 +50,6 @@ static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
50static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index); 50static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
51static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index); 51static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
52static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 52static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr);
54static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq); 53static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
55 54
56/** 55/**
@@ -1377,8 +1376,7 @@ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
1377 * Clear accounting of old secondary address list, 1376 * Clear accounting of old secondary address list,
1378 * don't count RAR[0] 1377 * don't count RAR[0]
1379 */ 1378 */
1380 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1379 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1381 hw->addr_ctrl.mc_addr_in_rar_count - 1;
1382 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1380 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1383 hw->addr_ctrl.overflow_promisc = 0; 1381 hw->addr_ctrl.overflow_promisc = 0;
1384 1382
@@ -1493,40 +1491,6 @@ static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1493} 1491}
1494 1492
1495/** 1493/**
1496 * ixgbe_add_mc_addr - Adds a multicast address.
1497 * @hw: pointer to hardware structure
1498 * @mc_addr: new multicast address
1499 *
1500 * Adds it to unused receive address register or to the multicast table.
1501 **/
1502static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
1503{
1504 u32 rar_entries = hw->mac.num_rar_entries;
1505 u32 rar;
1506
1507 hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n",
1508 mc_addr[0], mc_addr[1], mc_addr[2],
1509 mc_addr[3], mc_addr[4], mc_addr[5]);
1510
1511 /*
1512 * Place this multicast address in the RAR if there is room,
1513 * else put it in the MTA
1514 */
1515 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1516 /* use RAR from the end up for multicast */
1517 rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1;
1518 hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV);
1519 hw_dbg(hw, "Added a multicast address to RAR[%d]\n", rar);
1520 hw->addr_ctrl.rar_used_count++;
1521 hw->addr_ctrl.mc_addr_in_rar_count++;
1522 } else {
1523 ixgbe_set_mta(hw, mc_addr);
1524 }
1525
1526 hw_dbg(hw, "ixgbe_add_mc_addr Complete\n");
1527}
1528
1529/**
1530 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1494 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1531 * @hw: pointer to hardware structure 1495 * @hw: pointer to hardware structure
1532 * @mc_addr_list: the list of new multicast addresses 1496 * @mc_addr_list: the list of new multicast addresses
@@ -1542,7 +1506,6 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1542 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1506 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1543{ 1507{
1544 u32 i; 1508 u32 i;
1545 u32 rar_entries = hw->mac.num_rar_entries;
1546 u32 vmdq; 1509 u32 vmdq;
1547 1510
1548 /* 1511 /*
@@ -1550,18 +1513,8 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1550 * use. 1513 * use.
1551 */ 1514 */
1552 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1515 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1553 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count;
1554 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1555 hw->addr_ctrl.mta_in_use = 0; 1516 hw->addr_ctrl.mta_in_use = 0;
1556 1517
1557 /* Zero out the other receive addresses. */
1558 hw_dbg(hw, "Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count,
1559 rar_entries - 1);
1560 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) {
1561 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1562 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1563 }
1564
1565 /* Clear the MTA */ 1518 /* Clear the MTA */
1566 hw_dbg(hw, " Clearing MTA\n"); 1519 hw_dbg(hw, " Clearing MTA\n");
1567 for (i = 0; i < hw->mac.mcft_size; i++) 1520 for (i = 0; i < hw->mac.mcft_size; i++)
@@ -1570,7 +1523,7 @@ s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1570 /* Add the new addresses */ 1523 /* Add the new addresses */
1571 for (i = 0; i < mc_addr_count; i++) { 1524 for (i = 0; i < mc_addr_count; i++) {
1572 hw_dbg(hw, " Adding the multicast addresses:\n"); 1525 hw_dbg(hw, " Adding the multicast addresses:\n");
1573 ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq)); 1526 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
1574 } 1527 }
1575 1528
1576 /* Enable mta */ 1529 /* Enable mta */