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authorMallikarjuna R Chilakala <mallikarjuna.chilakala@intel.com>2009-06-04 07:11:13 -0400
committerDavid S. Miller <davem@davemloft.net>2009-06-07 08:20:19 -0400
commit620fa036b2459ca9acf7484c8074147f0dda68da (patch)
tree22ed490ea8f6c711c6c6e6779583dee475cc9729 /drivers/net/ixgbe/ixgbe_common.c
parent50ac58ba1d707df33f0c398ae700214e49bf918f (diff)
ixgbe: Fix 82599 adapter link flickering issues
Fix autoneg restart issues in flow control path which might create endless link flickering due to known timing issues with 82599 adapters. Signed-off-by: Mallikarjuna R Chilakala <mallikarjuna.chilakakla@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_common.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_common.c245
1 files changed, 127 insertions, 118 deletions
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index 4d36cd32cd30..db339d6fe63d 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -85,6 +85,9 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
85 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 85 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
86 IXGBE_WRITE_FLUSH(hw); 86 IXGBE_WRITE_FLUSH(hw);
87 87
88 /* Setup flow control */
89 ixgbe_setup_fc(hw, 0);
90
88 /* Clear adapter stopped flag */ 91 /* Clear adapter stopped flag */
89 hw->adapter_stopped = false; 92 hw->adapter_stopped = false;
90 93
@@ -1577,17 +1580,16 @@ s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1577} 1580}
1578 1581
1579/** 1582/**
1580 * ixgbe_fc_enable - Enable flow control 1583 * ixgbe_fc_enable_generic - Enable flow control
1581 * @hw: pointer to hardware structure 1584 * @hw: pointer to hardware structure
1582 * @packetbuf_num: packet buffer number (0-7) 1585 * @packetbuf_num: packet buffer number (0-7)
1583 * 1586 *
1584 * Enable flow control according to the current settings. 1587 * Enable flow control according to the current settings.
1585 **/ 1588 **/
1586s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num) 1589s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1587{ 1590{
1588 s32 ret_val = 0; 1591 s32 ret_val = 0;
1589 u32 mflcn_reg; 1592 u32 mflcn_reg, fccfg_reg;
1590 u32 fccfg_reg;
1591 u32 reg; 1593 u32 reg;
1592 u32 rx_pba_size; 1594 u32 rx_pba_size;
1593 1595
@@ -1596,7 +1598,12 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
1596 goto out; 1598 goto out;
1597 1599
1598#endif /* CONFIG_DCB */ 1600#endif /* CONFIG_DCB */
1601 /* Negotiate the fc mode to use */
1602 ret_val = ixgbe_fc_autoneg(hw);
1603 if (ret_val)
1604 goto out;
1599 1605
1606 /* Disable any previous flow control settings */
1600 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 1607 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1601 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 1608 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1602 1609
@@ -1616,7 +1623,10 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
1616 */ 1623 */
1617 switch (hw->fc.current_mode) { 1624 switch (hw->fc.current_mode) {
1618 case ixgbe_fc_none: 1625 case ixgbe_fc_none:
1619 /* Flow control completely disabled by software override. */ 1626 /*
1627 * Flow control is disabled by software override or autoneg.
1628 * The code below will actually disable it in the HW.
1629 */
1620 break; 1630 break;
1621 case ixgbe_fc_rx_pause: 1631 case ixgbe_fc_rx_pause:
1622 /* 1632 /*
@@ -1645,7 +1655,7 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
1645 case ixgbe_fc_pfc: 1655 case ixgbe_fc_pfc:
1646 goto out; 1656 goto out;
1647 break; 1657 break;
1648#endif 1658#endif /* CONFIG_DCB */
1649 default: 1659 default:
1650 hw_dbg(hw, "Flow control param set incorrectly\n"); 1660 hw_dbg(hw, "Flow control param set incorrectly\n");
1651 ret_val = -IXGBE_ERR_CONFIG; 1661 ret_val = -IXGBE_ERR_CONFIG;
@@ -1653,7 +1663,7 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
1653 break; 1663 break;
1654 } 1664 }
1655 1665
1656 /* Enable 802.3x based flow control settings. */ 1666 /* Set 802.3x based flow control settings. */
1657 mflcn_reg |= IXGBE_MFLCN_DPF; 1667 mflcn_reg |= IXGBE_MFLCN_DPF;
1658 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 1668 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1659 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 1669 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
@@ -1661,10 +1671,12 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
1661 reg = IXGBE_READ_REG(hw, IXGBE_MTQC); 1671 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1662 /* Thresholds are different for link flow control when in DCB mode */ 1672 /* Thresholds are different for link flow control when in DCB mode */
1663 if (reg & IXGBE_MTQC_RT_ENA) { 1673 if (reg & IXGBE_MTQC_RT_ENA) {
1674 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1675
1664 /* Always disable XON for LFC when in DCB mode */ 1676 /* Always disable XON for LFC when in DCB mode */
1665 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), 0); 1677 reg = (rx_pba_size >> 5) & 0xFFE0;
1678 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
1666 1679
1667 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1668 reg = (rx_pba_size >> 2) & 0xFFE0; 1680 reg = (rx_pba_size >> 2) & 0xFFE0;
1669 if (hw->fc.current_mode & ixgbe_fc_tx_pause) 1681 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1670 reg |= IXGBE_FCRTH_FCEN; 1682 reg |= IXGBE_FCRTH_FCEN;
@@ -1709,100 +1721,41 @@ out:
1709 * ixgbe_fc_autoneg - Configure flow control 1721 * ixgbe_fc_autoneg - Configure flow control
1710 * @hw: pointer to hardware structure 1722 * @hw: pointer to hardware structure
1711 * 1723 *
1712 * Negotiates flow control capabilities with link partner using autoneg and 1724 * Compares our advertised flow control capabilities to those advertised by
1713 * applies the results. 1725 * our link partner, and determines the proper flow control mode to use.
1714 **/ 1726 **/
1715s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 1727s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1716{ 1728{
1717 s32 ret_val = 0; 1729 s32 ret_val = 0;
1718 u32 i, reg, pcs_anadv_reg, pcs_lpab_reg; 1730 ixgbe_link_speed speed;
1719 1731 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1720 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1732 bool link_up;
1721 1733
1722 /* 1734 /*
1723 * The possible values of fc.current_mode are: 1735 * AN should have completed when the cable was plugged in.
1724 * 0: Flow control is completely disabled 1736 * Look for reasons to bail out. Bail out if:
1725 * 1: Rx flow control is enabled (we can receive pause frames, 1737 * - FC autoneg is disabled, or if
1726 * but not send pause frames). 1738 * - we don't have multispeed fiber, or if
1727 * 2: Tx flow control is enabled (we can send pause frames but 1739 * - we're not running at 1G, or if
1728 * we do not support receiving pause frames). 1740 * - link is not up, or if
1729 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1741 * - link is up but AN did not complete, or if
1730 * 4: Priority Flow Control is enabled. 1742 * - link is up and AN completed but timed out
1731 * other: Invalid. 1743 *
1744 * Since we're being called from an LSC, link is already know to be up.
1745 * So use link_up_wait_to_complete=false.
1732 */ 1746 */
1733 switch (hw->fc.current_mode) { 1747 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1734 case ixgbe_fc_none: 1748 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1735 /* Flow control completely disabled by software override. */ 1749
1736 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 1750 if (hw->fc.disable_fc_autoneg ||
1737 break; 1751 !hw->phy.multispeed_fiber ||
1738 case ixgbe_fc_rx_pause: 1752 (speed != IXGBE_LINK_SPEED_1GB_FULL) ||
1739 /* 1753 !link_up ||
1740 * Rx Flow control is enabled and Tx Flow control is 1754 ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1741 * disabled by software override. Since there really 1755 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1742 * isn't a way to advertise that we are capable of RX 1756 hw->fc.fc_was_autonegged = false;
1743 * Pause ONLY, we will advertise that we support both 1757 hw->fc.current_mode = hw->fc.requested_mode;
1744 * symmetric and asymmetric Rx PAUSE. Later, we will 1758 hw_dbg(hw, "Autoneg FC was skipped.\n");
1745 * disable the adapter's ability to send PAUSE frames.
1746 */
1747 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1748 break;
1749 case ixgbe_fc_tx_pause:
1750 /*
1751 * Tx Flow control is enabled, and Rx Flow control is
1752 * disabled by software override.
1753 */
1754 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1755 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1756 break;
1757 case ixgbe_fc_full:
1758 /* Flow control (both Rx and Tx) is enabled by SW override. */
1759 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1760 break;
1761#ifdef CONFIG_DCB
1762 case ixgbe_fc_pfc:
1763 goto out;
1764 break;
1765#endif
1766 default:
1767 hw_dbg(hw, "Flow control param set incorrectly\n");
1768 ret_val = -IXGBE_ERR_CONFIG;
1769 goto out;
1770 break;
1771 }
1772
1773 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1774 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
1775
1776 /* Set PCS register for autoneg */
1777 /* Enable and restart autoneg */
1778 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
1779
1780 /* Disable AN timeout */
1781 if (hw->fc.strict_ieee)
1782 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1783
1784 hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1785 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1786
1787 /* See if autonegotiation has succeeded */
1788 hw->mac.autoneg_succeeded = 0;
1789 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1790 msleep(10);
1791 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1792 if ((reg & (IXGBE_PCS1GLSTA_LINK_OK |
1793 IXGBE_PCS1GLSTA_AN_COMPLETE)) ==
1794 (IXGBE_PCS1GLSTA_LINK_OK |
1795 IXGBE_PCS1GLSTA_AN_COMPLETE)) {
1796 if (!(reg & IXGBE_PCS1GLSTA_AN_TIMED_OUT))
1797 hw->mac.autoneg_succeeded = 1;
1798 break;
1799 }
1800 }
1801
1802 if (!hw->mac.autoneg_succeeded) {
1803 /* Autoneg failed to achieve a link, so we turn fc off */
1804 hw->fc.current_mode = ixgbe_fc_none;
1805 hw_dbg(hw, "Flow Control = NONE.\n");
1806 goto out; 1759 goto out;
1807 } 1760 }
1808 1761
@@ -1845,21 +1798,23 @@ s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1845 hw_dbg(hw, "Flow Control = NONE.\n"); 1798 hw_dbg(hw, "Flow Control = NONE.\n");
1846 } 1799 }
1847 1800
1801 /* Record that current_mode is the result of a successful autoneg */
1802 hw->fc.fc_was_autonegged = true;
1803
1848out: 1804out:
1849 return ret_val; 1805 return ret_val;
1850} 1806}
1851 1807
1852/** 1808/**
1853 * ixgbe_setup_fc_generic - Set up flow control 1809 * ixgbe_setup_fc - Set up flow control
1854 * @hw: pointer to hardware structure 1810 * @hw: pointer to hardware structure
1855 * 1811 *
1856 * Sets up flow control. 1812 * Called at init time to set up flow control.
1857 **/ 1813 **/
1858s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1814s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
1859{ 1815{
1860 s32 ret_val = 0; 1816 s32 ret_val = 0;
1861 ixgbe_link_speed speed; 1817 u32 reg;
1862 bool link_up;
1863 1818
1864#ifdef CONFIG_DCB 1819#ifdef CONFIG_DCB
1865 if (hw->fc.requested_mode == ixgbe_fc_pfc) { 1820 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
@@ -1881,16 +1836,14 @@ s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1881 * because it causes the controller to just blast out fc packets. 1836 * because it causes the controller to just blast out fc packets.
1882 */ 1837 */
1883 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 1838 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1884 if (hw->fc.requested_mode != ixgbe_fc_none) { 1839 hw_dbg(hw, "Invalid water mark configuration\n");
1885 hw_dbg(hw, "Invalid water mark configuration\n"); 1840 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1886 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 1841 goto out;
1887 goto out;
1888 }
1889 } 1842 }
1890 1843
1891 /* 1844 /*
1892 * Validate the requested mode. Strict IEEE mode does not allow 1845 * Validate the requested mode. Strict IEEE mode does not allow
1893 * ixgbe_fc_rx_pause because it will cause testing anomalies. 1846 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
1894 */ 1847 */
1895 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 1848 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1896 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict " 1849 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
@@ -1907,21 +1860,77 @@ s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1907 hw->fc.requested_mode = ixgbe_fc_full; 1860 hw->fc.requested_mode = ixgbe_fc_full;
1908 1861
1909 /* 1862 /*
1910 * Save off the requested flow control mode for use later. Depending 1863 * Set up the 1G flow control advertisement registers so the HW will be
1911 * on the link partner's capabilities, we may or may not use this mode. 1864 * able to do fc autoneg once the cable is plugged in. If we end up
1865 * using 10g instead, this is harmless.
1912 */ 1866 */
1913 hw->fc.current_mode = hw->fc.requested_mode; 1867 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1914
1915 /* Decide whether to use autoneg or not. */
1916 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1917 if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
1918 (speed == IXGBE_LINK_SPEED_1GB_FULL))
1919 ret_val = ixgbe_fc_autoneg(hw);
1920 1868
1921 if (ret_val) 1869 /*
1870 * The possible values of fc.requested_mode are:
1871 * 0: Flow control is completely disabled
1872 * 1: Rx flow control is enabled (we can receive pause frames,
1873 * but not send pause frames).
1874 * 2: Tx flow control is enabled (we can send pause frames but
1875 * we do not support receiving pause frames).
1876 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1877#ifdef CONFIG_DCB
1878 * 4: Priority Flow Control is enabled.
1879#endif
1880 * other: Invalid.
1881 */
1882 switch (hw->fc.requested_mode) {
1883 case ixgbe_fc_none:
1884 /* Flow control completely disabled by software override. */
1885 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1886 break;
1887 case ixgbe_fc_rx_pause:
1888 /*
1889 * Rx Flow control is enabled and Tx Flow control is
1890 * disabled by software override. Since there really
1891 * isn't a way to advertise that we are capable of RX
1892 * Pause ONLY, we will advertise that we support both
1893 * symmetric and asymmetric Rx PAUSE. Later, we will
1894 * disable the adapter's ability to send PAUSE frames.
1895 */
1896 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1897 break;
1898 case ixgbe_fc_tx_pause:
1899 /*
1900 * Tx Flow control is enabled, and Rx Flow control is
1901 * disabled by software override.
1902 */
1903 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1904 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1905 break;
1906 case ixgbe_fc_full:
1907 /* Flow control (both Rx and Tx) is enabled by SW override. */
1908 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1909 break;
1910#ifdef CONFIG_DCB
1911 case ixgbe_fc_pfc:
1922 goto out; 1912 goto out;
1913 break;
1914#endif /* CONFIG_DCB */
1915 default:
1916 hw_dbg(hw, "Flow control param set incorrectly\n");
1917 ret_val = -IXGBE_ERR_CONFIG;
1918 goto out;
1919 break;
1920 }
1921
1922 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1923 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
1923 1924
1924 ret_val = ixgbe_fc_enable(hw, packetbuf_num); 1925 /* Enable and restart autoneg to inform the link partner */
1926 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
1927
1928 /* Disable AN timeout */
1929 if (hw->fc.strict_ieee)
1930 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1931
1932 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1933 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
1925 1934
1926out: 1935out:
1927 return ret_val; 1936 return ret_val;