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authorBen Hutchings <bhutchings@solarflare.com>2009-04-29 04:08:58 -0400
committerDavid S. Miller <davem@davemloft.net>2009-04-29 20:32:33 -0400
commit6b73e10d2d89f9ce773f9b47d61b195936d059ba (patch)
tree108a5d6ad55cb795d6afb0e0846c6782f42f5c90 /drivers/net/ixgbe/ixgbe_82598.c
parent0f07c4ee8c800923ae7918c231532a9256233eed (diff)
ixgbe: Use generic MDIO definitions and functions
Compile-tested only. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_82598.c')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c33
1 files changed, 16 insertions, 17 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 03eb54f4f1cc..e051964347e4 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -229,14 +229,13 @@ static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
229 *speed = 0; 229 *speed = 0;
230 *autoneg = true; 230 *autoneg = true;
231 231
232 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 232 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
233 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
234 &speed_ability); 233 &speed_ability);
235 234
236 if (status == 0) { 235 if (status == 0) {
237 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 236 if (speed_ability & MDIO_SPEED_10G)
238 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 237 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
239 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 238 if (speed_ability & MDIO_PMA_SPEED_1000)
240 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 239 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
241 } 240 }
242 241
@@ -526,9 +525,9 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
526 * clear indicates active; set indicates inactive. 525 * clear indicates active; set indicates inactive.
527 */ 526 */
528 if (hw->phy.type == ixgbe_phy_nl) { 527 if (hw->phy.type == ixgbe_phy_nl) {
529 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 528 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
530 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); 529 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
531 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, 530 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
532 &adapt_comp_reg); 531 &adapt_comp_reg);
533 if (link_up_wait_to_complete) { 532 if (link_up_wait_to_complete) {
534 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 533 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
@@ -541,10 +540,10 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
541 } 540 }
542 msleep(100); 541 msleep(100);
543 hw->phy.ops.read_reg(hw, 0xC79F, 542 hw->phy.ops.read_reg(hw, 0xC79F,
544 IXGBE_TWINAX_DEV, 543 MDIO_MMD_PMAPMD,
545 &link_reg); 544 &link_reg);
546 hw->phy.ops.read_reg(hw, 0xC00C, 545 hw->phy.ops.read_reg(hw, 0xC00C,
547 IXGBE_TWINAX_DEV, 546 MDIO_MMD_PMAPMD,
548 &adapt_comp_reg); 547 &adapt_comp_reg);
549 } 548 }
550 } else { 549 } else {
@@ -990,14 +989,14 @@ static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
990 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); 989 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
991 hw->phy.ops.write_reg(hw, 990 hw->phy.ops.write_reg(hw,
992 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, 991 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
993 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 992 MDIO_MMD_PMAPMD,
994 sfp_addr); 993 sfp_addr);
995 994
996 /* Poll status */ 995 /* Poll status */
997 for (i = 0; i < 100; i++) { 996 for (i = 0; i < 100; i++) {
998 hw->phy.ops.read_reg(hw, 997 hw->phy.ops.read_reg(hw,
999 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, 998 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1000 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 999 MDIO_MMD_PMAPMD,
1001 &sfp_stat); 1000 &sfp_stat);
1002 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; 1001 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1003 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) 1002 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
@@ -1013,7 +1012,7 @@ static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1013 1012
1014 /* Read data */ 1013 /* Read data */
1015 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, 1014 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1016 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); 1015 MDIO_MMD_PMAPMD, &sfp_data);
1017 1016
1018 *eeprom_data = (u8)(sfp_data >> 8); 1017 *eeprom_data = (u8)(sfp_data >> 8);
1019 } else { 1018 } else {
@@ -1045,13 +1044,13 @@ static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1045 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */ 1044 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1046 if (hw->phy.type == ixgbe_phy_tn || 1045 if (hw->phy.type == ixgbe_phy_tn ||
1047 hw->phy.type == ixgbe_phy_cu_unknown) { 1046 hw->phy.type == ixgbe_phy_cu_unknown) {
1048 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1047 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1049 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1048 &ext_ability);
1050 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1049 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1051 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1050 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1052 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1051 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1053 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1052 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1054 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1053 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1055 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1054 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1056 goto out; 1055 goto out;
1057 } 1056 }