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authorJesse Brandeburg <jesse.brandeburg@intel.com>2008-07-08 18:51:17 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-07-11 01:20:27 -0400
commit4360386f7d849f521e8ef042f90dbca73e07509c (patch)
tree874ef11dcb9ba00dd03013e0d3d30ae6bcc38c88 /drivers/net/ixgb/ixgb_main.c
parente539e4667e3c8125641f5916eb0b7d087d3e0844 (diff)
ixgb: fix bug in descriptor ring due to prefetch corruption
there was one more bug hidden in the prefetch routines in ixgb hardware that force us to remove it completely. Writebacks were being done on descriptors with stale data due to internal hardware fifo corruption. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/ixgb/ixgb_main.c')
-rw-r--r--drivers/net/ixgb/ixgb_main.c27
1 files changed, 6 insertions, 21 deletions
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c
index 652c0eab3a4a..ecd5252c4bf4 100644
--- a/drivers/net/ixgb/ixgb_main.c
+++ b/drivers/net/ixgb/ixgb_main.c
@@ -146,14 +146,6 @@ static int debug = DEFAULT_DEBUG_LEVEL_SHIFT;
146module_param(debug, int, 0); 146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148 148
149/* some defines for controlling descriptor fetches in h/w */
150#define RXDCTL_WTHRESH_DEFAULT 15 /* chip writes back at this many or RXT0 */
151#define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below
152 * this */
153#define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail
154 * is pushed this many descriptors
155 * from head */
156
157/** 149/**
158 * ixgb_init_module - Driver Registration Routine 150 * ixgb_init_module - Driver Registration Routine
159 * 151 *
@@ -839,7 +831,6 @@ ixgb_configure_rx(struct ixgb_adapter *adapter)
839 struct ixgb_hw *hw = &adapter->hw; 831 struct ixgb_hw *hw = &adapter->hw;
840 u32 rctl; 832 u32 rctl;
841 u32 rxcsum; 833 u32 rxcsum;
842 u32 rxdctl;
843 834
844 /* make sure receives are disabled while setting up the descriptors */ 835 /* make sure receives are disabled while setting up the descriptors */
845 836
@@ -861,18 +852,12 @@ ixgb_configure_rx(struct ixgb_adapter *adapter)
861 IXGB_WRITE_REG(hw, RDH, 0); 852 IXGB_WRITE_REG(hw, RDH, 0);
862 IXGB_WRITE_REG(hw, RDT, 0); 853 IXGB_WRITE_REG(hw, RDT, 0);
863 854
864 /* set up pre-fetching of receive buffers so we get some before we 855 /* due to the hardware errata with RXDCTL, we are unable to use any of
865 * run out (default hardware behavior is to run out before fetching 856 * the performance enhancing features of it without causing other
866 * more). This sets up to fetch if HTHRESH rx descriptors are avail 857 * subtle bugs, some of the bugs could include receive length
867 * and the descriptors in hw cache are below PTHRESH. This avoids 858 * corruption at high data rates (WTHRESH > 0) and/or receive
868 * the hardware behavior of fetching <=512 descriptors in a single 859 * descriptor ring irregularites (particularly in hardware cache) */
869 * burst that pre-empts all other activity, usually causing fifo 860 IXGB_WRITE_REG(hw, RXDCTL, 0);
870 * overflows. */
871 /* use WTHRESH to burst write 16 descriptors or burst when RXT0 */
872 rxdctl = RXDCTL_WTHRESH_DEFAULT << IXGB_RXDCTL_WTHRESH_SHIFT |
873 RXDCTL_HTHRESH_DEFAULT << IXGB_RXDCTL_HTHRESH_SHIFT |
874 RXDCTL_PTHRESH_DEFAULT << IXGB_RXDCTL_PTHRESH_SHIFT;
875 IXGB_WRITE_REG(hw, RXDCTL, rxdctl);
876 861
877 /* Enable Receive Checksum Offload for TCP and UDP */ 862 /* Enable Receive Checksum Offload for TCP and UDP */
878 if (adapter->rx_csum) { 863 if (adapter->rx_csum) {