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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/ixgb/ixgb_hw.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/ixgb/ixgb_hw.c')
-rw-r--r--drivers/net/ixgb/ixgb_hw.c1202
1 files changed, 1202 insertions, 0 deletions
diff --git a/drivers/net/ixgb/ixgb_hw.c b/drivers/net/ixgb/ixgb_hw.c
new file mode 100644
index 000000000000..69329c73095a
--- /dev/null
+++ b/drivers/net/ixgb/ixgb_hw.c
@@ -0,0 +1,1202 @@
1/*******************************************************************************
2
3
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ixgb_hw.c
30 * Shared functions for accessing and configuring the adapter
31 */
32
33#include "ixgb_hw.h"
34#include "ixgb_ids.h"
35
36/* Local function prototypes */
37
38static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t * mc_addr);
39
40static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
41
42static void ixgb_get_bus_info(struct ixgb_hw *hw);
43
44static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
45
46static void ixgb_optics_reset(struct ixgb_hw *hw);
47
48static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
49
50uint32_t ixgb_mac_reset(struct ixgb_hw *hw);
51
52uint32_t ixgb_mac_reset(struct ixgb_hw *hw)
53{
54 uint32_t ctrl_reg;
55
56 ctrl_reg = IXGB_CTRL0_RST |
57 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
58 IXGB_CTRL0_SDP2_DIR |
59 IXGB_CTRL0_SDP1_DIR |
60 IXGB_CTRL0_SDP0_DIR |
61 IXGB_CTRL0_SDP3 | /* Initial value 1101 */
62 IXGB_CTRL0_SDP2 |
63 IXGB_CTRL0_SDP0;
64
65#ifdef HP_ZX1
66 /* Workaround for 82597EX reset errata */
67 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
68#else
69 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
70#endif
71
72 /* Delay a few ms just to allow the reset to complete */
73 msec_delay(IXGB_DELAY_AFTER_RESET);
74 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
75#ifdef DBG
76 /* Make sure the self-clearing global reset bit did self clear */
77 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
78#endif
79
80 if (hw->phy_type == ixgb_phy_type_txn17401) {
81 ixgb_optics_reset(hw);
82 }
83
84 return ctrl_reg;
85}
86
87/******************************************************************************
88 * Reset the transmit and receive units; mask and clear all interrupts.
89 *
90 * hw - Struct containing variables accessed by shared code
91 *****************************************************************************/
92boolean_t
93ixgb_adapter_stop(struct ixgb_hw *hw)
94{
95 uint32_t ctrl_reg;
96 uint32_t icr_reg;
97
98 DEBUGFUNC("ixgb_adapter_stop");
99
100 /* If we are stopped or resetting exit gracefully and wait to be
101 * started again before accessing the hardware.
102 */
103 if(hw->adapter_stopped) {
104 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
105 return FALSE;
106 }
107
108 /* Set the Adapter Stopped flag so other driver functions stop
109 * touching the Hardware.
110 */
111 hw->adapter_stopped = TRUE;
112
113 /* Clear interrupt mask to stop board from generating interrupts */
114 DEBUGOUT("Masking off all interrupts\n");
115 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
116
117 /* Disable the Transmit and Receive units. Then delay to allow
118 * any pending transactions to complete before we hit the MAC with
119 * the global reset.
120 */
121 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
122 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
123 msec_delay(IXGB_DELAY_BEFORE_RESET);
124
125 /* Issue a global reset to the MAC. This will reset the chip's
126 * transmit, receive, DMA, and link units. It will not effect
127 * the current PCI configuration. The global reset bit is self-
128 * clearing, and should clear within a microsecond.
129 */
130 DEBUGOUT("Issuing a global reset to MAC\n");
131
132 ctrl_reg = ixgb_mac_reset(hw);
133
134 /* Clear interrupt mask to stop board from generating interrupts */
135 DEBUGOUT("Masking off all interrupts\n");
136 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
137
138 /* Clear any pending interrupt events. */
139 icr_reg = IXGB_READ_REG(hw, ICR);
140
141 return (ctrl_reg & IXGB_CTRL0_RST);
142}
143
144
145/******************************************************************************
146 * Identifies the vendor of the optics module on the adapter. The SR adapters
147 * support two different types of XPAK optics, so it is necessary to determine
148 * which optics are present before applying any optics-specific workarounds.
149 *
150 * hw - Struct containing variables accessed by shared code.
151 *
152 * Returns: the vendor of the XPAK optics module.
153 *****************************************************************************/
154static ixgb_xpak_vendor
155ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
156{
157 uint32_t i;
158 uint16_t vendor_name[5];
159 ixgb_xpak_vendor xpak_vendor;
160
161 DEBUGFUNC("ixgb_identify_xpak_vendor");
162
163 /* Read the first few bytes of the vendor string from the XPAK NVR
164 * registers. These are standard XENPAK/XPAK registers, so all XPAK
165 * devices should implement them. */
166 for (i = 0; i < 5; i++) {
167 vendor_name[i] = ixgb_read_phy_reg(hw,
168 MDIO_PMA_PMD_XPAK_VENDOR_NAME
169 + i, IXGB_PHY_ADDRESS,
170 MDIO_PMA_PMD_DID);
171 }
172
173 /* Determine the actual vendor */
174 if (vendor_name[0] == 'I' &&
175 vendor_name[1] == 'N' &&
176 vendor_name[2] == 'T' &&
177 vendor_name[3] == 'E' && vendor_name[4] == 'L') {
178 xpak_vendor = ixgb_xpak_vendor_intel;
179 } else {
180 xpak_vendor = ixgb_xpak_vendor_infineon;
181 }
182
183 return (xpak_vendor);
184}
185
186/******************************************************************************
187 * Determine the physical layer module on the adapter.
188 *
189 * hw - Struct containing variables accessed by shared code. The device_id
190 * field must be (correctly) populated before calling this routine.
191 *
192 * Returns: the phy type of the adapter.
193 *****************************************************************************/
194static ixgb_phy_type
195ixgb_identify_phy(struct ixgb_hw *hw)
196{
197 ixgb_phy_type phy_type;
198 ixgb_xpak_vendor xpak_vendor;
199
200 DEBUGFUNC("ixgb_identify_phy");
201
202 /* Infer the transceiver/phy type from the device id */
203 switch (hw->device_id) {
204 case IXGB_DEVICE_ID_82597EX:
205 DEBUGOUT("Identified TXN17401 optics\n");
206 phy_type = ixgb_phy_type_txn17401;
207 break;
208
209 case IXGB_DEVICE_ID_82597EX_SR:
210 /* The SR adapters carry two different types of XPAK optics
211 * modules; read the vendor identifier to determine the exact
212 * type of optics. */
213 xpak_vendor = ixgb_identify_xpak_vendor(hw);
214 if (xpak_vendor == ixgb_xpak_vendor_intel) {
215 DEBUGOUT("Identified TXN17201 optics\n");
216 phy_type = ixgb_phy_type_txn17201;
217 } else {
218 DEBUGOUT("Identified G6005 optics\n");
219 phy_type = ixgb_phy_type_g6005;
220 }
221 break;
222 case IXGB_DEVICE_ID_82597EX_LR:
223 DEBUGOUT("Identified G6104 optics\n");
224 phy_type = ixgb_phy_type_g6104;
225 break;
226 default:
227 DEBUGOUT("Unknown physical layer module\n");
228 phy_type = ixgb_phy_type_unknown;
229 break;
230 }
231
232 return (phy_type);
233}
234
235/******************************************************************************
236 * Performs basic configuration of the adapter.
237 *
238 * hw - Struct containing variables accessed by shared code
239 *
240 * Resets the controller.
241 * Reads and validates the EEPROM.
242 * Initializes the receive address registers.
243 * Initializes the multicast table.
244 * Clears all on-chip counters.
245 * Calls routine to setup flow control settings.
246 * Leaves the transmit and receive units disabled and uninitialized.
247 *
248 * Returns:
249 * TRUE if successful,
250 * FALSE if unrecoverable problems were encountered.
251 *****************************************************************************/
252boolean_t
253ixgb_init_hw(struct ixgb_hw *hw)
254{
255 uint32_t i;
256 uint32_t ctrl_reg;
257 boolean_t status;
258
259 DEBUGFUNC("ixgb_init_hw");
260
261 /* Issue a global reset to the MAC. This will reset the chip's
262 * transmit, receive, DMA, and link units. It will not effect
263 * the current PCI configuration. The global reset bit is self-
264 * clearing, and should clear within a microsecond.
265 */
266 DEBUGOUT("Issuing a global reset to MAC\n");
267
268 ctrl_reg = ixgb_mac_reset(hw);
269
270 DEBUGOUT("Issuing an EE reset to MAC\n");
271#ifdef HP_ZX1
272 /* Workaround for 82597EX reset errata */
273 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
274#else
275 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
276#endif
277
278 /* Delay a few ms just to allow the reset to complete */
279 msec_delay(IXGB_DELAY_AFTER_EE_RESET);
280
281 if (ixgb_get_eeprom_data(hw) == FALSE) {
282 return(FALSE);
283 }
284
285 /* Use the device id to determine the type of phy/transceiver. */
286 hw->device_id = ixgb_get_ee_device_id(hw);
287 hw->phy_type = ixgb_identify_phy(hw);
288
289 /* Setup the receive addresses.
290 * Receive Address Registers (RARs 0 - 15).
291 */
292 ixgb_init_rx_addrs(hw);
293
294 /*
295 * Check that a valid MAC address has been set.
296 * If it is not valid, we fail hardware init.
297 */
298 if (!mac_addr_valid(hw->curr_mac_addr)) {
299 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
300 return(FALSE);
301 }
302
303 /* tell the routines in this file they can access hardware again */
304 hw->adapter_stopped = FALSE;
305
306 /* Fill in the bus_info structure */
307 ixgb_get_bus_info(hw);
308
309 /* Zero out the Multicast HASH table */
310 DEBUGOUT("Zeroing the MTA\n");
311 for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
312 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
313
314 /* Zero out the VLAN Filter Table Array */
315 ixgb_clear_vfta(hw);
316
317 /* Zero all of the hardware counters */
318 ixgb_clear_hw_cntrs(hw);
319
320 /* Call a subroutine to setup flow control. */
321 status = ixgb_setup_fc(hw);
322
323 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
324 ixgb_check_for_link(hw);
325
326 return (status);
327}
328
329/******************************************************************************
330 * Initializes receive address filters.
331 *
332 * hw - Struct containing variables accessed by shared code
333 *
334 * Places the MAC address in receive address register 0 and clears the rest
335 * of the receive addresss registers. Clears the multicast table. Assumes
336 * the receiver is in reset when the routine is called.
337 *****************************************************************************/
338void
339ixgb_init_rx_addrs(struct ixgb_hw *hw)
340{
341 uint32_t i;
342
343 DEBUGFUNC("ixgb_init_rx_addrs");
344
345 /*
346 * If the current mac address is valid, assume it is a software override
347 * to the permanent address.
348 * Otherwise, use the permanent address from the eeprom.
349 */
350 if (!mac_addr_valid(hw->curr_mac_addr)) {
351
352 /* Get the MAC address from the eeprom for later reference */
353 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
354
355 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
356 hw->curr_mac_addr[0],
357 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
358 DEBUGOUT3("%.2X %.2X %.2X\n",
359 hw->curr_mac_addr[3],
360 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
361 } else {
362
363 /* Setup the receive address. */
364 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
365 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
366 hw->curr_mac_addr[0],
367 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
368 DEBUGOUT3("%.2X %.2X %.2X\n",
369 hw->curr_mac_addr[3],
370 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
371
372 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
373 }
374
375 /* Zero out the other 15 receive addresses. */
376 DEBUGOUT("Clearing RAR[1-15]\n");
377 for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
378 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
379 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
380 }
381
382 return;
383}
384
385/******************************************************************************
386 * Updates the MAC's list of multicast addresses.
387 *
388 * hw - Struct containing variables accessed by shared code
389 * mc_addr_list - the list of new multicast addresses
390 * mc_addr_count - number of addresses
391 * pad - number of bytes between addresses in the list
392 *
393 * The given list replaces any existing list. Clears the last 15 receive
394 * address registers and the multicast table. Uses receive address registers
395 * for the first 15 multicast addresses, and hashes the rest into the
396 * multicast table.
397 *****************************************************************************/
398void
399ixgb_mc_addr_list_update(struct ixgb_hw *hw,
400 uint8_t *mc_addr_list,
401 uint32_t mc_addr_count,
402 uint32_t pad)
403{
404 uint32_t hash_value;
405 uint32_t i;
406 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
407
408 DEBUGFUNC("ixgb_mc_addr_list_update");
409
410 /* Set the new number of MC addresses that we are being requested to use. */
411 hw->num_mc_addrs = mc_addr_count;
412
413 /* Clear RAR[1-15] */
414 DEBUGOUT(" Clearing RAR[1-15]\n");
415 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
416 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
417 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
418 }
419
420 /* Clear the MTA */
421 DEBUGOUT(" Clearing MTA\n");
422 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
423 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
424 }
425
426 /* Add the new addresses */
427 for(i = 0; i < mc_addr_count; i++) {
428 DEBUGOUT(" Adding the multicast addresses:\n");
429 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
430 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
431 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
432 1],
433 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
434 2],
435 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
436 3],
437 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
438 4],
439 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
440 5]);
441
442 /* Place this multicast address in the RAR if there is room, *
443 * else put it in the MTA
444 */
445 if(rar_used_count < IXGB_RAR_ENTRIES) {
446 ixgb_rar_set(hw,
447 mc_addr_list +
448 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
449 rar_used_count);
450 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
451 rar_used_count++;
452 } else {
453 hash_value = ixgb_hash_mc_addr(hw,
454 mc_addr_list +
455 (i *
456 (IXGB_ETH_LENGTH_OF_ADDRESS
457 + pad)));
458
459 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
460
461 ixgb_mta_set(hw, hash_value);
462 }
463 }
464
465 DEBUGOUT("MC Update Complete\n");
466 return;
467}
468
469/******************************************************************************
470 * Hashes an address to determine its location in the multicast table
471 *
472 * hw - Struct containing variables accessed by shared code
473 * mc_addr - the multicast address to hash
474 *
475 * Returns:
476 * The hash value
477 *****************************************************************************/
478static uint32_t
479ixgb_hash_mc_addr(struct ixgb_hw *hw,
480 uint8_t *mc_addr)
481{
482 uint32_t hash_value = 0;
483
484 DEBUGFUNC("ixgb_hash_mc_addr");
485
486 /* The portion of the address that is used for the hash table is
487 * determined by the mc_filter_type setting.
488 */
489 switch (hw->mc_filter_type) {
490 /* [0] [1] [2] [3] [4] [5]
491 * 01 AA 00 12 34 56
492 * LSB MSB - According to H/W docs */
493 case 0:
494 /* [47:36] i.e. 0x563 for above example address */
495 hash_value =
496 ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
497 break;
498 case 1: /* [46:35] i.e. 0xAC6 for above example address */
499 hash_value =
500 ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
501 break;
502 case 2: /* [45:34] i.e. 0x5D8 for above example address */
503 hash_value =
504 ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
505 break;
506 case 3: /* [43:32] i.e. 0x634 for above example address */
507 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
508 break;
509 default:
510 /* Invalid mc_filter_type, what should we do? */
511 DEBUGOUT("MC filter type param set incorrectly\n");
512 ASSERT(0);
513 break;
514 }
515
516 hash_value &= 0xFFF;
517 return (hash_value);
518}
519
520/******************************************************************************
521 * Sets the bit in the multicast table corresponding to the hash value.
522 *
523 * hw - Struct containing variables accessed by shared code
524 * hash_value - Multicast address hash value
525 *****************************************************************************/
526static void
527ixgb_mta_set(struct ixgb_hw *hw,
528 uint32_t hash_value)
529{
530 uint32_t hash_bit, hash_reg;
531 uint32_t mta_reg;
532
533 /* The MTA is a register array of 128 32-bit registers.
534 * It is treated like an array of 4096 bits. We want to set
535 * bit BitArray[hash_value]. So we figure out what register
536 * the bit is in, read it, OR in the new bit, then write
537 * back the new value. The register is determined by the
538 * upper 7 bits of the hash value and the bit within that
539 * register are determined by the lower 5 bits of the value.
540 */
541 hash_reg = (hash_value >> 5) & 0x7F;
542 hash_bit = hash_value & 0x1F;
543
544 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
545
546 mta_reg |= (1 << hash_bit);
547
548 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
549
550 return;
551}
552
553/******************************************************************************
554 * Puts an ethernet address into a receive address register.
555 *
556 * hw - Struct containing variables accessed by shared code
557 * addr - Address to put into receive address register
558 * index - Receive address register to write
559 *****************************************************************************/
560void
561ixgb_rar_set(struct ixgb_hw *hw,
562 uint8_t *addr,
563 uint32_t index)
564{
565 uint32_t rar_low, rar_high;
566
567 DEBUGFUNC("ixgb_rar_set");
568
569 /* HW expects these in little endian so we reverse the byte order
570 * from network order (big endian) to little endian
571 */
572 rar_low = ((uint32_t) addr[0] |
573 ((uint32_t)addr[1] << 8) |
574 ((uint32_t)addr[2] << 16) |
575 ((uint32_t)addr[3] << 24));
576
577 rar_high = ((uint32_t) addr[4] |
578 ((uint32_t)addr[5] << 8) |
579 IXGB_RAH_AV);
580
581 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
582 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
583 return;
584}
585
586/******************************************************************************
587 * Writes a value to the specified offset in the VLAN filter table.
588 *
589 * hw - Struct containing variables accessed by shared code
590 * offset - Offset in VLAN filer table to write
591 * value - Value to write into VLAN filter table
592 *****************************************************************************/
593void
594ixgb_write_vfta(struct ixgb_hw *hw,
595 uint32_t offset,
596 uint32_t value)
597{
598 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
599 return;
600}
601
602/******************************************************************************
603 * Clears the VLAN filer table
604 *
605 * hw - Struct containing variables accessed by shared code
606 *****************************************************************************/
607void
608ixgb_clear_vfta(struct ixgb_hw *hw)
609{
610 uint32_t offset;
611
612 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
613 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
614 return;
615}
616
617/******************************************************************************
618 * Configures the flow control settings based on SW configuration.
619 *
620 * hw - Struct containing variables accessed by shared code
621 *****************************************************************************/
622
623boolean_t
624ixgb_setup_fc(struct ixgb_hw *hw)
625{
626 uint32_t ctrl_reg;
627 uint32_t pap_reg = 0; /* by default, assume no pause time */
628 boolean_t status = TRUE;
629
630 DEBUGFUNC("ixgb_setup_fc");
631
632 /* Get the current control reg 0 settings */
633 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
634
635 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
636 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
637
638 /* The possible values of the "flow_control" parameter are:
639 * 0: Flow control is completely disabled
640 * 1: Rx flow control is enabled (we can receive pause frames
641 * but not send pause frames).
642 * 2: Tx flow control is enabled (we can send pause frames
643 * but we do not support receiving pause frames).
644 * 3: Both Rx and TX flow control (symmetric) are enabled.
645 * other: Invalid.
646 */
647 switch (hw->fc.type) {
648 case ixgb_fc_none: /* 0 */
649 /* Set CMDC bit to disable Rx Flow control */
650 ctrl_reg |= (IXGB_CTRL0_CMDC);
651 break;
652 case ixgb_fc_rx_pause: /* 1 */
653 /* RX Flow control is enabled, and TX Flow control is
654 * disabled.
655 */
656 ctrl_reg |= (IXGB_CTRL0_RPE);
657 break;
658 case ixgb_fc_tx_pause: /* 2 */
659 /* TX Flow control is enabled, and RX Flow control is
660 * disabled, by a software over-ride.
661 */
662 ctrl_reg |= (IXGB_CTRL0_TPE);
663 pap_reg = hw->fc.pause_time;
664 break;
665 case ixgb_fc_full: /* 3 */
666 /* Flow control (both RX and TX) is enabled by a software
667 * over-ride.
668 */
669 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
670 pap_reg = hw->fc.pause_time;
671 break;
672 default:
673 /* We should never get here. The value should be 0-3. */
674 DEBUGOUT("Flow control param set incorrectly\n");
675 ASSERT(0);
676 break;
677 }
678
679 /* Write the new settings */
680 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
681
682 if (pap_reg != 0) {
683 IXGB_WRITE_REG(hw, PAP, pap_reg);
684 }
685
686 /* Set the flow control receive threshold registers. Normally,
687 * these registers will be set to a default threshold that may be
688 * adjusted later by the driver's runtime code. However, if the
689 * ability to transmit pause frames in not enabled, then these
690 * registers will be set to 0.
691 */
692 if(!(hw->fc.type & ixgb_fc_tx_pause)) {
693 IXGB_WRITE_REG(hw, FCRTL, 0);
694 IXGB_WRITE_REG(hw, FCRTH, 0);
695 } else {
696 /* We need to set up the Receive Threshold high and low water
697 * marks as well as (optionally) enabling the transmission of XON
698 * frames. */
699 if(hw->fc.send_xon) {
700 IXGB_WRITE_REG(hw, FCRTL,
701 (hw->fc.low_water | IXGB_FCRTL_XONE));
702 } else {
703 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
704 }
705 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
706 }
707 return (status);
708}
709
710/******************************************************************************
711 * Reads a word from a device over the Management Data Interface (MDI) bus.
712 * This interface is used to manage Physical layer devices.
713 *
714 * hw - Struct containing variables accessed by hw code
715 * reg_address - Offset of device register being read.
716 * phy_address - Address of device on MDI.
717 *
718 * Returns: Data word (16 bits) from MDI device.
719 *
720 * The 82597EX has support for several MDI access methods. This routine
721 * uses the new protocol MDI Single Command and Address Operation.
722 * This requires that first an address cycle command is sent, followed by a
723 * read command.
724 *****************************************************************************/
725uint16_t
726ixgb_read_phy_reg(struct ixgb_hw *hw,
727 uint32_t reg_address,
728 uint32_t phy_address,
729 uint32_t device_type)
730{
731 uint32_t i;
732 uint32_t data;
733 uint32_t command = 0;
734
735 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
736 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
737 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
738
739 /* Setup and write the address cycle command */
740 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
741 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
742 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
743 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
744
745 IXGB_WRITE_REG(hw, MSCA, command);
746
747 /**************************************************************
748 ** Check every 10 usec to see if the address cycle completed
749 ** The COMMAND bit will clear when the operation is complete.
750 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
751 ** from the CPU Write to the Ready bit assertion.
752 **************************************************************/
753
754 for(i = 0; i < 10; i++)
755 {
756 udelay(10);
757
758 command = IXGB_READ_REG(hw, MSCA);
759
760 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
761 break;
762 }
763
764 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
765
766 /* Address cycle complete, setup and write the read command */
767 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
768 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
769 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
770 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
771
772 IXGB_WRITE_REG(hw, MSCA, command);
773
774 /**************************************************************
775 ** Check every 10 usec to see if the read command completed
776 ** The COMMAND bit will clear when the operation is complete.
777 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
778 ** from the CPU Write to the Ready bit assertion.
779 **************************************************************/
780
781 for(i = 0; i < 10; i++)
782 {
783 udelay(10);
784
785 command = IXGB_READ_REG(hw, MSCA);
786
787 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
788 break;
789 }
790
791 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
792
793 /* Operation is complete, get the data from the MDIO Read/Write Data
794 * register and return.
795 */
796 data = IXGB_READ_REG(hw, MSRWD);
797 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
798 return((uint16_t) data);
799}
800
801/******************************************************************************
802 * Writes a word to a device over the Management Data Interface (MDI) bus.
803 * This interface is used to manage Physical layer devices.
804 *
805 * hw - Struct containing variables accessed by hw code
806 * reg_address - Offset of device register being read.
807 * phy_address - Address of device on MDI.
808 * device_type - Also known as the Device ID or DID.
809 * data - 16-bit value to be written
810 *
811 * Returns: void.
812 *
813 * The 82597EX has support for several MDI access methods. This routine
814 * uses the new protocol MDI Single Command and Address Operation.
815 * This requires that first an address cycle command is sent, followed by a
816 * write command.
817 *****************************************************************************/
818void
819ixgb_write_phy_reg(struct ixgb_hw *hw,
820 uint32_t reg_address,
821 uint32_t phy_address,
822 uint32_t device_type,
823 uint16_t data)
824{
825 uint32_t i;
826 uint32_t command = 0;
827
828 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
829 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
830 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
831
832 /* Put the data in the MDIO Read/Write Data register */
833 IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
834
835 /* Setup and write the address cycle command */
836 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
837 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
838 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
839 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
840
841 IXGB_WRITE_REG(hw, MSCA, command);
842
843 /**************************************************************
844 ** Check every 10 usec to see if the address cycle completed
845 ** The COMMAND bit will clear when the operation is complete.
846 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
847 ** from the CPU Write to the Ready bit assertion.
848 **************************************************************/
849
850 for(i = 0; i < 10; i++)
851 {
852 udelay(10);
853
854 command = IXGB_READ_REG(hw, MSCA);
855
856 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
857 break;
858 }
859
860 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
861
862 /* Address cycle complete, setup and write the write command */
863 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
864 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
865 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
866 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
867
868 IXGB_WRITE_REG(hw, MSCA, command);
869
870 /**************************************************************
871 ** Check every 10 usec to see if the read command completed
872 ** The COMMAND bit will clear when the operation is complete.
873 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
874 ** from the CPU Write to the Ready bit assertion.
875 **************************************************************/
876
877 for(i = 0; i < 10; i++)
878 {
879 udelay(10);
880
881 command = IXGB_READ_REG(hw, MSCA);
882
883 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
884 break;
885 }
886
887 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
888
889 /* Operation is complete, return. */
890}
891
892/******************************************************************************
893 * Checks to see if the link status of the hardware has changed.
894 *
895 * hw - Struct containing variables accessed by hw code
896 *
897 * Called by any function that needs to check the link status of the adapter.
898 *****************************************************************************/
899void
900ixgb_check_for_link(struct ixgb_hw *hw)
901{
902 uint32_t status_reg;
903 uint32_t xpcss_reg;
904
905 DEBUGFUNC("ixgb_check_for_link");
906
907 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
908 status_reg = IXGB_READ_REG(hw, STATUS);
909
910 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
911 (status_reg & IXGB_STATUS_LU)) {
912 hw->link_up = TRUE;
913 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
914 (status_reg & IXGB_STATUS_LU)) {
915 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
916 hw->link_up = ixgb_link_reset(hw);
917 } else {
918 /*
919 * 82597EX errata. Since the lane deskew problem may prevent
920 * link, reset the link before reporting link down.
921 */
922 hw->link_up = ixgb_link_reset(hw);
923 }
924 /* Anything else for 10 Gig?? */
925}
926
927/******************************************************************************
928 * Check for a bad link condition that may have occured.
929 * The indication is that the RFC / LFC registers may be incrementing
930 * continually. A full adapter reset is required to recover.
931 *
932 * hw - Struct containing variables accessed by hw code
933 *
934 * Called by any function that needs to check the link status of the adapter.
935 *****************************************************************************/
936boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw)
937{
938 uint32_t newLFC, newRFC;
939 boolean_t bad_link_returncode = FALSE;
940
941 if (hw->phy_type == ixgb_phy_type_txn17401) {
942 newLFC = IXGB_READ_REG(hw, LFC);
943 newRFC = IXGB_READ_REG(hw, RFC);
944 if ((hw->lastLFC + 250 < newLFC)
945 || (hw->lastRFC + 250 < newRFC)) {
946 DEBUGOUT
947 ("BAD LINK! too many LFC/RFC since last check\n");
948 bad_link_returncode = TRUE;
949 }
950 hw->lastLFC = newLFC;
951 hw->lastRFC = newRFC;
952 }
953
954 return bad_link_returncode;
955}
956
957/******************************************************************************
958 * Clears all hardware statistics counters.
959 *
960 * hw - Struct containing variables accessed by shared code
961 *****************************************************************************/
962void
963ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
964{
965 volatile uint32_t temp_reg;
966
967 DEBUGFUNC("ixgb_clear_hw_cntrs");
968
969 /* if we are stopped or resetting exit gracefully */
970 if(hw->adapter_stopped) {
971 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
972 return;
973 }
974
975 temp_reg = IXGB_READ_REG(hw, TPRL);
976 temp_reg = IXGB_READ_REG(hw, TPRH);
977 temp_reg = IXGB_READ_REG(hw, GPRCL);
978 temp_reg = IXGB_READ_REG(hw, GPRCH);
979 temp_reg = IXGB_READ_REG(hw, BPRCL);
980 temp_reg = IXGB_READ_REG(hw, BPRCH);
981 temp_reg = IXGB_READ_REG(hw, MPRCL);
982 temp_reg = IXGB_READ_REG(hw, MPRCH);
983 temp_reg = IXGB_READ_REG(hw, UPRCL);
984 temp_reg = IXGB_READ_REG(hw, UPRCH);
985 temp_reg = IXGB_READ_REG(hw, VPRCL);
986 temp_reg = IXGB_READ_REG(hw, VPRCH);
987 temp_reg = IXGB_READ_REG(hw, JPRCL);
988 temp_reg = IXGB_READ_REG(hw, JPRCH);
989 temp_reg = IXGB_READ_REG(hw, GORCL);
990 temp_reg = IXGB_READ_REG(hw, GORCH);
991 temp_reg = IXGB_READ_REG(hw, TORL);
992 temp_reg = IXGB_READ_REG(hw, TORH);
993 temp_reg = IXGB_READ_REG(hw, RNBC);
994 temp_reg = IXGB_READ_REG(hw, RUC);
995 temp_reg = IXGB_READ_REG(hw, ROC);
996 temp_reg = IXGB_READ_REG(hw, RLEC);
997 temp_reg = IXGB_READ_REG(hw, CRCERRS);
998 temp_reg = IXGB_READ_REG(hw, ICBC);
999 temp_reg = IXGB_READ_REG(hw, ECBC);
1000 temp_reg = IXGB_READ_REG(hw, MPC);
1001 temp_reg = IXGB_READ_REG(hw, TPTL);
1002 temp_reg = IXGB_READ_REG(hw, TPTH);
1003 temp_reg = IXGB_READ_REG(hw, GPTCL);
1004 temp_reg = IXGB_READ_REG(hw, GPTCH);
1005 temp_reg = IXGB_READ_REG(hw, BPTCL);
1006 temp_reg = IXGB_READ_REG(hw, BPTCH);
1007 temp_reg = IXGB_READ_REG(hw, MPTCL);
1008 temp_reg = IXGB_READ_REG(hw, MPTCH);
1009 temp_reg = IXGB_READ_REG(hw, UPTCL);
1010 temp_reg = IXGB_READ_REG(hw, UPTCH);
1011 temp_reg = IXGB_READ_REG(hw, VPTCL);
1012 temp_reg = IXGB_READ_REG(hw, VPTCH);
1013 temp_reg = IXGB_READ_REG(hw, JPTCL);
1014 temp_reg = IXGB_READ_REG(hw, JPTCH);
1015 temp_reg = IXGB_READ_REG(hw, GOTCL);
1016 temp_reg = IXGB_READ_REG(hw, GOTCH);
1017 temp_reg = IXGB_READ_REG(hw, TOTL);
1018 temp_reg = IXGB_READ_REG(hw, TOTH);
1019 temp_reg = IXGB_READ_REG(hw, DC);
1020 temp_reg = IXGB_READ_REG(hw, PLT64C);
1021 temp_reg = IXGB_READ_REG(hw, TSCTC);
1022 temp_reg = IXGB_READ_REG(hw, TSCTFC);
1023 temp_reg = IXGB_READ_REG(hw, IBIC);
1024 temp_reg = IXGB_READ_REG(hw, RFC);
1025 temp_reg = IXGB_READ_REG(hw, LFC);
1026 temp_reg = IXGB_READ_REG(hw, PFRC);
1027 temp_reg = IXGB_READ_REG(hw, PFTC);
1028 temp_reg = IXGB_READ_REG(hw, MCFRC);
1029 temp_reg = IXGB_READ_REG(hw, MCFTC);
1030 temp_reg = IXGB_READ_REG(hw, XONRXC);
1031 temp_reg = IXGB_READ_REG(hw, XONTXC);
1032 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1033 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1034 temp_reg = IXGB_READ_REG(hw, RJC);
1035 return;
1036}
1037
1038/******************************************************************************
1039 * Turns on the software controllable LED
1040 *
1041 * hw - Struct containing variables accessed by shared code
1042 *****************************************************************************/
1043void
1044ixgb_led_on(struct ixgb_hw *hw)
1045{
1046 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1047
1048 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1049 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1050 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1051 return;
1052}
1053
1054/******************************************************************************
1055 * Turns off the software controllable LED
1056 *
1057 * hw - Struct containing variables accessed by shared code
1058 *****************************************************************************/
1059void
1060ixgb_led_off(struct ixgb_hw *hw)
1061{
1062 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1063
1064 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1065 ctrl0_reg |= IXGB_CTRL0_SDP0;
1066 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1067 return;
1068}
1069
1070/******************************************************************************
1071 * Gets the current PCI bus type, speed, and width of the hardware
1072 *
1073 * hw - Struct containing variables accessed by shared code
1074 *****************************************************************************/
1075static void
1076ixgb_get_bus_info(struct ixgb_hw *hw)
1077{
1078 uint32_t status_reg;
1079
1080 status_reg = IXGB_READ_REG(hw, STATUS);
1081
1082 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1083 ixgb_bus_type_pcix : ixgb_bus_type_pci;
1084
1085 if (hw->bus.type == ixgb_bus_type_pci) {
1086 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1087 ixgb_bus_speed_66 : ixgb_bus_speed_33;
1088 } else {
1089 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1090 case IXGB_STATUS_PCIX_SPD_66:
1091 hw->bus.speed = ixgb_bus_speed_66;
1092 break;
1093 case IXGB_STATUS_PCIX_SPD_100:
1094 hw->bus.speed = ixgb_bus_speed_100;
1095 break;
1096 case IXGB_STATUS_PCIX_SPD_133:
1097 hw->bus.speed = ixgb_bus_speed_133;
1098 break;
1099 default:
1100 hw->bus.speed = ixgb_bus_speed_reserved;
1101 break;
1102 }
1103 }
1104
1105 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1106 ixgb_bus_width_64 : ixgb_bus_width_32;
1107
1108 return;
1109}
1110
1111/******************************************************************************
1112 * Tests a MAC address to ensure it is a valid Individual Address
1113 *
1114 * mac_addr - pointer to MAC address.
1115 *
1116 *****************************************************************************/
1117boolean_t
1118mac_addr_valid(uint8_t *mac_addr)
1119{
1120 boolean_t is_valid = TRUE;
1121 DEBUGFUNC("mac_addr_valid");
1122
1123 /* Make sure it is not a multicast address */
1124 if (IS_MULTICAST(mac_addr)) {
1125 DEBUGOUT("MAC address is multicast\n");
1126 is_valid = FALSE;
1127 }
1128 /* Not a broadcast address */
1129 else if (IS_BROADCAST(mac_addr)) {
1130 DEBUGOUT("MAC address is broadcast\n");
1131 is_valid = FALSE;
1132 }
1133 /* Reject the zero address */
1134 else if (mac_addr[0] == 0 &&
1135 mac_addr[1] == 0 &&
1136 mac_addr[2] == 0 &&
1137 mac_addr[3] == 0 &&
1138 mac_addr[4] == 0 &&
1139 mac_addr[5] == 0) {
1140 DEBUGOUT("MAC address is all zeros\n");
1141 is_valid = FALSE;
1142 }
1143 return (is_valid);
1144}
1145
1146/******************************************************************************
1147 * Resets the 10GbE link. Waits the settle time and returns the state of
1148 * the link.
1149 *
1150 * hw - Struct containing variables accessed by shared code
1151 *****************************************************************************/
1152boolean_t
1153ixgb_link_reset(struct ixgb_hw *hw)
1154{
1155 boolean_t link_status = FALSE;
1156 uint8_t wait_retries = MAX_RESET_ITERATIONS;
1157 uint8_t lrst_retries = MAX_RESET_ITERATIONS;
1158
1159 do {
1160 /* Reset the link */
1161 IXGB_WRITE_REG(hw, CTRL0,
1162 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1163
1164 /* Wait for link-up and lane re-alignment */
1165 do {
1166 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1167 link_status =
1168 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1169 && (IXGB_READ_REG(hw, XPCSS) &
1170 IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
1171 } while (!link_status && --wait_retries);
1172
1173 } while (!link_status && --lrst_retries);
1174
1175 return link_status;
1176}
1177
1178/******************************************************************************
1179 * Resets the 10GbE optics module.
1180 *
1181 * hw - Struct containing variables accessed by shared code
1182 *****************************************************************************/
1183void
1184ixgb_optics_reset(struct ixgb_hw *hw)
1185{
1186 if (hw->phy_type == ixgb_phy_type_txn17401) {
1187 uint16_t mdio_reg;
1188
1189 ixgb_write_phy_reg(hw,
1190 MDIO_PMA_PMD_CR1,
1191 IXGB_PHY_ADDRESS,
1192 MDIO_PMA_PMD_DID,
1193 MDIO_PMA_PMD_CR1_RESET);
1194
1195 mdio_reg = ixgb_read_phy_reg( hw,
1196 MDIO_PMA_PMD_CR1,
1197 IXGB_PHY_ADDRESS,
1198 MDIO_PMA_PMD_DID);
1199 }
1200
1201 return;
1202}
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