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authorDmitry Torokhov <dtor_core@ameritech.net>2005-09-06 18:19:17 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-07 19:57:57 -0400
commit527b6af4133f433542a875dea7a24d58f8871d4b (patch)
treeada02585d9ef2523508fab47f6b946b06c8d9c35 /drivers/net/irda/smsc-ircc2.h
parent4407c2b6b297339e296facf62e020cf66e55053d (diff)
[PATCH] smsc-ircc2: whitespace fixes
IRDA: smsc-ircc2 - whitespace fixes. Signed-off-by: Dmitry Torokhov <dtor@mail.ru> Cc: Jean Tourrilhes <jt@hpl.hp.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/net/irda/smsc-ircc2.h')
-rw-r--r--drivers/net/irda/smsc-ircc2.h50
1 files changed, 25 insertions, 25 deletions
diff --git a/drivers/net/irda/smsc-ircc2.h b/drivers/net/irda/smsc-ircc2.h
index 458611cc0d40..0c36286d87f7 100644
--- a/drivers/net/irda/smsc-ircc2.h
+++ b/drivers/net/irda/smsc-ircc2.h
@@ -1,5 +1,5 @@
1/********************************************************************* 1/*********************************************************************
2 * $Id: smsc-ircc2.h,v 1.12.2.1 2002/10/27 10:52:37 dip Exp $ 2 * $Id: smsc-ircc2.h,v 1.12.2.1 2002/10/27 10:52:37 dip Exp $
3 * 3 *
4 * Description: Definitions for the SMC IrCC chipset 4 * Description: Definitions for the SMC IrCC chipset
5 * Status: Experimental. 5 * Status: Experimental.
@@ -9,25 +9,25 @@
9 * All Rights Reserved. 9 * All Rights Reserved.
10 * 10 *
11 * Based on smc-ircc.h: 11 * Based on smc-ircc.h:
12 * 12 *
13 * Copyright (c) 1999-2000, Dag Brattli <dagb@cs.uit.no> 13 * Copyright (c) 1999-2000, Dag Brattli <dagb@cs.uit.no>
14 * Copyright (c) 1998-1999, Thomas Davis (tadavis@jps.net> 14 * Copyright (c) 1998-1999, Thomas Davis (tadavis@jps.net>
15 * All Rights Reserved 15 * All Rights Reserved
16 * 16 *
17 * 17 *
18 * This program is free software; you can redistribute it and/or 18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as 19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of 20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version. 21 * the License, or (at your option) any later version.
22 * 22 *
23 * This program is distributed in the hope that it will be useful, 23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details. 26 * GNU General Public License for more details.
27 * 27 *
28 * You should have received a copy of the GNU General Public License 28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software 29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA 31 * MA 02111-1307 USA
32 * 32 *
33 ********************************************************************/ 33 ********************************************************************/
@@ -112,10 +112,10 @@
112 112
113#define IRCC_CFGA_COM 0x00 113#define IRCC_CFGA_COM 0x00
114#define IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK 0x87 114#define IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK 0x87
115#define IRCC_CFGA_IRDA_SIR_A 0x08 115#define IRCC_CFGA_IRDA_SIR_A 0x08
116#define IRCC_CFGA_ASK_SIR 0x10 116#define IRCC_CFGA_ASK_SIR 0x10
117#define IRCC_CFGA_IRDA_SIR_B 0x18 117#define IRCC_CFGA_IRDA_SIR_B 0x18
118#define IRCC_CFGA_IRDA_HDLC 0x20 118#define IRCC_CFGA_IRDA_HDLC 0x20
119#define IRCC_CFGA_IRDA_4PPM 0x28 119#define IRCC_CFGA_IRDA_4PPM 0x28
120#define IRCC_CFGA_CONSUMER 0x30 120#define IRCC_CFGA_CONSUMER 0x30
121#define IRCC_CFGA_RAW_IR 0x38 121#define IRCC_CFGA_RAW_IR 0x38
@@ -130,7 +130,7 @@
130#define IRCC_CFGB_LPBCK_TX_CRC 0x10 130#define IRCC_CFGB_LPBCK_TX_CRC 0x10
131#define IRCC_CFGB_NOWAIT 0x08 131#define IRCC_CFGB_NOWAIT 0x08
132#define IRCC_CFGB_STRING_MOVE 0x04 132#define IRCC_CFGB_STRING_MOVE 0x04
133#define IRCC_CFGB_DMA_BURST 0x02 133#define IRCC_CFGB_DMA_BURST 0x02
134#define IRCC_CFGB_DMA_ENABLE 0x01 134#define IRCC_CFGB_DMA_ENABLE 0x01
135 135
136#define IRCC_CFGB_MUX_COM 0x00 136#define IRCC_CFGB_MUX_COM 0x00
@@ -141,11 +141,11 @@
141/* Register block 3 - Identification Registers! */ 141/* Register block 3 - Identification Registers! */
142#define IRCC_ID_HIGH 0x00 /* 0x10 */ 142#define IRCC_ID_HIGH 0x00 /* 0x10 */
143#define IRCC_ID_LOW 0x01 /* 0xB8 */ 143#define IRCC_ID_LOW 0x01 /* 0xB8 */
144#define IRCC_CHIP_ID 0x02 /* 0xF1 */ 144#define IRCC_CHIP_ID 0x02 /* 0xF1 */
145#define IRCC_VERSION 0x03 /* 0x01 */ 145#define IRCC_VERSION 0x03 /* 0x01 */
146#define IRCC_INTERFACE 0x04 /* low 4 = DMA, high 4 = IRQ */ 146#define IRCC_INTERFACE 0x04 /* low 4 = DMA, high 4 = IRQ */
147#define IRCC_INTERFACE_DMA_MASK 0x0F /* low 4 = DMA, high 4 = IRQ */ 147#define IRCC_INTERFACE_DMA_MASK 0x0F /* low 4 = DMA, high 4 = IRQ */
148#define IRCC_INTERFACE_IRQ_MASK 0xF0 /* low 4 = DMA, high 4 = IRQ */ 148#define IRCC_INTERFACE_IRQ_MASK 0xF0 /* low 4 = DMA, high 4 = IRQ */
149 149
150/* Register block 4 - IrDA */ 150/* Register block 4 - IrDA */
151#define IRCC_CONTROL 0x00 151#define IRCC_CONTROL 0x00
@@ -163,10 +163,10 @@
163 163
164/* Register block 5 - IrDA */ 164/* Register block 5 - IrDA */
165#define IRCC_ATC 0x00 165#define IRCC_ATC 0x00
166#define IRCC_ATC_nPROGREADY 0x80 166#define IRCC_ATC_nPROGREADY 0x80
167#define IRCC_ATC_SPEED 0x40 167#define IRCC_ATC_SPEED 0x40
168#define IRCC_ATC_ENABLE 0x20 168#define IRCC_ATC_ENABLE 0x20
169#define IRCC_ATC_MASK 0xE0 169#define IRCC_ATC_MASK 0xE0
170 170
171 171
172#define IRCC_IRHALFDUPLEX_TIMEOUT 0x01 172#define IRCC_IRHALFDUPLEX_TIMEOUT 0x01
@@ -178,8 +178,8 @@
178 */ 178 */
179 179
180#define SMSC_IRCC2_MAX_SIR_SPEED 115200 180#define SMSC_IRCC2_MAX_SIR_SPEED 115200
181#define SMSC_IRCC2_FIR_CHIP_IO_EXTENT 8 181#define SMSC_IRCC2_FIR_CHIP_IO_EXTENT 8
182#define SMSC_IRCC2_SIR_CHIP_IO_EXTENT 8 182#define SMSC_IRCC2_SIR_CHIP_IO_EXTENT 8
183#define SMSC_IRCC2_FIFO_SIZE 16 183#define SMSC_IRCC2_FIFO_SIZE 16
184#define SMSC_IRCC2_FIFO_THRESHOLD 64 184#define SMSC_IRCC2_FIFO_THRESHOLD 64
185/* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */ 185/* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */