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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/irda/smsc-ircc2.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/irda/smsc-ircc2.c')
-rw-r--r--drivers/net/irda/smsc-ircc2.c2396
1 files changed, 2396 insertions, 0 deletions
diff --git a/drivers/net/irda/smsc-ircc2.c b/drivers/net/irda/smsc-ircc2.c
new file mode 100644
index 000000000000..10125a1dba22
--- /dev/null
+++ b/drivers/net/irda/smsc-ircc2.c
@@ -0,0 +1,2396 @@
1/*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
20 * Copyright (c) 1998-1999 Thomas Davis,
21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
30 * the License, or (at your option) any later version.
31 *
32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44#include <linux/module.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/skbuff.h>
48#include <linux/netdevice.h>
49#include <linux/ioport.h>
50#include <linux/delay.h>
51#include <linux/slab.h>
52#include <linux/init.h>
53#include <linux/rtnetlink.h>
54#include <linux/serial_reg.h>
55#include <linux/dma-mapping.h>
56
57#include <asm/io.h>
58#include <asm/dma.h>
59#include <asm/byteorder.h>
60
61#include <linux/spinlock.h>
62#include <linux/pm.h>
63
64#include <net/irda/wrapper.h>
65#include <net/irda/irda.h>
66#include <net/irda/irda_device.h>
67
68#include "smsc-ircc2.h"
69#include "smsc-sio.h"
70
71/* Types */
72
73struct smsc_transceiver {
74 char *name;
75 void (*set_for_speed)(int fir_base, u32 speed);
76 int (*probe)(int fir_base);
77};
78typedef struct smsc_transceiver smsc_transceiver_t;
79
80#if 0
81struct smc_chip {
82 char *name;
83 u16 flags;
84 u8 devid;
85 u8 rev;
86};
87typedef struct smc_chip smc_chip_t;
88#endif
89
90struct smsc_chip {
91 char *name;
92 #if 0
93 u8 type;
94 #endif
95 u16 flags;
96 u8 devid;
97 u8 rev;
98};
99typedef struct smsc_chip smsc_chip_t;
100
101struct smsc_chip_address {
102 unsigned int cfg_base;
103 unsigned int type;
104};
105typedef struct smsc_chip_address smsc_chip_address_t;
106
107/* Private data for each instance */
108struct smsc_ircc_cb {
109 struct net_device *netdev; /* Yes! we are some kind of netdevice */
110 struct net_device_stats stats;
111 struct irlap_cb *irlap; /* The link layer we are binded to */
112
113 chipio_t io; /* IrDA controller information */
114 iobuff_t tx_buff; /* Transmit buffer */
115 iobuff_t rx_buff; /* Receive buffer */
116 dma_addr_t tx_buff_dma;
117 dma_addr_t rx_buff_dma;
118
119 struct qos_info qos; /* QoS capabilities for this device */
120
121 spinlock_t lock; /* For serializing operations */
122
123 __u32 new_speed;
124 __u32 flags; /* Interface flags */
125
126 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
127 int tx_len; /* Number of frames in tx_buff */
128
129 int transceiver;
130 struct pm_dev *pmdev;
131};
132
133/* Constants */
134
135static const char *driver_name = "smsc-ircc2";
136#define DIM(x) (sizeof(x)/(sizeof(*(x))))
137#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
138#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
139#define SMSC_IRCC2_C_NET_TIMEOUT 0
140#define SMSC_IRCC2_C_SIR_STOP 0
141
142/* Prototypes */
143
144static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
145static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
146static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
147static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
148static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
149static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
150static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase);
151static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase);
152static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
153static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
154static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
155static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs);
156static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase);
157static void smsc_ircc_change_speed(void *priv, u32 speed);
158static void smsc_ircc_set_sir_speed(void *priv, u32 speed);
159static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
160static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
161static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
162#if SMSC_IRCC2_C_SIR_STOP
163static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
164#endif
165static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
166static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
167static int smsc_ircc_net_open(struct net_device *dev);
168static int smsc_ircc_net_close(struct net_device *dev);
169static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
170#if SMSC_IRCC2_C_NET_TIMEOUT
171static void smsc_ircc_timeout(struct net_device *dev);
172#endif
173static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
174static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
175static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
176static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
177static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
178static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
179
180/* Probing */
181static int __init smsc_ircc_look_for_chips(void);
182static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg,const smsc_chip_t *chip,char *type);
183static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfg_base, char *type);
184static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type);
185static int __init smsc_superio_fdc(unsigned short cfg_base);
186static int __init smsc_superio_lpc(unsigned short cfg_base);
187
188/* Transceivers specific functions */
189
190static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
191static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
192static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
193static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
194static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
195static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
196
197/* Power Management */
198
199static void smsc_ircc_suspend(struct smsc_ircc_cb *self);
200static void smsc_ircc_wakeup(struct smsc_ircc_cb *self);
201static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
202
203
204/* Transceivers for SMSC-ircc */
205
206static smsc_transceiver_t smsc_transceivers[]=
207{
208 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800},
209 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select},
210 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc},
211 { NULL, NULL}
212};
213#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (DIM(smsc_transceivers)-1)
214
215/* SMC SuperIO chipsets definitions */
216
217#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
218#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
219#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
220#define SIR 0 /* SuperIO Chip has only slow IRDA */
221#define FIR 4 /* SuperIO Chip has fast IRDA */
222#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
223
224static smsc_chip_t __initdata fdc_chips_flat[]=
225{
226 /* Base address 0x3f0 or 0x370 */
227 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
228 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
229 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
230 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
231 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
232 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
233 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
234 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
235 { NULL }
236};
237
238static smsc_chip_t __initdata fdc_chips_paged[]=
239{
240 /* Base address 0x3f0 or 0x370 */
241 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
242 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
243 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
244 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
245 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
246 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
247 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
248 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
249 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
250 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
251 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
252 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
253 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
254 { NULL }
255};
256
257static smsc_chip_t __initdata lpc_chips_flat[]=
258{
259 /* Base address 0x2E or 0x4E */
260 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
261 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
262 { NULL }
263};
264
265static smsc_chip_t __initdata lpc_chips_paged[]=
266{
267 /* Base address 0x2E or 0x4E */
268 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
269 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
270 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
271 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
272 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
273 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
274 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
275 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
276 { NULL }
277};
278
279#define SMSCSIO_TYPE_FDC 1
280#define SMSCSIO_TYPE_LPC 2
281#define SMSCSIO_TYPE_FLAT 4
282#define SMSCSIO_TYPE_PAGED 8
283
284static smsc_chip_address_t __initdata possible_addresses[]=
285{
286 {0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
287 {0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
288 {0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
289 {0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
290 {0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
291 {0,0}
292};
293
294/* Globals */
295
296static struct smsc_ircc_cb *dev_self[] = { NULL, NULL};
297
298static int ircc_irq=255;
299static int ircc_dma=255;
300static int ircc_fir=0;
301static int ircc_sir=0;
302static int ircc_cfg=0;
303static int ircc_transceiver=0;
304
305static unsigned short dev_count=0;
306
307static inline void register_bank(int iobase, int bank)
308{
309 outb(((inb(iobase+IRCC_MASTER) & 0xf0) | (bank & 0x07)),
310 iobase+IRCC_MASTER);
311}
312
313
314/*******************************************************************************
315 *
316 *
317 * SMSC-ircc stuff
318 *
319 *
320 *******************************************************************************/
321
322/*
323 * Function smsc_ircc_init ()
324 *
325 * Initialize chip. Just try to find out how many chips we are dealing with
326 * and where they are
327 */
328static int __init smsc_ircc_init(void)
329{
330 int ret=-ENODEV;
331
332 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
333
334 dev_count=0;
335
336 if ((ircc_fir>0)&&(ircc_sir>0)) {
337 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
338 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
339
340 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq) == 0)
341 return 0;
342
343 return -ENODEV;
344 }
345
346 /* try user provided configuration register base address */
347 if (ircc_cfg>0) {
348 IRDA_MESSAGE(" Overriding configuration address 0x%04x\n",
349 ircc_cfg);
350 if (!smsc_superio_fdc(ircc_cfg))
351 ret = 0;
352 if (!smsc_superio_lpc(ircc_cfg))
353 ret = 0;
354 }
355
356 if(smsc_ircc_look_for_chips()>0) ret = 0;
357
358 return ret;
359}
360
361/*
362 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
363 *
364 * Try to open driver instance
365 *
366 */
367static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
368{
369 struct smsc_ircc_cb *self;
370 struct net_device *dev;
371 int err;
372
373 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
374
375 err = smsc_ircc_present(fir_base, sir_base);
376 if(err)
377 goto err_out;
378
379 err = -ENOMEM;
380 if (dev_count > DIM(dev_self)) {
381 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
382 goto err_out1;
383 }
384
385 /*
386 * Allocate new instance of the driver
387 */
388 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
389 if (!dev) {
390 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
391 goto err_out1;
392 }
393
394 SET_MODULE_OWNER(dev);
395
396 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
397#if SMSC_IRCC2_C_NET_TIMEOUT
398 dev->tx_timeout = smsc_ircc_timeout;
399 dev->watchdog_timeo = HZ*2; /* Allow enough time for speed change */
400#endif
401 dev->open = smsc_ircc_net_open;
402 dev->stop = smsc_ircc_net_close;
403 dev->do_ioctl = smsc_ircc_net_ioctl;
404 dev->get_stats = smsc_ircc_net_get_stats;
405
406 self = dev->priv;
407 self->netdev = dev;
408
409 /* Make ifconfig display some details */
410 dev->base_addr = self->io.fir_base = fir_base;
411 dev->irq = self->io.irq = irq;
412
413 /* Need to store self somewhere */
414 dev_self[dev_count++] = self;
415 spin_lock_init(&self->lock);
416
417 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
418 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
419
420 self->rx_buff.head =
421 dma_alloc_coherent(NULL, self->rx_buff.truesize,
422 &self->rx_buff_dma, GFP_KERNEL);
423 if (self->rx_buff.head == NULL) {
424 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
425 driver_name);
426 goto err_out2;
427 }
428
429 self->tx_buff.head =
430 dma_alloc_coherent(NULL, self->tx_buff.truesize,
431 &self->tx_buff_dma, GFP_KERNEL);
432 if (self->tx_buff.head == NULL) {
433 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
434 driver_name);
435 goto err_out3;
436 }
437
438 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
439 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
440
441 self->rx_buff.in_frame = FALSE;
442 self->rx_buff.state = OUTSIDE_FRAME;
443 self->tx_buff.data = self->tx_buff.head;
444 self->rx_buff.data = self->rx_buff.head;
445
446 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
447
448 smsc_ircc_setup_qos(self);
449
450 smsc_ircc_init_chip(self);
451
452 if(ircc_transceiver > 0 &&
453 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
454 self->transceiver = ircc_transceiver;
455 else
456 smsc_ircc_probe_transceiver(self);
457
458 err = register_netdev(self->netdev);
459 if(err) {
460 IRDA_ERROR("%s, Network device registration failed!\n",
461 driver_name);
462 goto err_out4;
463 }
464
465 self->pmdev = pm_register(PM_SYS_DEV, PM_SYS_IRDA, smsc_ircc_pmproc);
466 if (self->pmdev)
467 self->pmdev->data = self;
468
469 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
470
471 return 0;
472 err_out4:
473 dma_free_coherent(NULL, self->tx_buff.truesize,
474 self->tx_buff.head, self->tx_buff_dma);
475 err_out3:
476 dma_free_coherent(NULL, self->rx_buff.truesize,
477 self->rx_buff.head, self->rx_buff_dma);
478 err_out2:
479 free_netdev(self->netdev);
480 dev_self[--dev_count] = NULL;
481 err_out1:
482 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
483 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
484 err_out:
485 return err;
486}
487
488/*
489 * Function smsc_ircc_present(fir_base, sir_base)
490 *
491 * Check the smsc-ircc chip presence
492 *
493 */
494static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
495{
496 unsigned char low, high, chip, config, dma, irq, version;
497
498 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
499 driver_name)) {
500 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
501 __FUNCTION__, fir_base);
502 goto out1;
503 }
504
505 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
506 driver_name)) {
507 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
508 __FUNCTION__, sir_base);
509 goto out2;
510 }
511
512 register_bank(fir_base, 3);
513
514 high = inb(fir_base+IRCC_ID_HIGH);
515 low = inb(fir_base+IRCC_ID_LOW);
516 chip = inb(fir_base+IRCC_CHIP_ID);
517 version = inb(fir_base+IRCC_VERSION);
518 config = inb(fir_base+IRCC_INTERFACE);
519 dma = config & IRCC_INTERFACE_DMA_MASK;
520 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
521
522 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
523 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
524 __FUNCTION__, fir_base);
525 goto out3;
526 }
527 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
528 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
529 chip & 0x0f, version, fir_base, sir_base, dma, irq);
530
531 return 0;
532 out3:
533 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
534 out2:
535 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
536 out1:
537 return -ENODEV;
538}
539
540/*
541 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
542 *
543 * Setup I/O
544 *
545 */
546static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
547 unsigned int fir_base, unsigned int sir_base,
548 u8 dma, u8 irq)
549{
550 unsigned char config, chip_dma, chip_irq;
551
552 register_bank(fir_base, 3);
553 config = inb(fir_base+IRCC_INTERFACE);
554 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
555 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
556
557 self->io.fir_base = fir_base;
558 self->io.sir_base = sir_base;
559 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
560 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
561 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
562 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
563
564 if (irq < 255) {
565 if (irq != chip_irq)
566 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
567 driver_name, chip_irq, irq);
568 self->io.irq = irq;
569 }
570 else
571 self->io.irq = chip_irq;
572
573 if (dma < 255) {
574 if (dma != chip_dma)
575 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
576 driver_name, chip_dma, dma);
577 self->io.dma = dma;
578 }
579 else
580 self->io.dma = chip_dma;
581
582}
583
584/*
585 * Function smsc_ircc_setup_qos(self)
586 *
587 * Setup qos
588 *
589 */
590static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
591{
592 /* Initialize QoS for this device */
593 irda_init_max_qos_capabilies(&self->qos);
594
595 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
596 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
597
598 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
599 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
600 irda_qos_bits_to_value(&self->qos);
601}
602
603/*
604 * Function smsc_ircc_init_chip(self)
605 *
606 * Init chip
607 *
608 */
609static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
610{
611 int iobase, ir_mode, ctrl, fast;
612
613 IRDA_ASSERT( self != NULL, return; );
614 iobase = self->io.fir_base;
615
616 ir_mode = IRCC_CFGA_IRDA_SIR_A;
617 ctrl = 0;
618 fast = 0;
619
620 register_bank(iobase, 0);
621 outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER);
622 outb(0x00, iobase+IRCC_MASTER);
623
624 register_bank(iobase, 1);
625 outb(((inb(iobase+IRCC_SCE_CFGA) & 0x87) | ir_mode),
626 iobase+IRCC_SCE_CFGA);
627
628#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
629 outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
630 iobase+IRCC_SCE_CFGB);
631#else
632 outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
633 iobase+IRCC_SCE_CFGB);
634#endif
635 (void) inb(iobase+IRCC_FIFO_THRESHOLD);
636 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase+IRCC_FIFO_THRESHOLD);
637
638 register_bank(iobase, 4);
639 outb((inb(iobase+IRCC_CONTROL) & 0x30) | ctrl, iobase+IRCC_CONTROL);
640
641 register_bank(iobase, 0);
642 outb(fast, iobase+IRCC_LCR_A);
643
644 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
645
646 /* Power on device */
647 outb(0x00, iobase+IRCC_MASTER);
648}
649
650/*
651 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
652 *
653 * Process IOCTL commands for this device
654 *
655 */
656static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
657{
658 struct if_irda_req *irq = (struct if_irda_req *) rq;
659 struct smsc_ircc_cb *self;
660 unsigned long flags;
661 int ret = 0;
662
663 IRDA_ASSERT(dev != NULL, return -1;);
664
665 self = dev->priv;
666
667 IRDA_ASSERT(self != NULL, return -1;);
668
669 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
670
671 switch (cmd) {
672 case SIOCSBANDWIDTH: /* Set bandwidth */
673 if (!capable(CAP_NET_ADMIN))
674 ret = -EPERM;
675 else {
676 /* Make sure we are the only one touching
677 * self->io.speed and the hardware - Jean II */
678 spin_lock_irqsave(&self->lock, flags);
679 smsc_ircc_change_speed(self, irq->ifr_baudrate);
680 spin_unlock_irqrestore(&self->lock, flags);
681 }
682 break;
683 case SIOCSMEDIABUSY: /* Set media busy */
684 if (!capable(CAP_NET_ADMIN)) {
685 ret = -EPERM;
686 break;
687 }
688
689 irda_device_set_media_busy(self->netdev, TRUE);
690 break;
691 case SIOCGRECEIVING: /* Check if we are receiving right now */
692 irq->ifr_receiving = smsc_ircc_is_receiving(self);
693 break;
694 #if 0
695 case SIOCSDTRRTS:
696 if (!capable(CAP_NET_ADMIN)) {
697 ret = -EPERM;
698 break;
699 }
700 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
701 break;
702 #endif
703 default:
704 ret = -EOPNOTSUPP;
705 }
706
707 return ret;
708}
709
710static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
711{
712 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) dev->priv;
713
714 return &self->stats;
715}
716
717#if SMSC_IRCC2_C_NET_TIMEOUT
718/*
719 * Function smsc_ircc_timeout (struct net_device *dev)
720 *
721 * The networking timeout management.
722 *
723 */
724
725static void smsc_ircc_timeout(struct net_device *dev)
726{
727 struct smsc_ircc_cb *self;
728 unsigned long flags;
729
730 self = (struct smsc_ircc_cb *) dev->priv;
731
732 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
733 dev->name, self->io.speed);
734 spin_lock_irqsave(&self->lock, flags);
735 smsc_ircc_sir_start(self);
736 smsc_ircc_change_speed(self, self->io.speed);
737 dev->trans_start = jiffies;
738 netif_wake_queue(dev);
739 spin_unlock_irqrestore(&self->lock, flags);
740}
741#endif
742
743/*
744 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
745 *
746 * Transmits the current frame until FIFO is full, then
747 * waits until the next transmit interrupt, and continues until the
748 * frame is transmitted.
749 */
750int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
751{
752 struct smsc_ircc_cb *self;
753 unsigned long flags;
754 int iobase;
755 s32 speed;
756
757 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
758
759 IRDA_ASSERT(dev != NULL, return 0;);
760
761 self = (struct smsc_ircc_cb *) dev->priv;
762 IRDA_ASSERT(self != NULL, return 0;);
763
764 iobase = self->io.sir_base;
765
766 netif_stop_queue(dev);
767
768 /* Make sure test of self->io.speed & speed change are atomic */
769 spin_lock_irqsave(&self->lock, flags);
770
771 /* Check if we need to change the speed */
772 speed = irda_get_next_speed(skb);
773 if ((speed != self->io.speed) && (speed != -1)) {
774 /* Check for empty frame */
775 if (!skb->len) {
776 /*
777 * We send frames one by one in SIR mode (no
778 * pipelining), so at this point, if we were sending
779 * a previous frame, we just received the interrupt
780 * telling us it is finished (UART_IIR_THRI).
781 * Therefore, waiting for the transmitter to really
782 * finish draining the fifo won't take too long.
783 * And the interrupt handler is not expected to run.
784 * - Jean II */
785 smsc_ircc_sir_wait_hw_transmitter_finish(self);
786 smsc_ircc_change_speed(self, speed);
787 spin_unlock_irqrestore(&self->lock, flags);
788 dev_kfree_skb(skb);
789 return 0;
790 } else {
791 self->new_speed = speed;
792 }
793 }
794
795 /* Init tx buffer */
796 self->tx_buff.data = self->tx_buff.head;
797
798 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
799 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
800 self->tx_buff.truesize);
801
802 self->stats.tx_bytes += self->tx_buff.len;
803
804 /* Turn on transmit finished interrupt. Will fire immediately! */
805 outb(UART_IER_THRI, iobase+UART_IER);
806
807 spin_unlock_irqrestore(&self->lock, flags);
808
809 dev_kfree_skb(skb);
810
811 return 0;
812}
813
814/*
815 * Function smsc_ircc_set_fir_speed (self, baud)
816 *
817 * Change the speed of the device
818 *
819 */
820static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
821{
822 int fir_base, ir_mode, ctrl, fast;
823
824 IRDA_ASSERT(self != NULL, return;);
825 fir_base = self->io.fir_base;
826
827 self->io.speed = speed;
828
829 switch(speed) {
830 default:
831 case 576000:
832 ir_mode = IRCC_CFGA_IRDA_HDLC;
833 ctrl = IRCC_CRC;
834 fast = 0;
835 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
836 break;
837 case 1152000:
838 ir_mode = IRCC_CFGA_IRDA_HDLC;
839 ctrl = IRCC_1152 | IRCC_CRC;
840 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
841 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
842 __FUNCTION__);
843 break;
844 case 4000000:
845 ir_mode = IRCC_CFGA_IRDA_4PPM;
846 ctrl = IRCC_CRC;
847 fast = IRCC_LCR_A_FAST;
848 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
849 __FUNCTION__);
850 break;
851 }
852 #if 0
853 Now in tranceiver!
854 /* This causes an interrupt */
855 register_bank(fir_base, 0);
856 outb((inb(fir_base+IRCC_LCR_A) & 0xbf) | fast, fir_base+IRCC_LCR_A);
857 #endif
858
859 register_bank(fir_base, 1);
860 outb(((inb(fir_base+IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base+IRCC_SCE_CFGA);
861
862 register_bank(fir_base, 4);
863 outb((inb(fir_base+IRCC_CONTROL) & 0x30) | ctrl, fir_base+IRCC_CONTROL);
864}
865
866/*
867 * Function smsc_ircc_fir_start(self)
868 *
869 * Change the speed of the device
870 *
871 */
872static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
873{
874 struct net_device *dev;
875 int fir_base;
876
877 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
878
879 IRDA_ASSERT(self != NULL, return;);
880 dev = self->netdev;
881 IRDA_ASSERT(dev != NULL, return;);
882
883 fir_base = self->io.fir_base;
884
885 /* Reset everything */
886
887 /* Install FIR transmit handler */
888 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
889
890 /* Clear FIFO */
891 outb(inb(fir_base+IRCC_LCR_A)|IRCC_LCR_A_FIFO_RESET, fir_base+IRCC_LCR_A);
892
893 /* Enable interrupt */
894 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base+IRCC_IER);*/
895
896 register_bank(fir_base, 1);
897
898 /* Select the TX/RX interface */
899#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
900 outb(((inb(fir_base+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
901 fir_base+IRCC_SCE_CFGB);
902#else
903 outb(((inb(fir_base+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
904 fir_base+IRCC_SCE_CFGB);
905#endif
906 (void) inb(fir_base+IRCC_FIFO_THRESHOLD);
907
908 /* Enable SCE interrupts */
909 outb(0, fir_base+IRCC_MASTER);
910 register_bank(fir_base, 0);
911 outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base+IRCC_IER);
912 outb(IRCC_MASTER_INT_EN, fir_base+IRCC_MASTER);
913}
914
915/*
916 * Function smsc_ircc_fir_stop(self, baud)
917 *
918 * Change the speed of the device
919 *
920 */
921static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
922{
923 int fir_base;
924
925 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
926
927 IRDA_ASSERT(self != NULL, return;);
928
929 fir_base = self->io.fir_base;
930 register_bank(fir_base, 0);
931 /*outb(IRCC_MASTER_RESET, fir_base+IRCC_MASTER);*/
932 outb(inb(fir_base+IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base+IRCC_LCR_B);
933}
934
935
936/*
937 * Function smsc_ircc_change_speed(self, baud)
938 *
939 * Change the speed of the device
940 *
941 * This function *must* be called with spinlock held, because it may
942 * be called from the irq handler. - Jean II
943 */
944static void smsc_ircc_change_speed(void *priv, u32 speed)
945{
946 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
947 struct net_device *dev;
948 int iobase;
949 int last_speed_was_sir;
950
951 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
952
953 IRDA_ASSERT(self != NULL, return;);
954 dev = self->netdev;
955 iobase = self->io.fir_base;
956
957 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
958
959 #if 0
960 /* Temp Hack */
961 speed= 1152000;
962 self->io.speed = speed;
963 last_speed_was_sir = 0;
964 smsc_ircc_fir_start(self);
965 #endif
966
967 if(self->io.speed == 0)
968 smsc_ircc_sir_start(self);
969
970 #if 0
971 if(!last_speed_was_sir) speed = self->io.speed;
972 #endif
973
974 if(self->io.speed != speed) smsc_ircc_set_transceiver_for_speed(self, speed);
975
976 self->io.speed = speed;
977
978 if(speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
979 if(!last_speed_was_sir) {
980 smsc_ircc_fir_stop(self);
981 smsc_ircc_sir_start(self);
982 }
983 smsc_ircc_set_sir_speed(self, speed);
984 }
985 else {
986 if(last_speed_was_sir) {
987 #if SMSC_IRCC2_C_SIR_STOP
988 smsc_ircc_sir_stop(self);
989 #endif
990 smsc_ircc_fir_start(self);
991 }
992 smsc_ircc_set_fir_speed(self, speed);
993
994 #if 0
995 self->tx_buff.len = 10;
996 self->tx_buff.data = self->tx_buff.head;
997
998 smsc_ircc_dma_xmit(self, iobase, 4000);
999 #endif
1000 /* Be ready for incoming frames */
1001 smsc_ircc_dma_receive(self, iobase);
1002 }
1003
1004 netif_wake_queue(dev);
1005}
1006
1007/*
1008 * Function smsc_ircc_set_sir_speed (self, speed)
1009 *
1010 * Set speed of IrDA port to specified baudrate
1011 *
1012 */
1013void smsc_ircc_set_sir_speed(void *priv, __u32 speed)
1014{
1015 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
1016 int iobase;
1017 int fcr; /* FIFO control reg */
1018 int lcr; /* Line control reg */
1019 int divisor;
1020
1021 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1022
1023 IRDA_ASSERT(self != NULL, return;);
1024 iobase = self->io.sir_base;
1025
1026 /* Update accounting for new speed */
1027 self->io.speed = speed;
1028
1029 /* Turn off interrupts */
1030 outb(0, iobase+UART_IER);
1031
1032 divisor = SMSC_IRCC2_MAX_SIR_SPEED/speed;
1033
1034 fcr = UART_FCR_ENABLE_FIFO;
1035
1036 /*
1037 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1038 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1039 * about this timeout since it will always be fast enough.
1040 */
1041 if (self->io.speed < 38400)
1042 fcr |= UART_FCR_TRIGGER_1;
1043 else
1044 fcr |= UART_FCR_TRIGGER_14;
1045
1046 /* IrDA ports use 8N1 */
1047 lcr = UART_LCR_WLEN8;
1048
1049 outb(UART_LCR_DLAB | lcr, iobase+UART_LCR); /* Set DLAB */
1050 outb(divisor & 0xff, iobase+UART_DLL); /* Set speed */
1051 outb(divisor >> 8, iobase+UART_DLM);
1052 outb(lcr, iobase+UART_LCR); /* Set 8N1 */
1053 outb(fcr, iobase+UART_FCR); /* Enable FIFO's */
1054
1055 /* Turn on interrups */
1056 outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, iobase+UART_IER);
1057
1058 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1059}
1060
1061
1062/*
1063 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1064 *
1065 * Transmit the frame!
1066 *
1067 */
1068static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1069{
1070 struct smsc_ircc_cb *self;
1071 unsigned long flags;
1072 s32 speed;
1073 int iobase;
1074 int mtt;
1075
1076 IRDA_ASSERT(dev != NULL, return 0;);
1077 self = (struct smsc_ircc_cb *) dev->priv;
1078 IRDA_ASSERT(self != NULL, return 0;);
1079
1080 iobase = self->io.fir_base;
1081
1082 netif_stop_queue(dev);
1083
1084 /* Make sure test of self->io.speed & speed change are atomic */
1085 spin_lock_irqsave(&self->lock, flags);
1086
1087 /* Check if we need to change the speed after this frame */
1088 speed = irda_get_next_speed(skb);
1089 if ((speed != self->io.speed) && (speed != -1)) {
1090 /* Check for empty frame */
1091 if (!skb->len) {
1092 /* Note : you should make sure that speed changes
1093 * are not going to corrupt any outgoing frame.
1094 * Look at nsc-ircc for the gory details - Jean II */
1095 smsc_ircc_change_speed(self, speed);
1096 spin_unlock_irqrestore(&self->lock, flags);
1097 dev_kfree_skb(skb);
1098 return 0;
1099 } else
1100 self->new_speed = speed;
1101 }
1102
1103 memcpy(self->tx_buff.head, skb->data, skb->len);
1104
1105 self->tx_buff.len = skb->len;
1106 self->tx_buff.data = self->tx_buff.head;
1107
1108 mtt = irda_get_mtt(skb);
1109 if (mtt) {
1110 int bofs;
1111
1112 /*
1113 * Compute how many BOFs (STA or PA's) we need to waste the
1114 * min turn time given the speed of the link.
1115 */
1116 bofs = mtt * (self->io.speed / 1000) / 8000;
1117 if (bofs > 4095)
1118 bofs = 4095;
1119
1120 smsc_ircc_dma_xmit(self, iobase, bofs);
1121 } else {
1122 /* Transmit frame */
1123 smsc_ircc_dma_xmit(self, iobase, 0);
1124 }
1125 spin_unlock_irqrestore(&self->lock, flags);
1126 dev_kfree_skb(skb);
1127
1128 return 0;
1129}
1130
1131/*
1132 * Function smsc_ircc_dma_xmit (self, iobase)
1133 *
1134 * Transmit data using DMA
1135 *
1136 */
1137static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs)
1138{
1139 u8 ctrl;
1140
1141 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1142#if 1
1143 /* Disable Rx */
1144 register_bank(iobase, 0);
1145 outb(0x00, iobase+IRCC_LCR_B);
1146#endif
1147 register_bank(iobase, 1);
1148 outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1149 iobase+IRCC_SCE_CFGB);
1150
1151 self->io.direction = IO_XMIT;
1152
1153 /* Set BOF additional count for generating the min turn time */
1154 register_bank(iobase, 4);
1155 outb(bofs & 0xff, iobase+IRCC_BOF_COUNT_LO);
1156 ctrl = inb(iobase+IRCC_CONTROL) & 0xf0;
1157 outb(ctrl | ((bofs >> 8) & 0x0f), iobase+IRCC_BOF_COUNT_HI);
1158
1159 /* Set max Tx frame size */
1160 outb(self->tx_buff.len >> 8, iobase+IRCC_TX_SIZE_HI);
1161 outb(self->tx_buff.len & 0xff, iobase+IRCC_TX_SIZE_LO);
1162
1163 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1164
1165 /* Enable burst mode chip Tx DMA */
1166 register_bank(iobase, 1);
1167 outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1168 IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);
1169
1170 /* Setup DMA controller (must be done after enabling chip DMA) */
1171 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1172 DMA_TX_MODE);
1173
1174 /* Enable interrupt */
1175
1176 register_bank(iobase, 0);
1177 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER);
1178 outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);
1179
1180 /* Enable transmit */
1181 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase+IRCC_LCR_B);
1182}
1183
1184/*
1185 * Function smsc_ircc_dma_xmit_complete (self)
1186 *
1187 * The transfer of a frame in finished. This function will only be called
1188 * by the interrupt handler
1189 *
1190 */
1191static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase)
1192{
1193 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1194#if 0
1195 /* Disable Tx */
1196 register_bank(iobase, 0);
1197 outb(0x00, iobase+IRCC_LCR_B);
1198#endif
1199 register_bank(self->io.fir_base, 1);
1200 outb(inb(self->io.fir_base+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1201 self->io.fir_base+IRCC_SCE_CFGB);
1202
1203 /* Check for underrun! */
1204 register_bank(iobase, 0);
1205 if (inb(iobase+IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1206 self->stats.tx_errors++;
1207 self->stats.tx_fifo_errors++;
1208
1209 /* Reset error condition */
1210 register_bank(iobase, 0);
1211 outb(IRCC_MASTER_ERROR_RESET, iobase+IRCC_MASTER);
1212 outb(0x00, iobase+IRCC_MASTER);
1213 } else {
1214 self->stats.tx_packets++;
1215 self->stats.tx_bytes += self->tx_buff.len;
1216 }
1217
1218 /* Check if it's time to change the speed */
1219 if (self->new_speed) {
1220 smsc_ircc_change_speed(self, self->new_speed);
1221 self->new_speed = 0;
1222 }
1223
1224 netif_wake_queue(self->netdev);
1225}
1226
1227/*
1228 * Function smsc_ircc_dma_receive(self)
1229 *
1230 * Get ready for receiving a frame. The device will initiate a DMA
1231 * if it starts to receive a frame.
1232 *
1233 */
1234static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase)
1235{
1236#if 0
1237 /* Turn off chip DMA */
1238 register_bank(iobase, 1);
1239 outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1240 iobase+IRCC_SCE_CFGB);
1241#endif
1242
1243 /* Disable Tx */
1244 register_bank(iobase, 0);
1245 outb(0x00, iobase+IRCC_LCR_B);
1246
1247 /* Turn off chip DMA */
1248 register_bank(iobase, 1);
1249 outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1250 iobase+IRCC_SCE_CFGB);
1251
1252 self->io.direction = IO_RECV;
1253 self->rx_buff.data = self->rx_buff.head;
1254
1255 /* Set max Rx frame size */
1256 register_bank(iobase, 4);
1257 outb((2050 >> 8) & 0x0f, iobase+IRCC_RX_SIZE_HI);
1258 outb(2050 & 0xff, iobase+IRCC_RX_SIZE_LO);
1259
1260 /* Setup DMA controller */
1261 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1262 DMA_RX_MODE);
1263
1264 /* Enable burst mode chip Rx DMA */
1265 register_bank(iobase, 1);
1266 outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1267 IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);
1268
1269 /* Enable interrupt */
1270 register_bank(iobase, 0);
1271 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER);
1272 outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);
1273
1274
1275 /* Enable receiver */
1276 register_bank(iobase, 0);
1277 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1278 iobase+IRCC_LCR_B);
1279
1280 return 0;
1281}
1282
1283/*
1284 * Function smsc_ircc_dma_receive_complete(self, iobase)
1285 *
1286 * Finished with receiving frames
1287 *
1288 */
1289static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase)
1290{
1291 struct sk_buff *skb;
1292 int len, msgcnt, lsr;
1293
1294 register_bank(iobase, 0);
1295
1296 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1297#if 0
1298 /* Disable Rx */
1299 register_bank(iobase, 0);
1300 outb(0x00, iobase+IRCC_LCR_B);
1301#endif
1302 register_bank(iobase, 0);
1303 outb(inb(iobase+IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase+IRCC_LSAR);
1304 lsr= inb(iobase+IRCC_LSR);
1305 msgcnt = inb(iobase+IRCC_LCR_B) & 0x08;
1306
1307 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1308 get_dma_residue(self->io.dma));
1309
1310 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1311
1312 /* Look for errors
1313 */
1314
1315 if(lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1316 self->stats.rx_errors++;
1317 if(lsr & IRCC_LSR_FRAME_ERROR) self->stats.rx_frame_errors++;
1318 if(lsr & IRCC_LSR_CRC_ERROR) self->stats.rx_crc_errors++;
1319 if(lsr & IRCC_LSR_SIZE_ERROR) self->stats.rx_length_errors++;
1320 if(lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) self->stats.rx_length_errors++;
1321 return;
1322 }
1323 /* Remove CRC */
1324 if (self->io.speed < 4000000)
1325 len -= 2;
1326 else
1327 len -= 4;
1328
1329 if ((len < 2) || (len > 2050)) {
1330 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1331 return;
1332 }
1333 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1334
1335 skb = dev_alloc_skb(len+1);
1336 if (!skb) {
1337 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1338 __FUNCTION__);
1339 return;
1340 }
1341 /* Make sure IP header gets aligned */
1342 skb_reserve(skb, 1);
1343
1344 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1345 self->stats.rx_packets++;
1346 self->stats.rx_bytes += len;
1347
1348 skb->dev = self->netdev;
1349 skb->mac.raw = skb->data;
1350 skb->protocol = htons(ETH_P_IRDA);
1351 netif_rx(skb);
1352}
1353
1354/*
1355 * Function smsc_ircc_sir_receive (self)
1356 *
1357 * Receive one frame from the infrared port
1358 *
1359 */
1360static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1361{
1362 int boguscount = 0;
1363 int iobase;
1364
1365 IRDA_ASSERT(self != NULL, return;);
1366
1367 iobase = self->io.sir_base;
1368
1369 /*
1370 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1371 * async_unwrap_char will deliver all found frames
1372 */
1373 do {
1374 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1375 inb(iobase+UART_RX));
1376
1377 /* Make sure we don't stay here to long */
1378 if (boguscount++ > 32) {
1379 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1380 break;
1381 }
1382 } while (inb(iobase+UART_LSR) & UART_LSR_DR);
1383}
1384
1385
1386/*
1387 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1388 *
1389 * An interrupt from the chip has arrived. Time to do some work
1390 *
1391 */
1392static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1393{
1394 struct net_device *dev = (struct net_device *) dev_id;
1395 struct smsc_ircc_cb *self;
1396 int iobase, iir, lcra, lsr;
1397 irqreturn_t ret = IRQ_NONE;
1398
1399 if (dev == NULL) {
1400 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1401 driver_name, irq);
1402 goto irq_ret;
1403 }
1404 self = (struct smsc_ircc_cb *) dev->priv;
1405 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1406
1407 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1408 spin_lock(&self->lock);
1409
1410 /* Check if we should use the SIR interrupt handler */
1411 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1412 ret = smsc_ircc_interrupt_sir(dev);
1413 goto irq_ret_unlock;
1414 }
1415
1416 iobase = self->io.fir_base;
1417
1418 register_bank(iobase, 0);
1419 iir = inb(iobase+IRCC_IIR);
1420 if (iir == 0)
1421 goto irq_ret_unlock;
1422 ret = IRQ_HANDLED;
1423
1424 /* Disable interrupts */
1425 outb(0, iobase+IRCC_IER);
1426 lcra = inb(iobase+IRCC_LCR_A);
1427 lsr = inb(iobase+IRCC_LSR);
1428
1429 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1430
1431 if (iir & IRCC_IIR_EOM) {
1432 if (self->io.direction == IO_RECV)
1433 smsc_ircc_dma_receive_complete(self, iobase);
1434 else
1435 smsc_ircc_dma_xmit_complete(self, iobase);
1436
1437 smsc_ircc_dma_receive(self, iobase);
1438 }
1439
1440 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1441 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1442 }
1443
1444 /* Enable interrupts again */
1445
1446 register_bank(iobase, 0);
1447 outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, iobase+IRCC_IER);
1448
1449 irq_ret_unlock:
1450 spin_unlock(&self->lock);
1451 irq_ret:
1452 return ret;
1453}
1454
1455/*
1456 * Function irport_interrupt_sir (irq, dev_id, regs)
1457 *
1458 * Interrupt handler for SIR modes
1459 */
1460static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1461{
1462 struct smsc_ircc_cb *self = dev->priv;
1463 int boguscount = 0;
1464 int iobase;
1465 int iir, lsr;
1466
1467 /* Already locked comming here in smsc_ircc_interrupt() */
1468 /*spin_lock(&self->lock);*/
1469
1470 iobase = self->io.sir_base;
1471
1472 iir = inb(iobase+UART_IIR) & UART_IIR_ID;
1473 if (iir == 0)
1474 return IRQ_NONE;
1475 while (iir) {
1476 /* Clear interrupt */
1477 lsr = inb(iobase+UART_LSR);
1478
1479 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1480 __FUNCTION__, iir, lsr, iobase);
1481
1482 switch (iir) {
1483 case UART_IIR_RLSI:
1484 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1485 break;
1486 case UART_IIR_RDI:
1487 /* Receive interrupt */
1488 smsc_ircc_sir_receive(self);
1489 break;
1490 case UART_IIR_THRI:
1491 if (lsr & UART_LSR_THRE)
1492 /* Transmitter ready for data */
1493 smsc_ircc_sir_write_wakeup(self);
1494 break;
1495 default:
1496 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1497 __FUNCTION__, iir);
1498 break;
1499 }
1500
1501 /* Make sure we don't stay here to long */
1502 if (boguscount++ > 100)
1503 break;
1504
1505 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1506 }
1507 /*spin_unlock(&self->lock);*/
1508 return IRQ_HANDLED;
1509}
1510
1511
1512#if 0 /* unused */
1513/*
1514 * Function ircc_is_receiving (self)
1515 *
1516 * Return TRUE is we are currently receiving a frame
1517 *
1518 */
1519static int ircc_is_receiving(struct smsc_ircc_cb *self)
1520{
1521 int status = FALSE;
1522 /* int iobase; */
1523
1524 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1525
1526 IRDA_ASSERT(self != NULL, return FALSE;);
1527
1528 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1529 get_dma_residue(self->io.dma));
1530
1531 status = (self->rx_buff.state != OUTSIDE_FRAME);
1532
1533 return status;
1534}
1535#endif /* unused */
1536
1537
1538/*
1539 * Function smsc_ircc_net_open (dev)
1540 *
1541 * Start the device
1542 *
1543 */
1544static int smsc_ircc_net_open(struct net_device *dev)
1545{
1546 struct smsc_ircc_cb *self;
1547 int iobase;
1548 char hwname[16];
1549 unsigned long flags;
1550
1551 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1552
1553 IRDA_ASSERT(dev != NULL, return -1;);
1554 self = (struct smsc_ircc_cb *) dev->priv;
1555 IRDA_ASSERT(self != NULL, return 0;);
1556
1557 iobase = self->io.fir_base;
1558
1559 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1560 (void *) dev)) {
1561 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1562 __FUNCTION__, self->io.irq);
1563 return -EAGAIN;
1564 }
1565
1566 spin_lock_irqsave(&self->lock, flags);
1567 /*smsc_ircc_sir_start(self);*/
1568 self->io.speed = 0;
1569 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1570 spin_unlock_irqrestore(&self->lock, flags);
1571
1572 /* Give self a hardware name */
1573 /* It would be cool to offer the chip revision here - Jean II */
1574 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1575
1576 /*
1577 * Open new IrLAP layer instance, now that everything should be
1578 * initialized properly
1579 */
1580 self->irlap = irlap_open(dev, &self->qos, hwname);
1581
1582 /*
1583 * Always allocate the DMA channel after the IRQ,
1584 * and clean up on failure.
1585 */
1586 if (request_dma(self->io.dma, dev->name)) {
1587 smsc_ircc_net_close(dev);
1588
1589 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1590 __FUNCTION__, self->io.dma);
1591 return -EAGAIN;
1592 }
1593
1594 netif_start_queue(dev);
1595
1596 return 0;
1597}
1598
1599/*
1600 * Function smsc_ircc_net_close (dev)
1601 *
1602 * Stop the device
1603 *
1604 */
1605static int smsc_ircc_net_close(struct net_device *dev)
1606{
1607 struct smsc_ircc_cb *self;
1608 int iobase;
1609
1610 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1611
1612 IRDA_ASSERT(dev != NULL, return -1;);
1613 self = (struct smsc_ircc_cb *) dev->priv;
1614 IRDA_ASSERT(self != NULL, return 0;);
1615
1616 iobase = self->io.fir_base;
1617
1618 /* Stop device */
1619 netif_stop_queue(dev);
1620
1621 /* Stop and remove instance of IrLAP */
1622 if (self->irlap)
1623 irlap_close(self->irlap);
1624 self->irlap = NULL;
1625
1626 free_irq(self->io.irq, dev);
1627
1628 disable_dma(self->io.dma);
1629
1630 free_dma(self->io.dma);
1631
1632 return 0;
1633}
1634
1635
1636static void smsc_ircc_suspend(struct smsc_ircc_cb *self)
1637{
1638 IRDA_MESSAGE("%s, Suspending\n", driver_name);
1639
1640 if (self->io.suspended)
1641 return;
1642
1643 smsc_ircc_net_close(self->netdev);
1644
1645 self->io.suspended = 1;
1646}
1647
1648static void smsc_ircc_wakeup(struct smsc_ircc_cb *self)
1649{
1650 if (!self->io.suspended)
1651 return;
1652
1653 /* The code was doing a "cli()" here, but this can't be right.
1654 * If you need protection, do it in net_open with a spinlock
1655 * or give a good reason. - Jean II */
1656
1657 smsc_ircc_net_open(self->netdev);
1658
1659 IRDA_MESSAGE("%s, Waking up\n", driver_name);
1660}
1661
1662static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data)
1663{
1664 struct smsc_ircc_cb *self = (struct smsc_ircc_cb*) dev->data;
1665 if (self) {
1666 switch (rqst) {
1667 case PM_SUSPEND:
1668 smsc_ircc_suspend(self);
1669 break;
1670 case PM_RESUME:
1671 smsc_ircc_wakeup(self);
1672 break;
1673 }
1674 }
1675 return 0;
1676}
1677
1678/*
1679 * Function smsc_ircc_close (self)
1680 *
1681 * Close driver instance
1682 *
1683 */
1684static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1685{
1686 int iobase;
1687 unsigned long flags;
1688
1689 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1690
1691 IRDA_ASSERT(self != NULL, return -1;);
1692
1693 iobase = self->io.fir_base;
1694
1695 if (self->pmdev)
1696 pm_unregister(self->pmdev);
1697
1698 /* Remove netdevice */
1699 unregister_netdev(self->netdev);
1700
1701 /* Make sure the irq handler is not exectuting */
1702 spin_lock_irqsave(&self->lock, flags);
1703
1704 /* Stop interrupts */
1705 register_bank(iobase, 0);
1706 outb(0, iobase+IRCC_IER);
1707 outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER);
1708 outb(0x00, iobase+IRCC_MASTER);
1709#if 0
1710 /* Reset to SIR mode */
1711 register_bank(iobase, 1);
1712 outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase+IRCC_SCE_CFGA);
1713 outb(IRCC_CFGB_IR, iobase+IRCC_SCE_CFGB);
1714#endif
1715 spin_unlock_irqrestore(&self->lock, flags);
1716
1717 /* Release the PORTS that this driver is using */
1718 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1719 self->io.fir_base);
1720
1721 release_region(self->io.fir_base, self->io.fir_ext);
1722
1723 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1724 self->io.sir_base);
1725
1726 release_region(self->io.sir_base, self->io.sir_ext);
1727
1728 if (self->tx_buff.head)
1729 dma_free_coherent(NULL, self->tx_buff.truesize,
1730 self->tx_buff.head, self->tx_buff_dma);
1731
1732 if (self->rx_buff.head)
1733 dma_free_coherent(NULL, self->rx_buff.truesize,
1734 self->rx_buff.head, self->rx_buff_dma);
1735
1736 free_netdev(self->netdev);
1737
1738 return 0;
1739}
1740
1741static void __exit smsc_ircc_cleanup(void)
1742{
1743 int i;
1744
1745 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1746
1747 for (i=0; i < 2; i++) {
1748 if (dev_self[i])
1749 smsc_ircc_close(dev_self[i]);
1750 }
1751}
1752
1753/*
1754 * Start SIR operations
1755 *
1756 * This function *must* be called with spinlock held, because it may
1757 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1758 */
1759void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1760{
1761 struct net_device *dev;
1762 int fir_base, sir_base;
1763
1764 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1765
1766 IRDA_ASSERT(self != NULL, return;);
1767 dev= self->netdev;
1768 IRDA_ASSERT(dev != NULL, return;);
1769 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1770
1771 fir_base = self->io.fir_base;
1772 sir_base = self->io.sir_base;
1773
1774 /* Reset everything */
1775 outb(IRCC_MASTER_RESET, fir_base+IRCC_MASTER);
1776
1777 #if SMSC_IRCC2_C_SIR_STOP
1778 /*smsc_ircc_sir_stop(self);*/
1779 #endif
1780
1781 register_bank(fir_base, 1);
1782 outb(((inb(fir_base+IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base+IRCC_SCE_CFGA);
1783
1784 /* Initialize UART */
1785 outb(UART_LCR_WLEN8, sir_base+UART_LCR); /* Reset DLAB */
1786 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base+UART_MCR);
1787
1788 /* Turn on interrups */
1789 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base+UART_IER);
1790
1791 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1792
1793 outb(0x00, fir_base+IRCC_MASTER);
1794}
1795
1796#if SMSC_IRCC2_C_SIR_STOP
1797void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1798{
1799 int iobase;
1800
1801 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1802 iobase = self->io.sir_base;
1803
1804 /* Reset UART */
1805 outb(0, iobase+UART_MCR);
1806
1807 /* Turn off interrupts */
1808 outb(0, iobase+UART_IER);
1809}
1810#endif
1811
1812/*
1813 * Function smsc_sir_write_wakeup (self)
1814 *
1815 * Called by the SIR interrupt handler when there's room for more data.
1816 * If we have more packets to send, we send them here.
1817 *
1818 */
1819static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1820{
1821 int actual = 0;
1822 int iobase;
1823 int fcr;
1824
1825 IRDA_ASSERT(self != NULL, return;);
1826
1827 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1828
1829 iobase = self->io.sir_base;
1830
1831 /* Finished with frame? */
1832 if (self->tx_buff.len > 0) {
1833 /* Write data left in transmit buffer */
1834 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1835 self->tx_buff.data, self->tx_buff.len);
1836 self->tx_buff.data += actual;
1837 self->tx_buff.len -= actual;
1838 } else {
1839
1840 /*if (self->tx_buff.len ==0) {*/
1841
1842 /*
1843 * Now serial buffer is almost free & we can start
1844 * transmission of another packet. But first we must check
1845 * if we need to change the speed of the hardware
1846 */
1847 if (self->new_speed) {
1848 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1849 __FUNCTION__, self->new_speed);
1850 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1851 smsc_ircc_change_speed(self, self->new_speed);
1852 self->new_speed = 0;
1853 } else {
1854 /* Tell network layer that we want more frames */
1855 netif_wake_queue(self->netdev);
1856 }
1857 self->stats.tx_packets++;
1858
1859 if(self->io.speed <= 115200) {
1860 /*
1861 * Reset Rx FIFO to make sure that all reflected transmit data
1862 * is discarded. This is needed for half duplex operation
1863 */
1864 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1865 if (self->io.speed < 38400)
1866 fcr |= UART_FCR_TRIGGER_1;
1867 else
1868 fcr |= UART_FCR_TRIGGER_14;
1869
1870 outb(fcr, iobase+UART_FCR);
1871
1872 /* Turn on receive interrupts */
1873 outb(UART_IER_RDI, iobase+UART_IER);
1874 }
1875 }
1876}
1877
1878/*
1879 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1880 *
1881 * Fill Tx FIFO with transmit data
1882 *
1883 */
1884static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1885{
1886 int actual = 0;
1887
1888 /* Tx FIFO should be empty! */
1889 if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) {
1890 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1891 return 0;
1892 }
1893
1894 /* Fill FIFO with current frame */
1895 while ((fifo_size-- > 0) && (actual < len)) {
1896 /* Transmit next byte */
1897 outb(buf[actual], iobase+UART_TX);
1898 actual++;
1899 }
1900 return actual;
1901}
1902
1903/*
1904 * Function smsc_ircc_is_receiving (self)
1905 *
1906 * Returns true is we are currently receiving data
1907 *
1908 */
1909static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1910{
1911 return (self->rx_buff.state != OUTSIDE_FRAME);
1912}
1913
1914
1915/*
1916 * Function smsc_ircc_probe_transceiver(self)
1917 *
1918 * Tries to find the used Transceiver
1919 *
1920 */
1921static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
1922{
1923 unsigned int i;
1924
1925 IRDA_ASSERT(self != NULL, return;);
1926
1927 for(i=0; smsc_transceivers[i].name!=NULL; i++)
1928 if((*smsc_transceivers[i].probe)(self->io.fir_base)) {
1929 IRDA_MESSAGE(" %s transceiver found\n",
1930 smsc_transceivers[i].name);
1931 self->transceiver= i+1;
1932 return;
1933 }
1934 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
1935 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
1936
1937 self->transceiver= SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1938}
1939
1940
1941/*
1942 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
1943 *
1944 * Set the transceiver according to the speed
1945 *
1946 */
1947static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
1948{
1949 unsigned int trx;
1950
1951 trx = self->transceiver;
1952 if(trx>0) (*smsc_transceivers[trx-1].set_for_speed)(self->io.fir_base, speed);
1953}
1954
1955/*
1956 * Function smsc_ircc_wait_hw_transmitter_finish ()
1957 *
1958 * Wait for the real end of HW transmission
1959 *
1960 * The UART is a strict FIFO, and we get called only when we have finished
1961 * pushing data to the FIFO, so the maximum amount of time we must wait
1962 * is only for the FIFO to drain out.
1963 *
1964 * We use a simple calibrated loop. We may need to adjust the loop
1965 * delay (udelay) to balance I/O traffic and latency. And we also need to
1966 * adjust the maximum timeout.
1967 * It would probably be better to wait for the proper interrupt,
1968 * but it doesn't seem to be available.
1969 *
1970 * We can't use jiffies or kernel timers because :
1971 * 1) We are called from the interrupt handler, which disable softirqs,
1972 * so jiffies won't be increased
1973 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
1974 * want to wait that long to detect stuck hardware.
1975 * Jean II
1976 */
1977
1978static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
1979{
1980 int iobase;
1981 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
1982
1983 iobase = self->io.sir_base;
1984
1985 /* Calibrated busy loop */
1986 while((count-- > 0) && !(inb(iobase+UART_LSR) & UART_LSR_TEMT))
1987 udelay(1);
1988
1989 if(count == 0)
1990 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
1991}
1992
1993
1994/* PROBING
1995 *
1996 *
1997 */
1998
1999static int __init smsc_ircc_look_for_chips(void)
2000{
2001 smsc_chip_address_t *address;
2002 char *type;
2003 unsigned int cfg_base, found;
2004
2005 found = 0;
2006 address = possible_addresses;
2007
2008 while(address->cfg_base){
2009 cfg_base = address->cfg_base;
2010
2011 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
2012
2013 if( address->type & SMSCSIO_TYPE_FDC){
2014 type = "FDC";
2015 if((address->type) & SMSCSIO_TYPE_FLAT) {
2016 if(!smsc_superio_flat(fdc_chips_flat,cfg_base, type)) found++;
2017 }
2018 if((address->type) & SMSCSIO_TYPE_PAGED) {
2019 if(!smsc_superio_paged(fdc_chips_paged,cfg_base, type)) found++;
2020 }
2021 }
2022 if( address->type & SMSCSIO_TYPE_LPC){
2023 type = "LPC";
2024 if((address->type) & SMSCSIO_TYPE_FLAT) {
2025 if(!smsc_superio_flat(lpc_chips_flat,cfg_base,type)) found++;
2026 }
2027 if((address->type) & SMSCSIO_TYPE_PAGED) {
2028 if(!smsc_superio_paged(lpc_chips_paged,cfg_base,"LPC")) found++;
2029 }
2030 }
2031 address++;
2032 }
2033 return found;
2034}
2035
2036/*
2037 * Function smsc_superio_flat (chip, base, type)
2038 *
2039 * Try to get configuration of a smc SuperIO chip with flat register model
2040 *
2041 */
2042static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfgbase, char *type)
2043{
2044 unsigned short firbase, sirbase;
2045 u8 mode, dma, irq;
2046 int ret = -ENODEV;
2047
2048 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2049
2050 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type)==NULL)
2051 return ret;
2052
2053 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2054 mode = inb(cfgbase+1);
2055
2056 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2057
2058 if(!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2059 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2060
2061 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2062 sirbase = inb(cfgbase+1) << 2;
2063
2064 /* FIR iobase */
2065 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2066 firbase = inb(cfgbase+1) << 3;
2067
2068 /* DMA */
2069 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2070 dma = inb(cfgbase+1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2071
2072 /* IRQ */
2073 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2074 irq = inb(cfgbase+1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2075
2076 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2077
2078 if (firbase) {
2079 if (smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2080 ret=0;
2081 }
2082
2083 /* Exit configuration */
2084 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2085
2086 return ret;
2087}
2088
2089/*
2090 * Function smsc_superio_paged (chip, base, type)
2091 *
2092 * Try to get configuration of a smc SuperIO chip with paged register model
2093 *
2094 */
2095static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type)
2096{
2097 unsigned short fir_io, sir_io;
2098 int ret = -ENODEV;
2099
2100 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2101
2102 if (smsc_ircc_probe(cfg_base,0x20,chips,type)==NULL)
2103 return ret;
2104
2105 /* Select logical device (UART2) */
2106 outb(0x07, cfg_base);
2107 outb(0x05, cfg_base + 1);
2108
2109 /* SIR iobase */
2110 outb(0x60, cfg_base);
2111 sir_io = inb(cfg_base + 1) << 8;
2112 outb(0x61, cfg_base);
2113 sir_io |= inb(cfg_base + 1);
2114
2115 /* Read FIR base */
2116 outb(0x62, cfg_base);
2117 fir_io = inb(cfg_base + 1) << 8;
2118 outb(0x63, cfg_base);
2119 fir_io |= inb(cfg_base + 1);
2120 outb(0x2b, cfg_base); /* ??? */
2121
2122 if (fir_io) {
2123 if (smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2124 ret=0;
2125 }
2126
2127 /* Exit configuration */
2128 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2129
2130 return ret;
2131}
2132
2133
2134static int __init smsc_access(unsigned short cfg_base,unsigned char reg)
2135{
2136 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2137
2138 outb(reg, cfg_base);
2139
2140 if (inb(cfg_base)!=reg)
2141 return -1;
2142
2143 return 0;
2144}
2145
2146static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg,const smsc_chip_t *chip,char *type)
2147{
2148 u8 devid,xdevid,rev;
2149
2150 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2151
2152 /* Leave configuration */
2153
2154 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2155
2156 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2157 return NULL;
2158
2159 outb(reg, cfg_base);
2160
2161 xdevid=inb(cfg_base+1);
2162
2163 /* Enter configuration */
2164
2165 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2166
2167 #if 0
2168 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2169 return NULL;
2170 #endif
2171
2172 /* probe device ID */
2173
2174 if (smsc_access(cfg_base,reg))
2175 return NULL;
2176
2177 devid=inb(cfg_base+1);
2178
2179 if (devid==0) /* typical value for unused port */
2180 return NULL;
2181
2182 if (devid==0xff) /* typical value for unused port */
2183 return NULL;
2184
2185 /* probe revision ID */
2186
2187 if (smsc_access(cfg_base,reg+1))
2188 return NULL;
2189
2190 rev=inb(cfg_base+1);
2191
2192 if (rev>=128) /* i think this will make no sense */
2193 return NULL;
2194
2195 if (devid==xdevid) /* protection against false positives */
2196 return NULL;
2197
2198 /* Check for expected device ID; are there others? */
2199
2200 while(chip->devid!=devid) {
2201
2202 chip++;
2203
2204 if (chip->name==NULL)
2205 return NULL;
2206 }
2207
2208 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",devid,rev,cfg_base,type,chip->name);
2209
2210 if (chip->rev>rev){
2211 IRDA_MESSAGE("Revision higher than expected\n");
2212 return NULL;
2213 }
2214
2215 if (chip->flags&NoIRDA)
2216 IRDA_MESSAGE("chipset does not support IRDA\n");
2217
2218 return chip;
2219}
2220
2221static int __init smsc_superio_fdc(unsigned short cfg_base)
2222{
2223 int ret = -1;
2224
2225 if (!request_region(cfg_base, 2, driver_name)) {
2226 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2227 __FUNCTION__, cfg_base);
2228 } else {
2229 if (!smsc_superio_flat(fdc_chips_flat,cfg_base,"FDC")
2230 ||!smsc_superio_paged(fdc_chips_paged,cfg_base,"FDC"))
2231 ret = 0;
2232
2233 release_region(cfg_base, 2);
2234 }
2235
2236 return ret;
2237}
2238
2239static int __init smsc_superio_lpc(unsigned short cfg_base)
2240{
2241 int ret = -1;
2242
2243 if (!request_region(cfg_base, 2, driver_name)) {
2244 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2245 __FUNCTION__, cfg_base);
2246 } else {
2247 if (!smsc_superio_flat(lpc_chips_flat,cfg_base,"LPC")
2248 ||!smsc_superio_paged(lpc_chips_paged,cfg_base,"LPC"))
2249 ret = 0;
2250 release_region(cfg_base, 2);
2251 }
2252 return ret;
2253}
2254
2255/************************************************
2256 *
2257 * Transceivers specific functions
2258 *
2259 ************************************************/
2260
2261
2262/*
2263 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2264 *
2265 * Program transceiver through smsc-ircc ATC circuitry
2266 *
2267 */
2268
2269static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2270{
2271 unsigned long jiffies_now, jiffies_timeout;
2272 u8 val;
2273
2274 jiffies_now= jiffies;
2275 jiffies_timeout= jiffies+SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2276
2277 /* ATC */
2278 register_bank(fir_base, 4);
2279 outb((inb(fir_base+IRCC_ATC) & IRCC_ATC_MASK) |IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, fir_base+IRCC_ATC);
2280 while((val=(inb(fir_base+IRCC_ATC) & IRCC_ATC_nPROGREADY)) && !time_after(jiffies, jiffies_timeout));
2281 if(val)
2282 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2283 inb(fir_base+IRCC_ATC));
2284}
2285
2286/*
2287 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2288 *
2289 * Probe transceiver smsc-ircc ATC circuitry
2290 *
2291 */
2292
2293static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2294{
2295 return 0;
2296}
2297
2298/*
2299 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2300 *
2301 * Set transceiver
2302 *
2303 */
2304
2305static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2306{
2307 u8 fast_mode;
2308
2309 switch(speed)
2310 {
2311 default:
2312 case 576000 :
2313 fast_mode = 0;
2314 break;
2315 case 1152000 :
2316 case 4000000 :
2317 fast_mode = IRCC_LCR_A_FAST;
2318 break;
2319
2320 }
2321 register_bank(fir_base, 0);
2322 outb((inb(fir_base+IRCC_LCR_A) & 0xbf) | fast_mode, fir_base+IRCC_LCR_A);
2323}
2324
2325/*
2326 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2327 *
2328 * Probe transceiver
2329 *
2330 */
2331
2332static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2333{
2334 return 0;
2335}
2336
2337/*
2338 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2339 *
2340 * Set transceiver
2341 *
2342 */
2343
2344static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2345{
2346 u8 fast_mode;
2347
2348 switch(speed)
2349 {
2350 default:
2351 case 576000 :
2352 fast_mode = 0;
2353 break;
2354 case 1152000 :
2355 case 4000000 :
2356 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2357 break;
2358
2359 }
2360 /* This causes an interrupt */
2361 register_bank(fir_base, 0);
2362 outb((inb(fir_base+IRCC_LCR_A) & 0xbf) | fast_mode, fir_base+IRCC_LCR_A);
2363}
2364
2365/*
2366 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2367 *
2368 * Probe transceiver
2369 *
2370 */
2371
2372static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2373{
2374 return 0;
2375}
2376
2377
2378module_init(smsc_ircc_init);
2379module_exit(smsc_ircc_cleanup);
2380
2381MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
2382MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
2383MODULE_LICENSE("GPL");
2384
2385module_param(ircc_dma, int, 0);
2386MODULE_PARM_DESC(ircc_dma, "DMA channel");
2387module_param(ircc_irq, int, 0);
2388MODULE_PARM_DESC(ircc_irq, "IRQ line");
2389module_param(ircc_fir, int, 0);
2390MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
2391module_param(ircc_sir, int, 0);
2392MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
2393module_param(ircc_cfg, int, 0);
2394MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
2395module_param(ircc_transceiver, int, 0);
2396MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 06:18:39 -0500