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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/ioc3-eth.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/ioc3-eth.c')
-rw-r--r--drivers/net/ioc3-eth.c1653
1 files changed, 1653 insertions, 0 deletions
diff --git a/drivers/net/ioc3-eth.c b/drivers/net/ioc3-eth.c
new file mode 100644
index 000000000000..d520b5920d6c
--- /dev/null
+++ b/drivers/net/ioc3-eth.c
@@ -0,0 +1,1653 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
7 *
8 * Copyright (C) 1999, 2000, 2001, 2003 Ralf Baechle
9 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
10 *
11 * References:
12 * o IOC3 ASIC specification 4.51, 1996-04-18
13 * o IEEE 802.3 specification, 2000 edition
14 * o DP38840A Specification, National Semiconductor, March 1997
15 *
16 * To do:
17 *
18 * o Handle allocation failures in ioc3_alloc_skb() more gracefully.
19 * o Handle allocation failures in ioc3_init_rings().
20 * o Use prefetching for large packets. What is a good lower limit for
21 * prefetching?
22 * o We're probably allocating a bit too much memory.
23 * o Use hardware checksums.
24 * o Convert to using a IOC3 meta driver.
25 * o Which PHYs might possibly be attached to the IOC3 in real live,
26 * which workarounds are required for them? Do we ever have Lucent's?
27 * o For the 2.5 branch kill the mii-tool ioctls.
28 */
29
30#define IOC3_NAME "ioc3-eth"
31#define IOC3_VERSION "2.6.3-3"
32
33#include <linux/config.h>
34#include <linux/init.h>
35#include <linux/delay.h>
36#include <linux/kernel.h>
37#include <linux/mm.h>
38#include <linux/errno.h>
39#include <linux/module.h>
40#include <linux/pci.h>
41#include <linux/crc32.h>
42#include <linux/mii.h>
43#include <linux/in.h>
44#include <linux/ip.h>
45#include <linux/tcp.h>
46#include <linux/udp.h>
47
48#ifdef CONFIG_SERIAL_8250
49#include <linux/serial.h>
50#include <asm/serial.h>
51#define IOC3_BAUD (22000000 / (3*16))
52#define IOC3_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
53#endif
54
55#include <linux/netdevice.h>
56#include <linux/etherdevice.h>
57#include <linux/ethtool.h>
58#include <linux/skbuff.h>
59#include <net/ip.h>
60
61#include <asm/byteorder.h>
62#include <asm/checksum.h>
63#include <asm/io.h>
64#include <asm/pgtable.h>
65#include <asm/uaccess.h>
66#include <asm/sn/types.h>
67#include <asm/sn/sn0/addrs.h>
68#include <asm/sn/sn0/hubni.h>
69#include <asm/sn/sn0/hubio.h>
70#include <asm/sn/klconfig.h>
71#include <asm/sn/ioc3.h>
72#include <asm/sn/sn0/ip27.h>
73#include <asm/pci/bridge.h>
74
75/*
76 * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The
77 * value must be a power of two.
78 */
79#define RX_BUFFS 64
80
81#define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21)
82#define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21)
83
84/* Private per NIC data of the driver. */
85struct ioc3_private {
86 struct ioc3 *regs;
87 unsigned long *rxr; /* pointer to receiver ring */
88 struct ioc3_etxd *txr;
89 struct sk_buff *rx_skbs[512];
90 struct sk_buff *tx_skbs[128];
91 struct net_device_stats stats;
92 int rx_ci; /* RX consumer index */
93 int rx_pi; /* RX producer index */
94 int tx_ci; /* TX consumer index */
95 int tx_pi; /* TX producer index */
96 int txqlen;
97 u32 emcr, ehar_h, ehar_l;
98 spinlock_t ioc3_lock;
99 struct mii_if_info mii;
100 struct pci_dev *pdev;
101
102 /* Members used by autonegotiation */
103 struct timer_list ioc3_timer;
104};
105
106static inline struct net_device *priv_netdev(struct ioc3_private *dev)
107{
108 return (void *)dev - ((sizeof(struct net_device) + 31) & ~31);
109}
110
111static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
112static void ioc3_set_multicast_list(struct net_device *dev);
113static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
114static void ioc3_timeout(struct net_device *dev);
115static inline unsigned int ioc3_hash(const unsigned char *addr);
116static inline void ioc3_stop(struct ioc3_private *ip);
117static void ioc3_init(struct net_device *dev);
118
119static const char ioc3_str[] = "IOC3 Ethernet";
120static struct ethtool_ops ioc3_ethtool_ops;
121
122/* We use this to acquire receive skb's that we can DMA directly into. */
123
124#define IOC3_CACHELINE 128UL
125
126static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
127{
128 return (~addr + 1) & (IOC3_CACHELINE - 1UL);
129}
130
131static inline struct sk_buff * ioc3_alloc_skb(unsigned long length,
132 unsigned int gfp_mask)
133{
134 struct sk_buff *skb;
135
136 skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
137 if (likely(skb)) {
138 int offset = aligned_rx_skb_addr((unsigned long) skb->data);
139 if (offset)
140 skb_reserve(skb, offset);
141 }
142
143 return skb;
144}
145
146static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
147{
148#ifdef CONFIG_SGI_IP27
149 vdev <<= 58; /* Shift to PCI64_ATTR_VIRTUAL */
150
151 return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
152 ((unsigned long)ptr & TO_PHYS_MASK);
153#else
154 return virt_to_bus(ptr);
155#endif
156}
157
158/* BEWARE: The IOC3 documentation documents the size of rx buffers as
159 1644 while it's actually 1664. This one was nasty to track down ... */
160#define RX_OFFSET 10
161#define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
162
163/* DMA barrier to separate cached and uncached accesses. */
164#define BARRIER() \
165 __asm__("sync" ::: "memory")
166
167
168#define IOC3_SIZE 0x100000
169
170/*
171 * IOC3 is a big endian device
172 *
173 * Unorthodox but makes the users of these macros more readable - the pointer
174 * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
175 * in the environment.
176 */
177#define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
178#define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
179#define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
180#define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
181#define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
182#define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
183#define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
184#define ioc3_r_eier() be32_to_cpu(ioc3->eier)
185#define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
186#define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
187#define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
188#define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
189#define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
190#define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
191#define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
192#define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
193#define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
194#define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
195#define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
196#define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
197#define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
198#define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
199#define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
200#define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
201#define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
202#define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
203#define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
204#define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
205#define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
206#define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
207#define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
208#define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
209#define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
210#define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
211#define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
212#define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
213#define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
214#define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
215#define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
216#define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
217#define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
218#define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
219#define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
220#define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
221#define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
222#define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
223#define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
224#define ioc3_r_micr() be32_to_cpu(ioc3->micr)
225#define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
226#define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
227#define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
228#define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
229#define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
230
231static inline u32 mcr_pack(u32 pulse, u32 sample)
232{
233 return (pulse << 10) | (sample << 2);
234}
235
236static int nic_wait(struct ioc3 *ioc3)
237{
238 u32 mcr;
239
240 do {
241 mcr = ioc3_r_mcr();
242 } while (!(mcr & 2));
243
244 return mcr & 1;
245}
246
247static int nic_reset(struct ioc3 *ioc3)
248{
249 int presence;
250
251 ioc3_w_mcr(mcr_pack(500, 65));
252 presence = nic_wait(ioc3);
253
254 ioc3_w_mcr(mcr_pack(0, 500));
255 nic_wait(ioc3);
256
257 return presence;
258}
259
260static inline int nic_read_bit(struct ioc3 *ioc3)
261{
262 int result;
263
264 ioc3_w_mcr(mcr_pack(6, 13));
265 result = nic_wait(ioc3);
266 ioc3_w_mcr(mcr_pack(0, 100));
267 nic_wait(ioc3);
268
269 return result;
270}
271
272static inline void nic_write_bit(struct ioc3 *ioc3, int bit)
273{
274 if (bit)
275 ioc3_w_mcr(mcr_pack(6, 110));
276 else
277 ioc3_w_mcr(mcr_pack(80, 30));
278
279 nic_wait(ioc3);
280}
281
282/*
283 * Read a byte from an iButton device
284 */
285static u32 nic_read_byte(struct ioc3 *ioc3)
286{
287 u32 result = 0;
288 int i;
289
290 for (i = 0; i < 8; i++)
291 result = (result >> 1) | (nic_read_bit(ioc3) << 7);
292
293 return result;
294}
295
296/*
297 * Write a byte to an iButton device
298 */
299static void nic_write_byte(struct ioc3 *ioc3, int byte)
300{
301 int i, bit;
302
303 for (i = 8; i; i--) {
304 bit = byte & 1;
305 byte >>= 1;
306
307 nic_write_bit(ioc3, bit);
308 }
309}
310
311static u64 nic_find(struct ioc3 *ioc3, int *last)
312{
313 int a, b, index, disc;
314 u64 address = 0;
315
316 nic_reset(ioc3);
317 /* Search ROM. */
318 nic_write_byte(ioc3, 0xf0);
319
320 /* Algorithm from ``Book of iButton Standards''. */
321 for (index = 0, disc = 0; index < 64; index++) {
322 a = nic_read_bit(ioc3);
323 b = nic_read_bit(ioc3);
324
325 if (a && b) {
326 printk("NIC search failed (not fatal).\n");
327 *last = 0;
328 return 0;
329 }
330
331 if (!a && !b) {
332 if (index == *last) {
333 address |= 1UL << index;
334 } else if (index > *last) {
335 address &= ~(1UL << index);
336 disc = index;
337 } else if ((address & (1UL << index)) == 0)
338 disc = index;
339 nic_write_bit(ioc3, address & (1UL << index));
340 continue;
341 } else {
342 if (a)
343 address |= 1UL << index;
344 else
345 address &= ~(1UL << index);
346 nic_write_bit(ioc3, a);
347 continue;
348 }
349 }
350
351 *last = disc;
352
353 return address;
354}
355
356static int nic_init(struct ioc3 *ioc3)
357{
358 const char *type;
359 u8 crc;
360 u8 serial[6];
361 int save = 0, i;
362
363 type = "unknown";
364
365 while (1) {
366 u64 reg;
367 reg = nic_find(ioc3, &save);
368
369 switch (reg & 0xff) {
370 case 0x91:
371 type = "DS1981U";
372 break;
373 default:
374 if (save == 0) {
375 /* Let the caller try again. */
376 return -1;
377 }
378 continue;
379 }
380
381 nic_reset(ioc3);
382
383 /* Match ROM. */
384 nic_write_byte(ioc3, 0x55);
385 for (i = 0; i < 8; i++)
386 nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
387
388 reg >>= 8; /* Shift out type. */
389 for (i = 0; i < 6; i++) {
390 serial[i] = reg & 0xff;
391 reg >>= 8;
392 }
393 crc = reg & 0xff;
394 break;
395 }
396
397 printk("Found %s NIC", type);
398 if (type != "unknown") {
399 printk (" registration number %02x:%02x:%02x:%02x:%02x:%02x,"
400 " CRC %02x", serial[0], serial[1], serial[2],
401 serial[3], serial[4], serial[5], crc);
402 }
403 printk(".\n");
404
405 return 0;
406}
407
408/*
409 * Read the NIC (Number-In-a-Can) device used to store the MAC address on
410 * SN0 / SN00 nodeboards and PCI cards.
411 */
412static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
413{
414 struct ioc3 *ioc3 = ip->regs;
415 u8 nic[14];
416 int tries = 2; /* There may be some problem with the battery? */
417 int i;
418
419 ioc3_w_gpcr_s(1 << 21);
420
421 while (tries--) {
422 if (!nic_init(ioc3))
423 break;
424 udelay(500);
425 }
426
427 if (tries < 0) {
428 printk("Failed to read MAC address\n");
429 return;
430 }
431
432 /* Read Memory. */
433 nic_write_byte(ioc3, 0xf0);
434 nic_write_byte(ioc3, 0x00);
435 nic_write_byte(ioc3, 0x00);
436
437 for (i = 13; i >= 0; i--)
438 nic[i] = nic_read_byte(ioc3);
439
440 for (i = 2; i < 8; i++)
441 priv_netdev(ip)->dev_addr[i - 2] = nic[i];
442}
443
444/*
445 * Ok, this is hosed by design. It's necessary to know what machine the
446 * NIC is in in order to know how to read the NIC address. We also have
447 * to know if it's a PCI card or a NIC in on the node board ...
448 */
449static void ioc3_get_eaddr(struct ioc3_private *ip)
450{
451 int i;
452
453
454 ioc3_get_eaddr_nic(ip);
455
456 printk("Ethernet address is ");
457 for (i = 0; i < 6; i++) {
458 printk("%02x", priv_netdev(ip)->dev_addr[i]);
459 if (i < 5)
460 printk(":");
461 }
462 printk(".\n");
463}
464
465static void __ioc3_set_mac_address(struct net_device *dev)
466{
467 struct ioc3_private *ip = netdev_priv(dev);
468 struct ioc3 *ioc3 = ip->regs;
469
470 ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]);
471 ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) |
472 (dev->dev_addr[1] << 8) | dev->dev_addr[0]);
473}
474
475static int ioc3_set_mac_address(struct net_device *dev, void *addr)
476{
477 struct ioc3_private *ip = netdev_priv(dev);
478 struct sockaddr *sa = addr;
479
480 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
481
482 spin_lock_irq(&ip->ioc3_lock);
483 __ioc3_set_mac_address(dev);
484 spin_unlock_irq(&ip->ioc3_lock);
485
486 return 0;
487}
488
489/*
490 * Caller must hold the ioc3_lock ever for MII readers. This is also
491 * used to protect the transmitter side but it's low contention.
492 */
493static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
494{
495 struct ioc3_private *ip = netdev_priv(dev);
496 struct ioc3 *ioc3 = ip->regs;
497
498 while (ioc3_r_micr() & MICR_BUSY);
499 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG);
500 while (ioc3_r_micr() & MICR_BUSY);
501
502 return ioc3_r_micr() & MIDR_DATA_MASK;
503}
504
505static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
506{
507 struct ioc3_private *ip = netdev_priv(dev);
508 struct ioc3 *ioc3 = ip->regs;
509
510 while (ioc3_r_micr() & MICR_BUSY);
511 ioc3_w_midr_w(data);
512 ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg);
513 while (ioc3_r_micr() & MICR_BUSY);
514}
515
516static int ioc3_mii_init(struct ioc3_private *ip);
517
518static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
519{
520 struct ioc3_private *ip = netdev_priv(dev);
521 struct ioc3 *ioc3 = ip->regs;
522
523 ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK);
524 return &ip->stats;
525}
526
527#ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
528
529static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
530{
531 struct ethhdr *eh = eth_hdr(skb);
532 uint32_t csum, ehsum;
533 unsigned int proto;
534 struct iphdr *ih;
535 uint16_t *ew;
536 unsigned char *cp;
537
538 /*
539 * Did hardware handle the checksum at all? The cases we can handle
540 * are:
541 *
542 * - TCP and UDP checksums of IPv4 only.
543 * - IPv6 would be doable but we keep that for later ...
544 * - Only unfragmented packets. Did somebody already tell you
545 * fragmentation is evil?
546 * - don't care about packet size. Worst case when processing a
547 * malformed packet we'll try to access the packet at ip header +
548 * 64 bytes which is still inside the skb. Even in the unlikely
549 * case where the checksum is right the higher layers will still
550 * drop the packet as appropriate.
551 */
552 if (eh->h_proto != ntohs(ETH_P_IP))
553 return;
554
555 ih = (struct iphdr *) ((char *)eh + ETH_HLEN);
556 if (ih->frag_off & htons(IP_MF | IP_OFFSET))
557 return;
558
559 proto = ih->protocol;
560 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
561 return;
562
563 /* Same as tx - compute csum of pseudo header */
564 csum = hwsum +
565 (ih->tot_len - (ih->ihl << 2)) +
566 htons((uint16_t)ih->protocol) +
567 (ih->saddr >> 16) + (ih->saddr & 0xffff) +
568 (ih->daddr >> 16) + (ih->daddr & 0xffff);
569
570 /* Sum up ethernet dest addr, src addr and protocol */
571 ew = (uint16_t *) eh;
572 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
573
574 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
575 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
576
577 csum += 0xffff ^ ehsum;
578
579 /* In the next step we also subtract the 1's complement
580 checksum of the trailing ethernet CRC. */
581 cp = (char *)eh + len; /* points at trailing CRC */
582 if (len & 1) {
583 csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]);
584 csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]);
585 } else {
586 csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]);
587 csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]);
588 }
589
590 csum = (csum & 0xffff) + (csum >> 16);
591 csum = (csum & 0xffff) + (csum >> 16);
592
593 if (csum == 0xffff)
594 skb->ip_summed = CHECKSUM_UNNECESSARY;
595}
596#endif /* CONFIG_SGI_IOC3_ETH_HW_RX_CSUM */
597
598static inline void ioc3_rx(struct ioc3_private *ip)
599{
600 struct sk_buff *skb, *new_skb;
601 struct ioc3 *ioc3 = ip->regs;
602 int rx_entry, n_entry, len;
603 struct ioc3_erxbuf *rxb;
604 unsigned long *rxr;
605 u32 w0, err;
606
607 rxr = (unsigned long *) ip->rxr; /* Ring base */
608 rx_entry = ip->rx_ci; /* RX consume index */
609 n_entry = ip->rx_pi;
610
611 skb = ip->rx_skbs[rx_entry];
612 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
613 w0 = be32_to_cpu(rxb->w0);
614
615 while (w0 & ERXBUF_V) {
616 err = be32_to_cpu(rxb->err); /* It's valid ... */
617 if (err & ERXBUF_GOODPKT) {
618 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
619 skb_trim(skb, len);
620 skb->protocol = eth_type_trans(skb, priv_netdev(ip));
621
622 new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
623 if (!new_skb) {
624 /* Ouch, drop packet and just recycle packet
625 to keep the ring filled. */
626 ip->stats.rx_dropped++;
627 new_skb = skb;
628 goto next;
629 }
630
631#ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
632 ioc3_tcpudp_checksum(skb, w0 & ERXBUF_IPCKSUM_MASK,len);
633#endif
634
635 netif_rx(skb);
636
637 ip->rx_skbs[rx_entry] = NULL; /* Poison */
638
639 new_skb->dev = priv_netdev(ip);
640
641 /* Because we reserve afterwards. */
642 skb_put(new_skb, (1664 + RX_OFFSET));
643 rxb = (struct ioc3_erxbuf *) new_skb->data;
644 skb_reserve(new_skb, RX_OFFSET);
645
646 priv_netdev(ip)->last_rx = jiffies;
647 ip->stats.rx_packets++; /* Statistics */
648 ip->stats.rx_bytes += len;
649 } else {
650 /* The frame is invalid and the skb never
651 reached the network layer so we can just
652 recycle it. */
653 new_skb = skb;
654 ip->stats.rx_errors++;
655 }
656 if (err & ERXBUF_CRCERR) /* Statistics */
657 ip->stats.rx_crc_errors++;
658 if (err & ERXBUF_FRAMERR)
659 ip->stats.rx_frame_errors++;
660next:
661 ip->rx_skbs[n_entry] = new_skb;
662 rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
663 rxb->w0 = 0; /* Clear valid flag */
664 n_entry = (n_entry + 1) & 511; /* Update erpir */
665
666 /* Now go on to the next ring entry. */
667 rx_entry = (rx_entry + 1) & 511;
668 skb = ip->rx_skbs[rx_entry];
669 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
670 w0 = be32_to_cpu(rxb->w0);
671 }
672 ioc3_w_erpir((n_entry << 3) | ERPIR_ARM);
673 ip->rx_pi = n_entry;
674 ip->rx_ci = rx_entry;
675}
676
677static inline void ioc3_tx(struct ioc3_private *ip)
678{
679 unsigned long packets, bytes;
680 struct ioc3 *ioc3 = ip->regs;
681 int tx_entry, o_entry;
682 struct sk_buff *skb;
683 u32 etcir;
684
685 spin_lock(&ip->ioc3_lock);
686 etcir = ioc3_r_etcir();
687
688 tx_entry = (etcir >> 7) & 127;
689 o_entry = ip->tx_ci;
690 packets = 0;
691 bytes = 0;
692
693 while (o_entry != tx_entry) {
694 packets++;
695 skb = ip->tx_skbs[o_entry];
696 bytes += skb->len;
697 dev_kfree_skb_irq(skb);
698 ip->tx_skbs[o_entry] = NULL;
699
700 o_entry = (o_entry + 1) & 127; /* Next */
701
702 etcir = ioc3_r_etcir(); /* More pkts sent? */
703 tx_entry = (etcir >> 7) & 127;
704 }
705
706 ip->stats.tx_packets += packets;
707 ip->stats.tx_bytes += bytes;
708 ip->txqlen -= packets;
709
710 if (ip->txqlen < 128)
711 netif_wake_queue(priv_netdev(ip));
712
713 ip->tx_ci = o_entry;
714 spin_unlock(&ip->ioc3_lock);
715}
716
717/*
718 * Deal with fatal IOC3 errors. This condition might be caused by a hard or
719 * software problems, so we should try to recover
720 * more gracefully if this ever happens. In theory we might be flooded
721 * with such error interrupts if something really goes wrong, so we might
722 * also consider to take the interface down.
723 */
724static void ioc3_error(struct ioc3_private *ip, u32 eisr)
725{
726 struct net_device *dev = priv_netdev(ip);
727 unsigned char *iface = dev->name;
728
729 spin_lock(&ip->ioc3_lock);
730
731 if (eisr & EISR_RXOFLO)
732 printk(KERN_ERR "%s: RX overflow.\n", iface);
733 if (eisr & EISR_RXBUFOFLO)
734 printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
735 if (eisr & EISR_RXMEMERR)
736 printk(KERN_ERR "%s: RX PCI error.\n", iface);
737 if (eisr & EISR_RXPARERR)
738 printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
739 if (eisr & EISR_TXBUFUFLO)
740 printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
741 if (eisr & EISR_TXMEMERR)
742 printk(KERN_ERR "%s: TX PCI error.\n", iface);
743
744 ioc3_stop(ip);
745 ioc3_init(dev);
746 ioc3_mii_init(ip);
747
748 netif_wake_queue(dev);
749
750 spin_unlock(&ip->ioc3_lock);
751}
752
753/* The interrupt handler does all of the Rx thread work and cleans up
754 after the Tx thread. */
755static irqreturn_t ioc3_interrupt(int irq, void *_dev, struct pt_regs *regs)
756{
757 struct net_device *dev = (struct net_device *)_dev;
758 struct ioc3_private *ip = netdev_priv(dev);
759 struct ioc3 *ioc3 = ip->regs;
760 const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
761 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
762 EISR_TXEXPLICIT | EISR_TXMEMERR;
763 u32 eisr;
764
765 eisr = ioc3_r_eisr() & enabled;
766
767 ioc3_w_eisr(eisr);
768 (void) ioc3_r_eisr(); /* Flush */
769
770 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
771 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
772 ioc3_error(ip, eisr);
773 if (eisr & EISR_RXTIMERINT)
774 ioc3_rx(ip);
775 if (eisr & EISR_TXEXPLICIT)
776 ioc3_tx(ip);
777
778 return IRQ_HANDLED;
779}
780
781static inline void ioc3_setup_duplex(struct ioc3_private *ip)
782{
783 struct ioc3 *ioc3 = ip->regs;
784
785 if (ip->mii.full_duplex) {
786 ioc3_w_etcsr(ETCSR_FD);
787 ip->emcr |= EMCR_DUPLEX;
788 } else {
789 ioc3_w_etcsr(ETCSR_HD);
790 ip->emcr &= ~EMCR_DUPLEX;
791 }
792 ioc3_w_emcr(ip->emcr);
793}
794
795static void ioc3_timer(unsigned long data)
796{
797 struct ioc3_private *ip = (struct ioc3_private *) data;
798
799 /* Print the link status if it has changed */
800 mii_check_media(&ip->mii, 1, 0);
801 ioc3_setup_duplex(ip);
802
803 ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2s */
804 add_timer(&ip->ioc3_timer);
805}
806
807/*
808 * Try to find a PHY. There is no apparent relation between the MII addresses
809 * in the SGI documentation and what we find in reality, so we simply probe
810 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
811 * onboard IOC3s has the special oddity that probing doesn't seem to find it
812 * yet the interface seems to work fine, so if probing fails we for now will
813 * simply default to PHY 31 instead of bailing out.
814 */
815static int ioc3_mii_init(struct ioc3_private *ip)
816{
817 struct net_device *dev = priv_netdev(ip);
818 int i, found = 0, res = 0;
819 int ioc3_phy_workaround = 1;
820 u16 word;
821
822 for (i = 0; i < 32; i++) {
823 word = ioc3_mdio_read(dev, i, MII_PHYSID1);
824
825 if (word != 0xffff && word != 0x0000) {
826 found = 1;
827 break; /* Found a PHY */
828 }
829 }
830
831 if (!found) {
832 if (ioc3_phy_workaround)
833 i = 31;
834 else {
835 ip->mii.phy_id = -1;
836 res = -ENODEV;
837 goto out;
838 }
839 }
840
841 ip->mii.phy_id = i;
842 ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
843 ip->ioc3_timer.data = (unsigned long) ip;
844 ip->ioc3_timer.function = &ioc3_timer;
845 add_timer(&ip->ioc3_timer);
846
847out:
848 return res;
849}
850
851static inline void ioc3_clean_rx_ring(struct ioc3_private *ip)
852{
853 struct sk_buff *skb;
854 int i;
855
856 for (i = ip->rx_ci; i & 15; i++) {
857 ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
858 ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
859 }
860 ip->rx_pi &= 511;
861 ip->rx_ci &= 511;
862
863 for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) {
864 struct ioc3_erxbuf *rxb;
865 skb = ip->rx_skbs[i];
866 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
867 rxb->w0 = 0;
868 }
869}
870
871static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
872{
873 struct sk_buff *skb;
874 int i;
875
876 for (i=0; i < 128; i++) {
877 skb = ip->tx_skbs[i];
878 if (skb) {
879 ip->tx_skbs[i] = NULL;
880 dev_kfree_skb_any(skb);
881 }
882 ip->txr[i].cmd = 0;
883 }
884 ip->tx_pi = 0;
885 ip->tx_ci = 0;
886}
887
888static void ioc3_free_rings(struct ioc3_private *ip)
889{
890 struct sk_buff *skb;
891 int rx_entry, n_entry;
892
893 if (ip->txr) {
894 ioc3_clean_tx_ring(ip);
895 free_pages((unsigned long)ip->txr, 2);
896 ip->txr = NULL;
897 }
898
899 if (ip->rxr) {
900 n_entry = ip->rx_ci;
901 rx_entry = ip->rx_pi;
902
903 while (n_entry != rx_entry) {
904 skb = ip->rx_skbs[n_entry];
905 if (skb)
906 dev_kfree_skb_any(skb);
907
908 n_entry = (n_entry + 1) & 511;
909 }
910 free_page((unsigned long)ip->rxr);
911 ip->rxr = NULL;
912 }
913}
914
915static void ioc3_alloc_rings(struct net_device *dev)
916{
917 struct ioc3_private *ip = netdev_priv(dev);
918 struct ioc3_erxbuf *rxb;
919 unsigned long *rxr;
920 int i;
921
922 if (ip->rxr == NULL) {
923 /* Allocate and initialize rx ring. 4kb = 512 entries */
924 ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC);
925 rxr = (unsigned long *) ip->rxr;
926 if (!rxr)
927 printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
928
929 /* Now the rx buffers. The RX ring may be larger but
930 we only allocate 16 buffers for now. Need to tune
931 this for performance and memory later. */
932 for (i = 0; i < RX_BUFFS; i++) {
933 struct sk_buff *skb;
934
935 skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
936 if (!skb) {
937 show_free_areas();
938 continue;
939 }
940
941 ip->rx_skbs[i] = skb;
942 skb->dev = dev;
943
944 /* Because we reserve afterwards. */
945 skb_put(skb, (1664 + RX_OFFSET));
946 rxb = (struct ioc3_erxbuf *) skb->data;
947 rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
948 skb_reserve(skb, RX_OFFSET);
949 }
950 ip->rx_ci = 0;
951 ip->rx_pi = RX_BUFFS;
952 }
953
954 if (ip->txr == NULL) {
955 /* Allocate and initialize tx rings. 16kb = 128 bufs. */
956 ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
957 if (!ip->txr)
958 printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
959 ip->tx_pi = 0;
960 ip->tx_ci = 0;
961 }
962}
963
964static void ioc3_init_rings(struct net_device *dev)
965{
966 struct ioc3_private *ip = netdev_priv(dev);
967 struct ioc3 *ioc3 = ip->regs;
968 unsigned long ring;
969
970 ioc3_free_rings(ip);
971 ioc3_alloc_rings(dev);
972
973 ioc3_clean_rx_ring(ip);
974 ioc3_clean_tx_ring(ip);
975
976 /* Now the rx ring base, consume & produce registers. */
977 ring = ioc3_map(ip->rxr, 0);
978 ioc3_w_erbr_h(ring >> 32);
979 ioc3_w_erbr_l(ring & 0xffffffff);
980 ioc3_w_ercir(ip->rx_ci << 3);
981 ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM);
982
983 ring = ioc3_map(ip->txr, 0);
984
985 ip->txqlen = 0; /* nothing queued */
986
987 /* Now the tx ring base, consume & produce registers. */
988 ioc3_w_etbr_h(ring >> 32);
989 ioc3_w_etbr_l(ring & 0xffffffff);
990 ioc3_w_etpir(ip->tx_pi << 7);
991 ioc3_w_etcir(ip->tx_ci << 7);
992 (void) ioc3_r_etcir(); /* Flush */
993}
994
995static inline void ioc3_ssram_disc(struct ioc3_private *ip)
996{
997 struct ioc3 *ioc3 = ip->regs;
998 volatile u32 *ssram0 = &ioc3->ssram[0x0000];
999 volatile u32 *ssram1 = &ioc3->ssram[0x4000];
1000 unsigned int pattern = 0x5555;
1001
1002 /* Assume the larger size SSRAM and enable parity checking */
1003 ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR));
1004
1005 *ssram0 = pattern;
1006 *ssram1 = ~pattern & IOC3_SSRAM_DM;
1007
1008 if ((*ssram0 & IOC3_SSRAM_DM) != pattern ||
1009 (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
1010 /* set ssram size to 64 KB */
1011 ip->emcr = EMCR_RAMPAR;
1012 ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ);
1013 } else
1014 ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR;
1015}
1016
1017static void ioc3_init(struct net_device *dev)
1018{
1019 struct ioc3_private *ip = netdev_priv(dev);
1020 struct ioc3 *ioc3 = ip->regs;
1021
1022 del_timer(&ip->ioc3_timer); /* Kill if running */
1023
1024 ioc3_w_emcr(EMCR_RST); /* Reset */
1025 (void) ioc3_r_emcr(); /* Flush WB */
1026 udelay(4); /* Give it time ... */
1027 ioc3_w_emcr(0);
1028 (void) ioc3_r_emcr();
1029
1030 /* Misc registers */
1031#ifdef CONFIG_SGI_IP27
1032 ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */
1033#else
1034 ioc3_w_erbar(0); /* Let PCI API get it right */
1035#endif
1036 (void) ioc3_r_etcdc(); /* Clear on read */
1037 ioc3_w_ercsr(15); /* RX low watermark */
1038 ioc3_w_ertr(0); /* Interrupt immediately */
1039 __ioc3_set_mac_address(dev);
1040 ioc3_w_ehar_h(ip->ehar_h);
1041 ioc3_w_ehar_l(ip->ehar_l);
1042 ioc3_w_ersr(42); /* XXX should be random */
1043
1044 ioc3_init_rings(dev);
1045
1046 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
1047 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
1048 ioc3_w_emcr(ip->emcr);
1049 ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
1050 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
1051 EISR_TXEXPLICIT | EISR_TXMEMERR);
1052 (void) ioc3_r_eier();
1053}
1054
1055static inline void ioc3_stop(struct ioc3_private *ip)
1056{
1057 struct ioc3 *ioc3 = ip->regs;
1058
1059 ioc3_w_emcr(0); /* Shutup */
1060 ioc3_w_eier(0); /* Disable interrupts */
1061 (void) ioc3_r_eier(); /* Flush */
1062}
1063
1064static int ioc3_open(struct net_device *dev)
1065{
1066 struct ioc3_private *ip = netdev_priv(dev);
1067
1068 if (request_irq(dev->irq, ioc3_interrupt, SA_SHIRQ, ioc3_str, dev)) {
1069 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
1070
1071 return -EAGAIN;
1072 }
1073
1074 ip->ehar_h = 0;
1075 ip->ehar_l = 0;
1076 ioc3_init(dev);
1077
1078 netif_start_queue(dev);
1079 return 0;
1080}
1081
1082static int ioc3_close(struct net_device *dev)
1083{
1084 struct ioc3_private *ip = netdev_priv(dev);
1085
1086 del_timer(&ip->ioc3_timer);
1087
1088 netif_stop_queue(dev);
1089
1090 ioc3_stop(ip);
1091 free_irq(dev->irq, dev);
1092
1093 ioc3_free_rings(ip);
1094 return 0;
1095}
1096
1097/*
1098 * MENET cards have four IOC3 chips, which are attached to two sets of
1099 * PCI slot resources each: the primary connections are on slots
1100 * 0..3 and the secondaries are on 4..7
1101 *
1102 * All four ethernets are brought out to connectors; six serial ports
1103 * (a pair from each of the first three IOC3s) are brought out to
1104 * MiniDINs; all other subdevices are left swinging in the wind, leave
1105 * them disabled.
1106 */
1107static inline int ioc3_is_menet(struct pci_dev *pdev)
1108{
1109 struct pci_dev *dev;
1110
1111 return pdev->bus->parent == NULL
1112 && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(0, 0)))
1113 && dev->vendor == PCI_VENDOR_ID_SGI
1114 && dev->device == PCI_DEVICE_ID_SGI_IOC3
1115 && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(1, 0)))
1116 && dev->vendor == PCI_VENDOR_ID_SGI
1117 && dev->device == PCI_DEVICE_ID_SGI_IOC3
1118 && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(2, 0)))
1119 && dev->vendor == PCI_VENDOR_ID_SGI
1120 && dev->device == PCI_DEVICE_ID_SGI_IOC3;
1121}
1122
1123#ifdef CONFIG_SERIAL_8250
1124/*
1125 * Note about serial ports and consoles:
1126 * For console output, everyone uses the IOC3 UARTA (offset 0x178)
1127 * connected to the master node (look in ip27_setup_console() and
1128 * ip27prom_console_write()).
1129 *
1130 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
1131 * addresses on a partitioned machine. Since we currently use the ioc3
1132 * serial ports, we use dynamic serial port discovery that the serial.c
1133 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1134 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
1135 * than UARTB's, although UARTA on o200s has traditionally been known as
1136 * port 0. So, we just use one serial port from each ioc3 (since the
1137 * serial driver adds addresses to get to higher ports).
1138 *
1139 * The first one to do a register_console becomes the preferred console
1140 * (if there is no kernel command line console= directive). /dev/console
1141 * (ie 5, 1) is then "aliased" into the device number returned by the
1142 * "device" routine referred to in this console structure
1143 * (ip27prom_console_dev).
1144 *
1145 * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
1146 * around ioc3 oddities in this respect.
1147 *
1148 * The IOC3 serials use a 22MHz clock rate with an additional divider by 3.
1149 * (IOC3_BAUD = (22000000 / (3*16)))
1150 */
1151
1152static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
1153{
1154 struct serial_struct req;
1155
1156 /*
1157 * We need to recognice and treat the fourth MENET serial as it
1158 * does not have an SuperIO chip attached to it, therefore attempting
1159 * to access it will result in bus errors. We call something an
1160 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
1161 * in it. This is paranoid but we want to avoid blowing up on a
1162 * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
1163 * not paranoid enough ...
1164 */
1165 if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
1166 return;
1167
1168 /* Register to interrupt zero because we share the interrupt with
1169 the serial driver which we don't properly support yet. */
1170 memset(&req, 0, sizeof(req));
1171 req.irq = 0;
1172 req.flags = IOC3_COM_FLAGS;
1173 req.io_type = SERIAL_IO_MEM;
1174 req.iomem_reg_shift = 0;
1175 req.baud_base = IOC3_BAUD;
1176
1177 req.iomem_base = (unsigned char *) &ioc3->sregs.uarta;
1178 register_serial(&req);
1179
1180 req.iomem_base = (unsigned char *) &ioc3->sregs.uartb;
1181 register_serial(&req);
1182}
1183#endif
1184
1185static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1186{
1187 unsigned int sw_physid1, sw_physid2;
1188 struct net_device *dev = NULL;
1189 struct ioc3_private *ip;
1190 struct ioc3 *ioc3;
1191 unsigned long ioc3_base, ioc3_size;
1192 u32 vendor, model, rev;
1193 int err, pci_using_dac;
1194
1195 /* Configure DMA attributes. */
1196 err = pci_set_dma_mask(pdev, 0xffffffffffffffffULL);
1197 if (!err) {
1198 pci_using_dac = 1;
1199 err = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL);
1200 if (err < 0) {
1201 printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "
1202 "for consistent allocations\n", pci_name(pdev));
1203 goto out;
1204 }
1205 } else {
1206 err = pci_set_dma_mask(pdev, 0xffffffffULL);
1207 if (err) {
1208 printk(KERN_ERR "%s: No usable DMA configuration, "
1209 "aborting.\n", pci_name(pdev));
1210 goto out;
1211 }
1212 pci_using_dac = 0;
1213 }
1214
1215 if (pci_enable_device(pdev))
1216 return -ENODEV;
1217
1218 dev = alloc_etherdev(sizeof(struct ioc3_private));
1219 if (!dev) {
1220 err = -ENOMEM;
1221 goto out_disable;
1222 }
1223
1224 if (pci_using_dac)
1225 dev->features |= NETIF_F_HIGHDMA;
1226
1227 err = pci_request_regions(pdev, "ioc3");
1228 if (err)
1229 goto out_free;
1230
1231 SET_MODULE_OWNER(dev);
1232 SET_NETDEV_DEV(dev, &pdev->dev);
1233
1234 ip = netdev_priv(dev);
1235
1236 dev->irq = pdev->irq;
1237
1238 ioc3_base = pci_resource_start(pdev, 0);
1239 ioc3_size = pci_resource_len(pdev, 0);
1240 ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
1241 if (!ioc3) {
1242 printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",
1243 pci_name(pdev));
1244 err = -ENOMEM;
1245 goto out_res;
1246 }
1247 ip->regs = ioc3;
1248
1249#ifdef CONFIG_SERIAL_8250
1250 ioc3_serial_probe(pdev, ioc3);
1251#endif
1252
1253 spin_lock_init(&ip->ioc3_lock);
1254 init_timer(&ip->ioc3_timer);
1255
1256 ioc3_stop(ip);
1257 ioc3_init(dev);
1258
1259 ip->pdev = pdev;
1260
1261 ip->mii.phy_id_mask = 0x1f;
1262 ip->mii.reg_num_mask = 0x1f;
1263 ip->mii.dev = dev;
1264 ip->mii.mdio_read = ioc3_mdio_read;
1265 ip->mii.mdio_write = ioc3_mdio_write;
1266
1267 ioc3_mii_init(ip);
1268
1269 if (ip->mii.phy_id == -1) {
1270 printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1271 pci_name(pdev));
1272 err = -ENODEV;
1273 goto out_stop;
1274 }
1275
1276 ioc3_ssram_disc(ip);
1277 ioc3_get_eaddr(ip);
1278
1279 /* The IOC3-specific entries in the device structure. */
1280 dev->open = ioc3_open;
1281 dev->hard_start_xmit = ioc3_start_xmit;
1282 dev->tx_timeout = ioc3_timeout;
1283 dev->watchdog_timeo = 5 * HZ;
1284 dev->stop = ioc3_close;
1285 dev->get_stats = ioc3_get_stats;
1286 dev->do_ioctl = ioc3_ioctl;
1287 dev->set_multicast_list = ioc3_set_multicast_list;
1288 dev->set_mac_address = ioc3_set_mac_address;
1289 dev->ethtool_ops = &ioc3_ethtool_ops;
1290#ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
1291 dev->features = NETIF_F_IP_CSUM;
1292#endif
1293
1294 ioc3_setup_duplex(ip);
1295 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
1296 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
1297
1298 err = register_netdev(dev);
1299 if (err)
1300 goto out_stop;
1301
1302 mii_check_media(&ip->mii, 1, 1);
1303
1304 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
1305 model = (sw_physid2 >> 4) & 0x3f;
1306 rev = sw_physid2 & 0xf;
1307 printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "
1308 "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);
1309 printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
1310 ip->emcr & EMCR_BUFSIZ ? 128 : 64);
1311
1312 return 0;
1313
1314out_stop:
1315 ioc3_stop(ip);
1316 ioc3_free_rings(ip);
1317out_res:
1318 pci_release_regions(pdev);
1319out_free:
1320 free_netdev(dev);
1321out_disable:
1322 /*
1323 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1324 * such a weird device ...
1325 */
1326out:
1327 return err;
1328}
1329
1330static void __devexit ioc3_remove_one (struct pci_dev *pdev)
1331{
1332 struct net_device *dev = pci_get_drvdata(pdev);
1333 struct ioc3_private *ip = netdev_priv(dev);
1334 struct ioc3 *ioc3 = ip->regs;
1335
1336 unregister_netdev(dev);
1337 iounmap(ioc3);
1338 pci_release_regions(pdev);
1339 free_netdev(dev);
1340 /*
1341 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1342 * such a weird device ...
1343 */
1344}
1345
1346static struct pci_device_id ioc3_pci_tbl[] = {
1347 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
1348 { 0 }
1349};
1350MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
1351
1352static struct pci_driver ioc3_driver = {
1353 .name = "ioc3-eth",
1354 .id_table = ioc3_pci_tbl,
1355 .probe = ioc3_probe,
1356 .remove = __devexit_p(ioc3_remove_one),
1357};
1358
1359static int __init ioc3_init_module(void)
1360{
1361 return pci_module_init(&ioc3_driver);
1362}
1363
1364static void __exit ioc3_cleanup_module(void)
1365{
1366 pci_unregister_driver(&ioc3_driver);
1367}
1368
1369static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1370{
1371 unsigned long data;
1372 struct ioc3_private *ip = netdev_priv(dev);
1373 struct ioc3 *ioc3 = ip->regs;
1374 unsigned int len;
1375 struct ioc3_etxd *desc;
1376 uint32_t w0 = 0;
1377 int produce;
1378
1379#ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
1380 /*
1381 * IOC3 has a fairly simple minded checksumming hardware which simply
1382 * adds up the 1's complement checksum for the entire packet and
1383 * inserts it at an offset which can be specified in the descriptor
1384 * into the transmit packet. This means we have to compensate for the
1385 * MAC header which should not be summed and the TCP/UDP pseudo headers
1386 * manually.
1387 */
1388 if (skb->ip_summed == CHECKSUM_HW) {
1389 int proto = ntohs(skb->nh.iph->protocol);
1390 unsigned int csoff;
1391 struct iphdr *ih = skb->nh.iph;
1392 uint32_t csum, ehsum;
1393 uint16_t *eh;
1394
1395 /* The MAC header. skb->mac seem the logic approach
1396 to find the MAC header - except it's a NULL pointer ... */
1397 eh = (uint16_t *) skb->data;
1398
1399 /* Sum up dest addr, src addr and protocol */
1400 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
1401
1402 /* Fold ehsum. can't use csum_fold which negates also ... */
1403 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1404 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1405
1406 /* Skip IP header; it's sum is always zero and was
1407 already filled in by ip_output.c */
1408 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
1409 ih->tot_len - (ih->ihl << 2),
1410 proto, 0xffff ^ ehsum);
1411
1412 csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
1413 csum = (csum & 0xffff) + (csum >> 16);
1414
1415 csoff = ETH_HLEN + (ih->ihl << 2);
1416 if (proto == IPPROTO_UDP) {
1417 csoff += offsetof(struct udphdr, check);
1418 skb->h.uh->check = csum;
1419 }
1420 if (proto == IPPROTO_TCP) {
1421 csoff += offsetof(struct tcphdr, check);
1422 skb->h.th->check = csum;
1423 }
1424
1425 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
1426 }
1427#endif /* CONFIG_SGI_IOC3_ETH_HW_TX_CSUM */
1428
1429 spin_lock_irq(&ip->ioc3_lock);
1430
1431 data = (unsigned long) skb->data;
1432 len = skb->len;
1433
1434 produce = ip->tx_pi;
1435 desc = &ip->txr[produce];
1436
1437 if (len <= 104) {
1438 /* Short packet, let's copy it directly into the ring. */
1439 memcpy(desc->data, skb->data, skb->len);
1440 if (len < ETH_ZLEN) {
1441 /* Very short packet, pad with zeros at the end. */
1442 memset(desc->data + len, 0, ETH_ZLEN - len);
1443 len = ETH_ZLEN;
1444 }
1445 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
1446 desc->bufcnt = cpu_to_be32(len);
1447 } else if ((data ^ (data + len - 1)) & 0x4000) {
1448 unsigned long b2 = (data | 0x3fffUL) + 1UL;
1449 unsigned long s1 = b2 - data;
1450 unsigned long s2 = data + len - b2;
1451
1452 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
1453 ETXD_B1V | ETXD_B2V | w0);
1454 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
1455 (s2 << ETXD_B2CNT_SHIFT));
1456 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1457 desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1));
1458 } else {
1459 /* Normal sized packet that doesn't cross a page boundary. */
1460 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
1461 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
1462 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1463 }
1464
1465 BARRIER();
1466
1467 dev->trans_start = jiffies;
1468 ip->tx_skbs[produce] = skb; /* Remember skb */
1469 produce = (produce + 1) & 127;
1470 ip->tx_pi = produce;
1471 ioc3_w_etpir(produce << 7); /* Fire ... */
1472
1473 ip->txqlen++;
1474
1475 if (ip->txqlen >= 127)
1476 netif_stop_queue(dev);
1477
1478 spin_unlock_irq(&ip->ioc3_lock);
1479
1480 return 0;
1481}
1482
1483static void ioc3_timeout(struct net_device *dev)
1484{
1485 struct ioc3_private *ip = netdev_priv(dev);
1486
1487 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
1488
1489 spin_lock_irq(&ip->ioc3_lock);
1490
1491 ioc3_stop(ip);
1492 ioc3_init(dev);
1493 ioc3_mii_init(ip);
1494
1495 spin_unlock_irq(&ip->ioc3_lock);
1496
1497 netif_wake_queue(dev);
1498}
1499
1500/*
1501 * Given a multicast ethernet address, this routine calculates the
1502 * address's bit index in the logical address filter mask
1503 */
1504
1505static inline unsigned int ioc3_hash(const unsigned char *addr)
1506{
1507 unsigned int temp = 0;
1508 u32 crc;
1509 int bits;
1510
1511 crc = ether_crc_le(ETH_ALEN, addr);
1512
1513 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
1514 for (bits = 6; --bits >= 0; ) {
1515 temp <<= 1;
1516 temp |= (crc & 0x1);
1517 crc >>= 1;
1518 }
1519
1520 return temp;
1521}
1522
1523static void ioc3_get_drvinfo (struct net_device *dev,
1524 struct ethtool_drvinfo *info)
1525{
1526 struct ioc3_private *ip = netdev_priv(dev);
1527
1528 strcpy (info->driver, IOC3_NAME);
1529 strcpy (info->version, IOC3_VERSION);
1530 strcpy (info->bus_info, pci_name(ip->pdev));
1531}
1532
1533static int ioc3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1534{
1535 struct ioc3_private *ip = netdev_priv(dev);
1536 int rc;
1537
1538 spin_lock_irq(&ip->ioc3_lock);
1539 rc = mii_ethtool_gset(&ip->mii, cmd);
1540 spin_unlock_irq(&ip->ioc3_lock);
1541
1542 return rc;
1543}
1544
1545static int ioc3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1546{
1547 struct ioc3_private *ip = netdev_priv(dev);
1548 int rc;
1549
1550 spin_lock_irq(&ip->ioc3_lock);
1551 rc = mii_ethtool_sset(&ip->mii, cmd);
1552 spin_unlock_irq(&ip->ioc3_lock);
1553
1554 return rc;
1555}
1556
1557static int ioc3_nway_reset(struct net_device *dev)
1558{
1559 struct ioc3_private *ip = netdev_priv(dev);
1560 int rc;
1561
1562 spin_lock_irq(&ip->ioc3_lock);
1563 rc = mii_nway_restart(&ip->mii);
1564 spin_unlock_irq(&ip->ioc3_lock);
1565
1566 return rc;
1567}
1568
1569static u32 ioc3_get_link(struct net_device *dev)
1570{
1571 struct ioc3_private *ip = netdev_priv(dev);
1572 int rc;
1573
1574 spin_lock_irq(&ip->ioc3_lock);
1575 rc = mii_link_ok(&ip->mii);
1576 spin_unlock_irq(&ip->ioc3_lock);
1577
1578 return rc;
1579}
1580
1581static struct ethtool_ops ioc3_ethtool_ops = {
1582 .get_drvinfo = ioc3_get_drvinfo,
1583 .get_settings = ioc3_get_settings,
1584 .set_settings = ioc3_set_settings,
1585 .nway_reset = ioc3_nway_reset,
1586 .get_link = ioc3_get_link,
1587};
1588
1589static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1590{
1591 struct ioc3_private *ip = netdev_priv(dev);
1592 int rc;
1593
1594 spin_lock_irq(&ip->ioc3_lock);
1595 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
1596 spin_unlock_irq(&ip->ioc3_lock);
1597
1598 return rc;
1599}
1600
1601static void ioc3_set_multicast_list(struct net_device *dev)
1602{
1603 struct dev_mc_list *dmi = dev->mc_list;
1604 struct ioc3_private *ip = netdev_priv(dev);
1605 struct ioc3 *ioc3 = ip->regs;
1606 u64 ehar = 0;
1607 int i;
1608
1609 netif_stop_queue(dev); /* Lock out others. */
1610
1611 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1612 /* Unconditionally log net taps. */
1613 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1614 ip->emcr |= EMCR_PROMISC;
1615 ioc3_w_emcr(ip->emcr);
1616 (void) ioc3_r_emcr();
1617 } else {
1618 ip->emcr &= ~EMCR_PROMISC;
1619 ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */
1620 (void) ioc3_r_emcr();
1621
1622 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1623 /* Too many for hashing to make sense or we want all
1624 multicast packets anyway, so skip computing all the
1625 hashes and just accept all packets. */
1626 ip->ehar_h = 0xffffffff;
1627 ip->ehar_l = 0xffffffff;
1628 } else {
1629 for (i = 0; i < dev->mc_count; i++) {
1630 char *addr = dmi->dmi_addr;
1631 dmi = dmi->next;
1632
1633 if (!(*addr & 1))
1634 continue;
1635
1636 ehar |= (1UL << ioc3_hash(addr));
1637 }
1638 ip->ehar_h = ehar >> 32;
1639 ip->ehar_l = ehar & 0xffffffff;
1640 }
1641 ioc3_w_ehar_h(ip->ehar_h);
1642 ioc3_w_ehar_l(ip->ehar_l);
1643 }
1644
1645 netif_wake_queue(dev); /* Let us get going again. */
1646}
1647
1648MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1649MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1650MODULE_LICENSE("GPL");
1651
1652module_init(ioc3_init_module);
1653module_exit(ioc3_cleanup_module);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 22:54:27 -0500