diff options
author | Alexander Duyck <alexander.h.duyck@intel.com> | 2008-07-08 18:10:12 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-07-11 01:20:32 -0400 |
commit | 2d064c06fecadadcb81a452acd373af00dfb1fec (patch) | |
tree | 760bc30311966bd406a9f21725bc13cd34755de2 /drivers/net/igb | |
parent | 0024fd00cd404b418b6e6a7408700814cfe7b3dd (diff) |
igb: add 82576 MAC support
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/igb')
-rw-r--r-- | drivers/net/igb/e1000_82575.c | 208 | ||||
-rw-r--r-- | drivers/net/igb/e1000_82575.h | 9 | ||||
-rw-r--r-- | drivers/net/igb/e1000_defines.h | 10 | ||||
-rw-r--r-- | drivers/net/igb/e1000_hw.h | 8 | ||||
-rw-r--r-- | drivers/net/igb/e1000_mac.c | 3 | ||||
-rw-r--r-- | drivers/net/igb/e1000_mac.h | 1 | ||||
-rw-r--r-- | drivers/net/igb/e1000_regs.h | 7 | ||||
-rw-r--r-- | drivers/net/igb/igb_ethtool.c | 146 | ||||
-rw-r--r-- | drivers/net/igb/igb_main.c | 170 |
9 files changed, 476 insertions, 86 deletions
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c index 2c8b91060d98..e098f234770f 100644 --- a/drivers/net/igb/e1000_82575.c +++ b/drivers/net/igb/e1000_82575.c | |||
@@ -31,6 +31,7 @@ | |||
31 | 31 | ||
32 | #include <linux/types.h> | 32 | #include <linux/types.h> |
33 | #include <linux/slab.h> | 33 | #include <linux/slab.h> |
34 | #include <linux/if_ether.h> | ||
34 | 35 | ||
35 | #include "e1000_mac.h" | 36 | #include "e1000_mac.h" |
36 | #include "e1000_82575.h" | 37 | #include "e1000_82575.h" |
@@ -45,7 +46,6 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *); | |||
45 | static s32 igb_init_hw_82575(struct e1000_hw *); | 46 | static s32 igb_init_hw_82575(struct e1000_hw *); |
46 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); | 47 | static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); |
47 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); | 48 | static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); |
48 | static void igb_rar_set_82575(struct e1000_hw *, u8 *, u32); | ||
49 | static s32 igb_reset_hw_82575(struct e1000_hw *); | 49 | static s32 igb_reset_hw_82575(struct e1000_hw *); |
50 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); | 50 | static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); |
51 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); | 51 | static s32 igb_setup_copper_link_82575(struct e1000_hw *); |
@@ -84,6 +84,12 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) | |||
84 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | 84 | case E1000_DEV_ID_82575GB_QUAD_COPPER: |
85 | mac->type = e1000_82575; | 85 | mac->type = e1000_82575; |
86 | break; | 86 | break; |
87 | case E1000_DEV_ID_82576: | ||
88 | case E1000_DEV_ID_82576_FIBER: | ||
89 | case E1000_DEV_ID_82576_SERDES: | ||
90 | case E1000_DEV_ID_82576_QUAD_COPPER: | ||
91 | mac->type = e1000_82576; | ||
92 | break; | ||
87 | default: | 93 | default: |
88 | return -E1000_ERR_MAC_INIT; | 94 | return -E1000_ERR_MAC_INIT; |
89 | break; | 95 | break; |
@@ -128,6 +134,8 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) | |||
128 | mac->mta_reg_count = 128; | 134 | mac->mta_reg_count = 128; |
129 | /* Set rar entry count */ | 135 | /* Set rar entry count */ |
130 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; | 136 | mac->rar_entry_count = E1000_RAR_ENTRIES_82575; |
137 | if (mac->type == e1000_82576) | ||
138 | mac->rar_entry_count = E1000_RAR_ENTRIES_82576; | ||
131 | /* Set if part includes ASF firmware */ | 139 | /* Set if part includes ASF firmware */ |
132 | mac->asf_firmware_present = true; | 140 | mac->asf_firmware_present = true; |
133 | /* Set if manageability features are enabled. */ | 141 | /* Set if manageability features are enabled. */ |
@@ -694,13 +702,12 @@ static s32 igb_check_for_link_82575(struct e1000_hw *hw) | |||
694 | if ((hw->phy.media_type != e1000_media_type_copper) || | 702 | if ((hw->phy.media_type != e1000_media_type_copper) || |
695 | (igb_sgmii_active_82575(hw))) | 703 | (igb_sgmii_active_82575(hw))) |
696 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, | 704 | ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, |
697 | &duplex); | 705 | &duplex); |
698 | else | 706 | else |
699 | ret_val = igb_check_for_copper_link(hw); | 707 | ret_val = igb_check_for_copper_link(hw); |
700 | 708 | ||
701 | return ret_val; | 709 | return ret_val; |
702 | } | 710 | } |
703 | |||
704 | /** | 711 | /** |
705 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex | 712 | * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex |
706 | * @hw: pointer to the HW structure | 713 | * @hw: pointer to the HW structure |
@@ -757,18 +764,129 @@ static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, | |||
757 | } | 764 | } |
758 | 765 | ||
759 | /** | 766 | /** |
760 | * igb_rar_set_82575 - Set receive address register | 767 | * igb_init_rx_addrs_82575 - Initialize receive address's |
768 | * @hw: pointer to the HW structure | ||
769 | * @rar_count: receive address registers | ||
770 | * | ||
771 | * Setups the receive address registers by setting the base receive address | ||
772 | * register to the devices MAC address and clearing all the other receive | ||
773 | * address registers to 0. | ||
774 | **/ | ||
775 | static void igb_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count) | ||
776 | { | ||
777 | u32 i; | ||
778 | u8 addr[6] = {0,0,0,0,0,0}; | ||
779 | /* | ||
780 | * This function is essentially the same as that of | ||
781 | * e1000_init_rx_addrs_generic. However it also takes care | ||
782 | * of the special case where the register offset of the | ||
783 | * second set of RARs begins elsewhere. This is implicitly taken care by | ||
784 | * function e1000_rar_set_generic. | ||
785 | */ | ||
786 | |||
787 | hw_dbg("e1000_init_rx_addrs_82575"); | ||
788 | |||
789 | /* Setup the receive address */ | ||
790 | hw_dbg("Programming MAC Address into RAR[0]\n"); | ||
791 | hw->mac.ops.rar_set(hw, hw->mac.addr, 0); | ||
792 | |||
793 | /* Zero out the other (rar_entry_count - 1) receive addresses */ | ||
794 | hw_dbg("Clearing RAR[1-%u]\n", rar_count-1); | ||
795 | for (i = 1; i < rar_count; i++) | ||
796 | hw->mac.ops.rar_set(hw, addr, i); | ||
797 | } | ||
798 | |||
799 | /** | ||
800 | * igb_update_mc_addr_list_82575 - Update Multicast addresses | ||
801 | * @hw: pointer to the HW structure | ||
802 | * @mc_addr_list: array of multicast addresses to program | ||
803 | * @mc_addr_count: number of multicast addresses to program | ||
804 | * @rar_used_count: the first RAR register free to program | ||
805 | * @rar_count: total number of supported Receive Address Registers | ||
806 | * | ||
807 | * Updates the Receive Address Registers and Multicast Table Array. | ||
808 | * The caller must have a packed mc_addr_list of multicast addresses. | ||
809 | * The parameter rar_count will usually be hw->mac.rar_entry_count | ||
810 | * unless there are workarounds that change this. | ||
811 | **/ | ||
812 | void igb_update_mc_addr_list_82575(struct e1000_hw *hw, | ||
813 | u8 *mc_addr_list, u32 mc_addr_count, | ||
814 | u32 rar_used_count, u32 rar_count) | ||
815 | { | ||
816 | u32 hash_value; | ||
817 | u32 i; | ||
818 | u8 addr[6] = {0,0,0,0,0,0}; | ||
819 | /* | ||
820 | * This function is essentially the same as that of | ||
821 | * igb_update_mc_addr_list_generic. However it also takes care | ||
822 | * of the special case where the register offset of the | ||
823 | * second set of RARs begins elsewhere. This is implicitly taken care by | ||
824 | * function e1000_rar_set_generic. | ||
825 | */ | ||
826 | |||
827 | /* | ||
828 | * Load the first set of multicast addresses into the exact | ||
829 | * filters (RAR). If there are not enough to fill the RAR | ||
830 | * array, clear the filters. | ||
831 | */ | ||
832 | for (i = rar_used_count; i < rar_count; i++) { | ||
833 | if (mc_addr_count) { | ||
834 | igb_rar_set(hw, mc_addr_list, i); | ||
835 | mc_addr_count--; | ||
836 | mc_addr_list += ETH_ALEN; | ||
837 | } else { | ||
838 | igb_rar_set(hw, addr, i); | ||
839 | } | ||
840 | } | ||
841 | |||
842 | /* Clear the old settings from the MTA */ | ||
843 | hw_dbg("Clearing MTA\n"); | ||
844 | for (i = 0; i < hw->mac.mta_reg_count; i++) { | ||
845 | array_wr32(E1000_MTA, i, 0); | ||
846 | wrfl(); | ||
847 | } | ||
848 | |||
849 | /* Load any remaining multicast addresses into the hash table. */ | ||
850 | for (; mc_addr_count > 0; mc_addr_count--) { | ||
851 | hash_value = igb_hash_mc_addr(hw, mc_addr_list); | ||
852 | hw_dbg("Hash value = 0x%03X\n", hash_value); | ||
853 | hw->mac.ops.mta_set(hw, hash_value); | ||
854 | mc_addr_list += ETH_ALEN; | ||
855 | } | ||
856 | } | ||
857 | |||
858 | /** | ||
859 | * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down | ||
761 | * @hw: pointer to the HW structure | 860 | * @hw: pointer to the HW structure |
762 | * @addr: pointer to the receive address | ||
763 | * @index: receive address array register | ||
764 | * | 861 | * |
765 | * Sets the receive address array register at index to the address passed | 862 | * In the case of fiber serdes, shut down optics and PCS on driver unload |
766 | * in by addr. | 863 | * when management pass thru is not enabled. |
767 | **/ | 864 | **/ |
768 | static void igb_rar_set_82575(struct e1000_hw *hw, u8 *addr, u32 index) | 865 | void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw) |
769 | { | 866 | { |
770 | if (index < E1000_RAR_ENTRIES_82575) | 867 | u32 reg; |
771 | igb_rar_set(hw, addr, index); | 868 | |
869 | if (hw->mac.type != e1000_82576 || | ||
870 | (hw->phy.media_type != e1000_media_type_fiber && | ||
871 | hw->phy.media_type != e1000_media_type_internal_serdes)) | ||
872 | return; | ||
873 | |||
874 | /* if the management interface is not enabled, then power down */ | ||
875 | if (!igb_enable_mng_pass_thru(hw)) { | ||
876 | /* Disable PCS to turn off link */ | ||
877 | reg = rd32(E1000_PCS_CFG0); | ||
878 | reg &= ~E1000_PCS_CFG_PCS_EN; | ||
879 | wr32(E1000_PCS_CFG0, reg); | ||
880 | |||
881 | /* shutdown the laser */ | ||
882 | reg = rd32(E1000_CTRL_EXT); | ||
883 | reg |= E1000_CTRL_EXT_SDP7_DATA; | ||
884 | wr32(E1000_CTRL_EXT, reg); | ||
885 | |||
886 | /* flush the write to verify completion */ | ||
887 | wrfl(); | ||
888 | msleep(1); | ||
889 | } | ||
772 | 890 | ||
773 | return; | 891 | return; |
774 | } | 892 | } |
@@ -854,7 +972,7 @@ static s32 igb_init_hw_82575(struct e1000_hw *hw) | |||
854 | igb_clear_vfta(hw); | 972 | igb_clear_vfta(hw); |
855 | 973 | ||
856 | /* Setup the receive address */ | 974 | /* Setup the receive address */ |
857 | igb_init_rx_addrs(hw, rar_count); | 975 | igb_init_rx_addrs_82575(hw, rar_count); |
858 | /* Zero out the Multicast HASH table */ | 976 | /* Zero out the Multicast HASH table */ |
859 | hw_dbg("Zeroing the MTA\n"); | 977 | hw_dbg("Zeroing the MTA\n"); |
860 | for (i = 0; i < mac->mta_reg_count; i++) | 978 | for (i = 0; i < mac->mta_reg_count; i++) |
@@ -1114,6 +1232,70 @@ out: | |||
1114 | } | 1232 | } |
1115 | 1233 | ||
1116 | /** | 1234 | /** |
1235 | * igb_translate_register_82576 - Translate the proper register offset | ||
1236 | * @reg: e1000 register to be read | ||
1237 | * | ||
1238 | * Registers in 82576 are located in different offsets than other adapters | ||
1239 | * even though they function in the same manner. This function takes in | ||
1240 | * the name of the register to read and returns the correct offset for | ||
1241 | * 82576 silicon. | ||
1242 | **/ | ||
1243 | u32 igb_translate_register_82576(u32 reg) | ||
1244 | { | ||
1245 | /* | ||
1246 | * Some of the Kawela registers are located at different | ||
1247 | * offsets than they are in older adapters. | ||
1248 | * Despite the difference in location, the registers | ||
1249 | * function in the same manner. | ||
1250 | */ | ||
1251 | switch (reg) { | ||
1252 | case E1000_TDBAL(0): | ||
1253 | reg = 0x0E000; | ||
1254 | break; | ||
1255 | case E1000_TDBAH(0): | ||
1256 | reg = 0x0E004; | ||
1257 | break; | ||
1258 | case E1000_TDLEN(0): | ||
1259 | reg = 0x0E008; | ||
1260 | break; | ||
1261 | case E1000_TDH(0): | ||
1262 | reg = 0x0E010; | ||
1263 | break; | ||
1264 | case E1000_TDT(0): | ||
1265 | reg = 0x0E018; | ||
1266 | break; | ||
1267 | case E1000_TXDCTL(0): | ||
1268 | reg = 0x0E028; | ||
1269 | break; | ||
1270 | case E1000_RDBAL(0): | ||
1271 | reg = 0x0C000; | ||
1272 | break; | ||
1273 | case E1000_RDBAH(0): | ||
1274 | reg = 0x0C004; | ||
1275 | break; | ||
1276 | case E1000_RDLEN(0): | ||
1277 | reg = 0x0C008; | ||
1278 | break; | ||
1279 | case E1000_RDH(0): | ||
1280 | reg = 0x0C010; | ||
1281 | break; | ||
1282 | case E1000_RDT(0): | ||
1283 | reg = 0x0C018; | ||
1284 | break; | ||
1285 | case E1000_RXDCTL(0): | ||
1286 | reg = 0x0C028; | ||
1287 | break; | ||
1288 | case E1000_SRRCTL(0): | ||
1289 | reg = 0x0C00C; | ||
1290 | break; | ||
1291 | default: | ||
1292 | break; | ||
1293 | } | ||
1294 | |||
1295 | return reg; | ||
1296 | } | ||
1297 | |||
1298 | /** | ||
1117 | * igb_reset_init_script_82575 - Inits HW defaults after reset | 1299 | * igb_reset_init_script_82575 - Inits HW defaults after reset |
1118 | * @hw: pointer to the HW structure | 1300 | * @hw: pointer to the HW structure |
1119 | * | 1301 | * |
@@ -1304,7 +1486,7 @@ static struct e1000_mac_operations e1000_mac_ops_82575 = { | |||
1304 | .reset_hw = igb_reset_hw_82575, | 1486 | .reset_hw = igb_reset_hw_82575, |
1305 | .init_hw = igb_init_hw_82575, | 1487 | .init_hw = igb_init_hw_82575, |
1306 | .check_for_link = igb_check_for_link_82575, | 1488 | .check_for_link = igb_check_for_link_82575, |
1307 | .rar_set = igb_rar_set_82575, | 1489 | .rar_set = igb_rar_set, |
1308 | .read_mac_addr = igb_read_mac_addr_82575, | 1490 | .read_mac_addr = igb_read_mac_addr_82575, |
1309 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, | 1491 | .get_speed_and_duplex = igb_get_speed_and_duplex_copper, |
1310 | }; | 1492 | }; |
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h index 02e57a8447cb..d273236c7764 100644 --- a/drivers/net/igb/e1000_82575.h +++ b/drivers/net/igb/e1000_82575.h | |||
@@ -28,9 +28,13 @@ | |||
28 | #ifndef _E1000_82575_H_ | 28 | #ifndef _E1000_82575_H_ |
29 | #define _E1000_82575_H_ | 29 | #define _E1000_82575_H_ |
30 | 30 | ||
31 | u32 igb_translate_register_82576(u32 reg); | ||
32 | void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32); | ||
33 | extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw); | ||
31 | extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); | 34 | extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); |
32 | 35 | ||
33 | #define E1000_RAR_ENTRIES_82575 16 | 36 | #define E1000_RAR_ENTRIES_82575 16 |
37 | #define E1000_RAR_ENTRIES_82576 24 | ||
34 | 38 | ||
35 | /* SRRCTL bit definitions */ | 39 | /* SRRCTL bit definitions */ |
36 | #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ | 40 | #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ |
@@ -159,5 +163,10 @@ struct e1000_adv_tx_context_desc { | |||
159 | #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ | 163 | #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ |
160 | #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ | 164 | #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ |
161 | 165 | ||
166 | /* Additional DCA related definitions, note change in position of CPUID */ | ||
167 | #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ | ||
168 | #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ | ||
169 | #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */ | ||
170 | #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */ | ||
162 | 171 | ||
163 | #endif | 172 | #endif |
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h index ed748dcfb7a4..afdba3c9073c 100644 --- a/drivers/net/igb/e1000_defines.h +++ b/drivers/net/igb/e1000_defines.h | |||
@@ -90,6 +90,11 @@ | |||
90 | #define E1000_I2CCMD_ERROR 0x80000000 | 90 | #define E1000_I2CCMD_ERROR 0x80000000 |
91 | #define E1000_MAX_SGMII_PHY_REG_ADDR 255 | 91 | #define E1000_MAX_SGMII_PHY_REG_ADDR 255 |
92 | #define E1000_I2CCMD_PHY_TIMEOUT 200 | 92 | #define E1000_I2CCMD_PHY_TIMEOUT 200 |
93 | #define E1000_IVAR_VALID 0x80 | ||
94 | #define E1000_GPIE_NSICR 0x00000001 | ||
95 | #define E1000_GPIE_MSIX_MODE 0x00000010 | ||
96 | #define E1000_GPIE_EIAME 0x40000000 | ||
97 | #define E1000_GPIE_PBA 0x80000000 | ||
93 | 98 | ||
94 | /* Receive Descriptor bit definitions */ | 99 | /* Receive Descriptor bit definitions */ |
95 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | 100 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
@@ -213,6 +218,7 @@ | |||
213 | /* Device Control */ | 218 | /* Device Control */ |
214 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | 219 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ |
215 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ | 220 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ |
221 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ | ||
216 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ | 222 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ |
217 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ | 223 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ |
218 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ | 224 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ |
@@ -244,6 +250,7 @@ | |||
244 | */ | 250 | */ |
245 | 251 | ||
246 | #define E1000_CONNSW_ENRGSRC 0x4 | 252 | #define E1000_CONNSW_ENRGSRC 0x4 |
253 | #define E1000_PCS_CFG_PCS_EN 8 | ||
247 | #define E1000_PCS_LCTL_FLV_LINK_UP 1 | 254 | #define E1000_PCS_LCTL_FLV_LINK_UP 1 |
248 | #define E1000_PCS_LCTL_FSV_100 2 | 255 | #define E1000_PCS_LCTL_FSV_100 2 |
249 | #define E1000_PCS_LCTL_FSV_1000 4 | 256 | #define E1000_PCS_LCTL_FSV_1000 4 |
@@ -253,6 +260,7 @@ | |||
253 | #define E1000_PCS_LCTL_AN_ENABLE 0x10000 | 260 | #define E1000_PCS_LCTL_AN_ENABLE 0x10000 |
254 | #define E1000_PCS_LCTL_AN_RESTART 0x20000 | 261 | #define E1000_PCS_LCTL_AN_RESTART 0x20000 |
255 | #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 | 262 | #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 |
263 | #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 | ||
256 | 264 | ||
257 | #define E1000_PCS_LSTS_LINK_OK 1 | 265 | #define E1000_PCS_LSTS_LINK_OK 1 |
258 | #define E1000_PCS_LSTS_SPEED_100 2 | 266 | #define E1000_PCS_LSTS_SPEED_100 2 |
@@ -360,6 +368,7 @@ | |||
360 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ | 368 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ |
361 | #define E1000_PBA_24K 0x0018 | 369 | #define E1000_PBA_24K 0x0018 |
362 | #define E1000_PBA_34K 0x0022 | 370 | #define E1000_PBA_34K 0x0022 |
371 | #define E1000_PBA_64K 0x0040 /* 64KB */ | ||
363 | 372 | ||
364 | #define IFS_MAX 80 | 373 | #define IFS_MAX 80 |
365 | #define IFS_MIN 40 | 374 | #define IFS_MIN 40 |
@@ -528,6 +537,7 @@ | |||
528 | /* PHY Control Register */ | 537 | /* PHY Control Register */ |
529 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | 538 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
530 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | 539 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
540 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ | ||
531 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | 541 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
532 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | 542 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
533 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | 543 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
diff --git a/drivers/net/igb/e1000_hw.h b/drivers/net/igb/e1000_hw.h index 746c3ea09e27..19fa4ee96f2e 100644 --- a/drivers/net/igb/e1000_hw.h +++ b/drivers/net/igb/e1000_hw.h | |||
@@ -38,6 +38,10 @@ | |||
38 | 38 | ||
39 | struct e1000_hw; | 39 | struct e1000_hw; |
40 | 40 | ||
41 | #define E1000_DEV_ID_82576 0x10C9 | ||
42 | #define E1000_DEV_ID_82576_FIBER 0x10E6 | ||
43 | #define E1000_DEV_ID_82576_SERDES 0x10E7 | ||
44 | #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 | ||
41 | #define E1000_DEV_ID_82575EB_COPPER 0x10A7 | 45 | #define E1000_DEV_ID_82575EB_COPPER 0x10A7 |
42 | #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 | 46 | #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 |
43 | #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 | 47 | #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 |
@@ -50,6 +54,7 @@ struct e1000_hw; | |||
50 | enum e1000_mac_type { | 54 | enum e1000_mac_type { |
51 | e1000_undefined = 0, | 55 | e1000_undefined = 0, |
52 | e1000_82575, | 56 | e1000_82575, |
57 | e1000_82576, | ||
53 | e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ | 58 | e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ |
54 | }; | 59 | }; |
55 | 60 | ||
@@ -410,14 +415,17 @@ struct e1000_mac_operations { | |||
410 | s32 (*check_for_link)(struct e1000_hw *); | 415 | s32 (*check_for_link)(struct e1000_hw *); |
411 | s32 (*reset_hw)(struct e1000_hw *); | 416 | s32 (*reset_hw)(struct e1000_hw *); |
412 | s32 (*init_hw)(struct e1000_hw *); | 417 | s32 (*init_hw)(struct e1000_hw *); |
418 | bool (*check_mng_mode)(struct e1000_hw *); | ||
413 | s32 (*setup_physical_interface)(struct e1000_hw *); | 419 | s32 (*setup_physical_interface)(struct e1000_hw *); |
414 | void (*rar_set)(struct e1000_hw *, u8 *, u32); | 420 | void (*rar_set)(struct e1000_hw *, u8 *, u32); |
415 | s32 (*read_mac_addr)(struct e1000_hw *); | 421 | s32 (*read_mac_addr)(struct e1000_hw *); |
416 | s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); | 422 | s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); |
423 | void (*mta_set)(struct e1000_hw *, u32); | ||
417 | }; | 424 | }; |
418 | 425 | ||
419 | struct e1000_phy_operations { | 426 | struct e1000_phy_operations { |
420 | s32 (*acquire_phy)(struct e1000_hw *); | 427 | s32 (*acquire_phy)(struct e1000_hw *); |
428 | s32 (*check_reset_block)(struct e1000_hw *); | ||
421 | s32 (*force_speed_duplex)(struct e1000_hw *); | 429 | s32 (*force_speed_duplex)(struct e1000_hw *); |
422 | s32 (*get_cfg_done)(struct e1000_hw *hw); | 430 | s32 (*get_cfg_done)(struct e1000_hw *hw); |
423 | s32 (*get_cable_length)(struct e1000_hw *); | 431 | s32 (*get_cable_length)(struct e1000_hw *); |
diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c index 47ad2c4277c3..20408aa1f916 100644 --- a/drivers/net/igb/e1000_mac.c +++ b/drivers/net/igb/e1000_mac.c | |||
@@ -36,7 +36,6 @@ | |||
36 | 36 | ||
37 | static s32 igb_set_default_fc(struct e1000_hw *hw); | 37 | static s32 igb_set_default_fc(struct e1000_hw *hw); |
38 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw); | 38 | static s32 igb_set_fc_watermarks(struct e1000_hw *hw); |
39 | static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); | ||
40 | 39 | ||
41 | /** | 40 | /** |
42 | * igb_remove_device - Free device specific structure | 41 | * igb_remove_device - Free device specific structure |
@@ -360,7 +359,7 @@ void igb_update_mc_addr_list(struct e1000_hw *hw, | |||
360 | * the multicast filter table array address and new table value. See | 359 | * the multicast filter table array address and new table value. See |
361 | * igb_mta_set() | 360 | * igb_mta_set() |
362 | **/ | 361 | **/ |
363 | static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) | 362 | u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
364 | { | 363 | { |
365 | u32 hash_value, hash_mask; | 364 | u32 hash_value, hash_mask; |
366 | u8 bit_shift = 0; | 365 | u8 bit_shift = 0; |
diff --git a/drivers/net/igb/e1000_mac.h b/drivers/net/igb/e1000_mac.h index 326b6592307b..dc2f8cce15e7 100644 --- a/drivers/net/igb/e1000_mac.h +++ b/drivers/net/igb/e1000_mac.h | |||
@@ -94,5 +94,6 @@ enum e1000_mng_mode { | |||
94 | #define E1000_HICR_C 0x02 | 94 | #define E1000_HICR_C 0x02 |
95 | 95 | ||
96 | extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); | 96 | extern void e1000_init_function_pointers_82575(struct e1000_hw *hw); |
97 | extern u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr); | ||
97 | 98 | ||
98 | #endif | 99 | #endif |
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h index d25e914df975..b95093d24c09 100644 --- a/drivers/net/igb/e1000_regs.h +++ b/drivers/net/igb/e1000_regs.h | |||
@@ -56,6 +56,9 @@ | |||
56 | #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ | 56 | #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ |
57 | #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ | 57 | #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ |
58 | #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ | 58 | #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ |
59 | #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ | ||
60 | #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ | ||
61 | #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ | ||
59 | #define E1000_TCTL 0x00400 /* TX Control - RW */ | 62 | #define E1000_TCTL 0x00400 /* TX Control - RW */ |
60 | #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ | 63 | #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ |
61 | #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ | 64 | #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ |
@@ -217,6 +220,7 @@ | |||
217 | #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ | 220 | #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ |
218 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ | 221 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ |
219 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ | 222 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ |
223 | #define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW Array */ | ||
220 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ | 224 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ |
221 | #define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */ | 225 | #define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */ |
222 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ | 226 | #define E1000_WUC 0x05800 /* Wakeup Control - RW */ |
@@ -258,7 +262,8 @@ | |||
258 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) | 262 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) |
259 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ | 263 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ |
260 | 264 | ||
261 | #define E1000_REGISTER(a, reg) reg | 265 | #define E1000_REGISTER(a, reg) (((a)->mac.type < e1000_82576) \ |
266 | ? reg : e1000_translate_register_82576(reg)) | ||
262 | 267 | ||
263 | #define wr32(reg, value) (writel(value, hw->hw_addr + reg)) | 268 | #define wr32(reg, value) (writel(value, hw->hw_addr + reg)) |
264 | #define rd32(reg) (readl(hw->hw_addr + reg)) | 269 | #define rd32(reg) (readl(hw->hw_addr + reg)) |
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c index ed756c12aba6..e27d5a533b4f 100644 --- a/drivers/net/igb/igb_ethtool.c +++ b/drivers/net/igb/igb_ethtool.c | |||
@@ -827,8 +827,9 @@ err_setup: | |||
827 | /* ethtool register test data */ | 827 | /* ethtool register test data */ |
828 | struct igb_reg_test { | 828 | struct igb_reg_test { |
829 | u16 reg; | 829 | u16 reg; |
830 | u8 array_len; | 830 | u16 reg_offset; |
831 | u8 test_type; | 831 | u16 array_len; |
832 | u16 test_type; | ||
832 | u32 mask; | 833 | u32 mask; |
833 | u32 write; | 834 | u32 write; |
834 | }; | 835 | }; |
@@ -850,34 +851,72 @@ struct igb_reg_test { | |||
850 | #define TABLE64_TEST_LO 5 | 851 | #define TABLE64_TEST_LO 5 |
851 | #define TABLE64_TEST_HI 6 | 852 | #define TABLE64_TEST_HI 6 |
852 | 853 | ||
853 | /* default register test */ | 854 | /* 82576 reg test */ |
855 | static struct igb_reg_test reg_test_82576[] = { | ||
856 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | ||
857 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | ||
858 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | ||
859 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | ||
860 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | ||
861 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | ||
862 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | ||
863 | { E1000_RDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | ||
864 | { E1000_RDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | ||
865 | { E1000_RDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | ||
866 | /* Enable all four RX queues before testing. */ | ||
867 | { E1000_RXDCTL(0), 0x100, 1, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, | ||
868 | /* RDH is read-only for 82576, only test RDT. */ | ||
869 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | ||
870 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, | ||
871 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, | ||
872 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | ||
873 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | ||
874 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | ||
875 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | ||
876 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | ||
877 | { E1000_TDBAL(4), 0x40, 8, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | ||
878 | { E1000_TDBAH(4), 0x40, 8, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | ||
879 | { E1000_TDLEN(4), 0x40, 8, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | ||
880 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | ||
881 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, | ||
882 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, | ||
883 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | ||
884 | { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | ||
885 | { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, | ||
886 | { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | ||
887 | { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, | ||
888 | { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | ||
889 | { 0, 0, 0, 0 } | ||
890 | }; | ||
891 | |||
892 | /* 82575 register test */ | ||
854 | static struct igb_reg_test reg_test_82575[] = { | 893 | static struct igb_reg_test reg_test_82575[] = { |
855 | { E1000_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | 894 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
856 | { E1000_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | 895 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, |
857 | { E1000_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | 896 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, |
858 | { E1000_VET, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | 897 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
859 | { E1000_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | 898 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
860 | { E1000_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | 899 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
861 | { E1000_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | 900 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
862 | /* Enable all four RX queues before testing. */ | 901 | /* Enable all four RX queues before testing. */ |
863 | { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, | 902 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, |
864 | /* RDH is read-only for 82575, only test RDT. */ | 903 | /* RDH is read-only for 82575, only test RDT. */ |
865 | { E1000_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | 904 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, |
866 | { E1000_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, | 905 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, |
867 | { E1000_FCRTH, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, | 906 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, |
868 | { E1000_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | 907 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, |
869 | { E1000_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | 908 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, |
870 | { E1000_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | 909 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
871 | { E1000_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | 910 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
872 | { E1000_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | 911 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
873 | { E1000_RCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | 912 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, |
874 | { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, | 913 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, |
875 | { E1000_RCTL, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, | 914 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, |
876 | { E1000_TCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | 915 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, |
877 | { E1000_TXCW, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, | 916 | { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, |
878 | { E1000_RA, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | 917 | { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, |
879 | { E1000_RA, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, | 918 | { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, |
880 | { E1000_MTA, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | 919 | { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
881 | { 0, 0, 0, 0 } | 920 | { 0, 0, 0, 0 } |
882 | }; | 921 | }; |
883 | 922 | ||
@@ -937,7 +976,15 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data) | |||
937 | u32 i, toggle; | 976 | u32 i, toggle; |
938 | 977 | ||
939 | toggle = 0x7FFFF3FF; | 978 | toggle = 0x7FFFF3FF; |
940 | test = reg_test_82575; | 979 | |
980 | switch (adapter->hw.mac.type) { | ||
981 | case e1000_82576: | ||
982 | test = reg_test_82576; | ||
983 | break; | ||
984 | default: | ||
985 | test = reg_test_82575; | ||
986 | break; | ||
987 | } | ||
941 | 988 | ||
942 | /* Because the status register is such a special case, | 989 | /* Because the status register is such a special case, |
943 | * we handle it separately from the rest of the register | 990 | * we handle it separately from the rest of the register |
@@ -964,19 +1011,19 @@ static int igb_reg_test(struct igb_adapter *adapter, u64 *data) | |||
964 | for (i = 0; i < test->array_len; i++) { | 1011 | for (i = 0; i < test->array_len; i++) { |
965 | switch (test->test_type) { | 1012 | switch (test->test_type) { |
966 | case PATTERN_TEST: | 1013 | case PATTERN_TEST: |
967 | REG_PATTERN_TEST(test->reg + (i * 0x100), | 1014 | REG_PATTERN_TEST(test->reg + (i * test->reg_offset), |
968 | test->mask, | 1015 | test->mask, |
969 | test->write); | 1016 | test->write); |
970 | break; | 1017 | break; |
971 | case SET_READ_TEST: | 1018 | case SET_READ_TEST: |
972 | REG_SET_AND_CHECK(test->reg + (i * 0x100), | 1019 | REG_SET_AND_CHECK(test->reg + (i * test->reg_offset), |
973 | test->mask, | 1020 | test->mask, |
974 | test->write); | 1021 | test->write); |
975 | break; | 1022 | break; |
976 | case WRITE_NO_TEST: | 1023 | case WRITE_NO_TEST: |
977 | writel(test->write, | 1024 | writel(test->write, |
978 | (adapter->hw.hw_addr + test->reg) | 1025 | (adapter->hw.hw_addr + test->reg) |
979 | + (i * 0x100)); | 1026 | + (i * test->reg_offset)); |
980 | break; | 1027 | break; |
981 | case TABLE32_TEST: | 1028 | case TABLE32_TEST: |
982 | REG_PATTERN_TEST(test->reg + (i * 4), | 1029 | REG_PATTERN_TEST(test->reg + (i * 4), |
@@ -1392,13 +1439,39 @@ static int igb_set_phy_loopback(struct igb_adapter *adapter) | |||
1392 | static int igb_setup_loopback_test(struct igb_adapter *adapter) | 1439 | static int igb_setup_loopback_test(struct igb_adapter *adapter) |
1393 | { | 1440 | { |
1394 | struct e1000_hw *hw = &adapter->hw; | 1441 | struct e1000_hw *hw = &adapter->hw; |
1395 | u32 rctl; | 1442 | u32 reg; |
1396 | 1443 | ||
1397 | if (hw->phy.media_type == e1000_media_type_fiber || | 1444 | if (hw->phy.media_type == e1000_media_type_fiber || |
1398 | hw->phy.media_type == e1000_media_type_internal_serdes) { | 1445 | hw->phy.media_type == e1000_media_type_internal_serdes) { |
1399 | rctl = rd32(E1000_RCTL); | 1446 | reg = rd32(E1000_RCTL); |
1400 | rctl |= E1000_RCTL_LBM_TCVR; | 1447 | reg |= E1000_RCTL_LBM_TCVR; |
1401 | wr32(E1000_RCTL, rctl); | 1448 | wr32(E1000_RCTL, reg); |
1449 | |||
1450 | wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); | ||
1451 | |||
1452 | reg = rd32(E1000_CTRL); | ||
1453 | reg &= ~(E1000_CTRL_RFCE | | ||
1454 | E1000_CTRL_TFCE | | ||
1455 | E1000_CTRL_LRST); | ||
1456 | reg |= E1000_CTRL_SLU | | ||
1457 | E1000_CTRL_FD; | ||
1458 | wr32(E1000_CTRL, reg); | ||
1459 | |||
1460 | /* Unset switch control to serdes energy detect */ | ||
1461 | reg = rd32(E1000_CONNSW); | ||
1462 | reg &= ~E1000_CONNSW_ENRGSRC; | ||
1463 | wr32(E1000_CONNSW, reg); | ||
1464 | |||
1465 | /* Set PCS register for forced speed */ | ||
1466 | reg = rd32(E1000_PCS_LCTL); | ||
1467 | reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ | ||
1468 | reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ | ||
1469 | E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ | ||
1470 | E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ | ||
1471 | E1000_PCS_LCTL_FSD | /* Force Speed */ | ||
1472 | E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ | ||
1473 | wr32(E1000_PCS_LCTL, reg); | ||
1474 | |||
1402 | return 0; | 1475 | return 0; |
1403 | } else if (hw->phy.media_type == e1000_media_type_copper) { | 1476 | } else if (hw->phy.media_type == e1000_media_type_copper) { |
1404 | return igb_set_phy_loopback(adapter); | 1477 | return igb_set_phy_loopback(adapter); |
@@ -1654,10 +1727,13 @@ static int igb_wol_exclusion(struct igb_adapter *adapter, | |||
1654 | 1727 | ||
1655 | switch (hw->device_id) { | 1728 | switch (hw->device_id) { |
1656 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | 1729 | case E1000_DEV_ID_82575GB_QUAD_COPPER: |
1730 | case E1000_DEV_ID_82576_QUAD_COPPER: | ||
1657 | /* WoL not supported */ | 1731 | /* WoL not supported */ |
1658 | wol->supported = 0; | 1732 | wol->supported = 0; |
1659 | break; | 1733 | break; |
1660 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | 1734 | case E1000_DEV_ID_82575EB_FIBER_SERDES: |
1735 | case E1000_DEV_ID_82576_FIBER: | ||
1736 | case E1000_DEV_ID_82576_SERDES: | ||
1661 | /* Wake events not supported on port B */ | 1737 | /* Wake events not supported on port B */ |
1662 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) { | 1738 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) { |
1663 | wol->supported = 0; | 1739 | wol->supported = 0; |
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index 14363260612c..ba043c4e1ca2 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c | |||
@@ -51,7 +51,7 @@ char igb_driver_name[] = "igb"; | |||
51 | char igb_driver_version[] = DRV_VERSION; | 51 | char igb_driver_version[] = DRV_VERSION; |
52 | static const char igb_driver_string[] = | 52 | static const char igb_driver_string[] = |
53 | "Intel(R) Gigabit Ethernet Network Driver"; | 53 | "Intel(R) Gigabit Ethernet Network Driver"; |
54 | static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation."; | 54 | static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation."; |
55 | 55 | ||
56 | 56 | ||
57 | static const struct e1000_info *igb_info_tbl[] = { | 57 | static const struct e1000_info *igb_info_tbl[] = { |
@@ -59,6 +59,10 @@ static const struct e1000_info *igb_info_tbl[] = { | |||
59 | }; | 59 | }; |
60 | 60 | ||
61 | static struct pci_device_id igb_pci_tbl[] = { | 61 | static struct pci_device_id igb_pci_tbl[] = { |
62 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, | ||
63 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, | ||
64 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | ||
65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, | ||
62 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, | 66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
63 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | 67 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, |
64 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | 68 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, |
@@ -268,6 +272,10 @@ static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |||
268 | { | 272 | { |
269 | u32 msixbm = 0; | 273 | u32 msixbm = 0; |
270 | struct e1000_hw *hw = &adapter->hw; | 274 | struct e1000_hw *hw = &adapter->hw; |
275 | u32 ivar, index; | ||
276 | |||
277 | switch (hw->mac.type) { | ||
278 | case e1000_82575: | ||
271 | /* The 82575 assigns vectors using a bitmask, which matches the | 279 | /* The 82575 assigns vectors using a bitmask, which matches the |
272 | bitmask for the EICR/EIMS/EIMC registers. To assign one | 280 | bitmask for the EICR/EIMS/EIMC registers. To assign one |
273 | or more queues to a vector, we write the appropriate bits | 281 | or more queues to a vector, we write the appropriate bits |
@@ -282,6 +290,47 @@ static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue, | |||
282 | E1000_EICR_TX_QUEUE0 << tx_queue; | 290 | E1000_EICR_TX_QUEUE0 << tx_queue; |
283 | } | 291 | } |
284 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); | 292 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
293 | break; | ||
294 | case e1000_82576: | ||
295 | /* Kawela uses a table-based method for assigning vectors. | ||
296 | Each queue has a single entry in the table to which we write | ||
297 | a vector number along with a "valid" bit. Sadly, the layout | ||
298 | of the table is somewhat counterintuitive. */ | ||
299 | if (rx_queue > IGB_N0_QUEUE) { | ||
300 | index = (rx_queue & 0x7); | ||
301 | ivar = array_rd32(E1000_IVAR0, index); | ||
302 | if (rx_queue < 8) { | ||
303 | /* vector goes into low byte of register */ | ||
304 | ivar = ivar & 0xFFFFFF00; | ||
305 | ivar |= msix_vector | E1000_IVAR_VALID; | ||
306 | } else { | ||
307 | /* vector goes into third byte of register */ | ||
308 | ivar = ivar & 0xFF00FFFF; | ||
309 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | ||
310 | } | ||
311 | adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector; | ||
312 | array_wr32(E1000_IVAR0, index, ivar); | ||
313 | } | ||
314 | if (tx_queue > IGB_N0_QUEUE) { | ||
315 | index = (tx_queue & 0x7); | ||
316 | ivar = array_rd32(E1000_IVAR0, index); | ||
317 | if (tx_queue < 8) { | ||
318 | /* vector goes into second byte of register */ | ||
319 | ivar = ivar & 0xFFFF00FF; | ||
320 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | ||
321 | } else { | ||
322 | /* vector goes into high byte of register */ | ||
323 | ivar = ivar & 0x00FFFFFF; | ||
324 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | ||
325 | } | ||
326 | adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector; | ||
327 | array_wr32(E1000_IVAR0, index, ivar); | ||
328 | } | ||
329 | break; | ||
330 | default: | ||
331 | BUG(); | ||
332 | break; | ||
333 | } | ||
285 | } | 334 | } |
286 | 335 | ||
287 | /** | 336 | /** |
@@ -297,6 +346,12 @@ static void igb_configure_msix(struct igb_adapter *adapter) | |||
297 | struct e1000_hw *hw = &adapter->hw; | 346 | struct e1000_hw *hw = &adapter->hw; |
298 | 347 | ||
299 | adapter->eims_enable_mask = 0; | 348 | adapter->eims_enable_mask = 0; |
349 | if (hw->mac.type == e1000_82576) | ||
350 | /* Turn on MSI-X capability first, or our settings | ||
351 | * won't stick. And it will take days to debug. */ | ||
352 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | ||
353 | E1000_GPIE_PBA | E1000_GPIE_EIAME | | ||
354 | E1000_GPIE_NSICR); | ||
300 | 355 | ||
301 | for (i = 0; i < adapter->num_tx_queues; i++) { | 356 | for (i = 0; i < adapter->num_tx_queues; i++) { |
302 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | 357 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; |
@@ -322,6 +377,8 @@ static void igb_configure_msix(struct igb_adapter *adapter) | |||
322 | 377 | ||
323 | 378 | ||
324 | /* set vector for other causes, i.e. link changes */ | 379 | /* set vector for other causes, i.e. link changes */ |
380 | switch (hw->mac.type) { | ||
381 | case e1000_82575: | ||
325 | array_wr32(E1000_MSIXBM(0), vector++, | 382 | array_wr32(E1000_MSIXBM(0), vector++, |
326 | E1000_EIMS_OTHER); | 383 | E1000_EIMS_OTHER); |
327 | 384 | ||
@@ -337,6 +394,19 @@ static void igb_configure_msix(struct igb_adapter *adapter) | |||
337 | adapter->eims_enable_mask |= E1000_EIMS_OTHER; | 394 | adapter->eims_enable_mask |= E1000_EIMS_OTHER; |
338 | adapter->eims_other = E1000_EIMS_OTHER; | 395 | adapter->eims_other = E1000_EIMS_OTHER; |
339 | 396 | ||
397 | break; | ||
398 | |||
399 | case e1000_82576: | ||
400 | tmp = (vector++ | E1000_IVAR_VALID) << 8; | ||
401 | wr32(E1000_IVAR_MISC, tmp); | ||
402 | |||
403 | adapter->eims_enable_mask = (1 << (vector)) - 1; | ||
404 | adapter->eims_other = 1 << (vector - 1); | ||
405 | break; | ||
406 | default: | ||
407 | /* do nothing, since nothing else supports MSI-X */ | ||
408 | break; | ||
409 | } /* switch (hw->mac.type) */ | ||
340 | wrfl(); | 410 | wrfl(); |
341 | } | 411 | } |
342 | 412 | ||
@@ -474,8 +544,17 @@ static int igb_request_irq(struct igb_adapter *adapter) | |||
474 | adapter->num_rx_queues = 1; | 544 | adapter->num_rx_queues = 1; |
475 | igb_alloc_queues(adapter); | 545 | igb_alloc_queues(adapter); |
476 | } else { | 546 | } else { |
477 | wr32(E1000_MSIXBM(0), (E1000_EICR_RX_QUEUE0 | | 547 | switch (hw->mac.type) { |
478 | E1000_EIMS_OTHER)); | 548 | case e1000_82575: |
549 | wr32(E1000_MSIXBM(0), | ||
550 | (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER)); | ||
551 | break; | ||
552 | case e1000_82576: | ||
553 | wr32(E1000_IVAR0, E1000_IVAR_VALID); | ||
554 | break; | ||
555 | default: | ||
556 | break; | ||
557 | } | ||
479 | } | 558 | } |
480 | 559 | ||
481 | if (adapter->msi_enabled) { | 560 | if (adapter->msi_enabled) { |
@@ -770,16 +849,23 @@ void igb_reinit_locked(struct igb_adapter *adapter) | |||
770 | void igb_reset(struct igb_adapter *adapter) | 849 | void igb_reset(struct igb_adapter *adapter) |
771 | { | 850 | { |
772 | struct e1000_hw *hw = &adapter->hw; | 851 | struct e1000_hw *hw = &adapter->hw; |
773 | struct e1000_fc_info *fc = &adapter->hw.fc; | 852 | struct e1000_mac_info *mac = &hw->mac; |
853 | struct e1000_fc_info *fc = &hw->fc; | ||
774 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; | 854 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; |
775 | u16 hwm; | 855 | u16 hwm; |
776 | 856 | ||
777 | /* Repartition Pba for greater than 9k mtu | 857 | /* Repartition Pba for greater than 9k mtu |
778 | * To take effect CTRL.RST is required. | 858 | * To take effect CTRL.RST is required. |
779 | */ | 859 | */ |
860 | if (mac->type != e1000_82576) { | ||
780 | pba = E1000_PBA_34K; | 861 | pba = E1000_PBA_34K; |
862 | } | ||
863 | else { | ||
864 | pba = E1000_PBA_64K; | ||
865 | } | ||
781 | 866 | ||
782 | if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) { | 867 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
868 | (mac->type < e1000_82576)) { | ||
783 | /* adjust PBA for jumbo frames */ | 869 | /* adjust PBA for jumbo frames */ |
784 | wr32(E1000_PBA, pba); | 870 | wr32(E1000_PBA, pba); |
785 | 871 | ||
@@ -818,8 +904,8 @@ void igb_reset(struct igb_adapter *adapter) | |||
818 | if (pba < min_rx_space) | 904 | if (pba < min_rx_space) |
819 | pba = min_rx_space; | 905 | pba = min_rx_space; |
820 | } | 906 | } |
907 | wr32(E1000_PBA, pba); | ||
821 | } | 908 | } |
822 | wr32(E1000_PBA, pba); | ||
823 | 909 | ||
824 | /* flow control settings */ | 910 | /* flow control settings */ |
825 | /* The high water mark must be low enough to fit one full frame | 911 | /* The high water mark must be low enough to fit one full frame |
@@ -828,10 +914,15 @@ void igb_reset(struct igb_adapter *adapter) | |||
828 | * - 90% of the Rx FIFO size, or | 914 | * - 90% of the Rx FIFO size, or |
829 | * - the full Rx FIFO size minus one full frame */ | 915 | * - the full Rx FIFO size minus one full frame */ |
830 | hwm = min(((pba << 10) * 9 / 10), | 916 | hwm = min(((pba << 10) * 9 / 10), |
831 | ((pba << 10) - adapter->max_frame_size)); | 917 | ((pba << 10) - 2 * adapter->max_frame_size)); |
832 | 918 | ||
833 | fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ | 919 | if (mac->type < e1000_82576) { |
834 | fc->low_water = fc->high_water - 8; | 920 | fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ |
921 | fc->low_water = fc->high_water - 8; | ||
922 | } else { | ||
923 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ | ||
924 | fc->low_water = fc->high_water - 16; | ||
925 | } | ||
835 | fc->pause_time = 0xFFFF; | 926 | fc->pause_time = 0xFFFF; |
836 | fc->send_xon = 1; | 927 | fc->send_xon = 1; |
837 | fc->type = fc->original_type; | 928 | fc->type = fc->original_type; |
@@ -1118,9 +1209,12 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
1118 | * lan on a particular port */ | 1209 | * lan on a particular port */ |
1119 | switch (pdev->device) { | 1210 | switch (pdev->device) { |
1120 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | 1211 | case E1000_DEV_ID_82575GB_QUAD_COPPER: |
1212 | case E1000_DEV_ID_82576_QUAD_COPPER: | ||
1121 | adapter->eeprom_wol = 0; | 1213 | adapter->eeprom_wol = 0; |
1122 | break; | 1214 | break; |
1123 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | 1215 | case E1000_DEV_ID_82575EB_FIBER_SERDES: |
1216 | case E1000_DEV_ID_82576_FIBER: | ||
1217 | case E1000_DEV_ID_82576_SERDES: | ||
1124 | /* Wake events only supported on port A for dual fiber | 1218 | /* Wake events only supported on port A for dual fiber |
1125 | * regardless of eeprom setting */ | 1219 | * regardless of eeprom setting */ |
1126 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | 1220 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) |
@@ -1801,7 +1895,10 @@ static void igb_configure_rx(struct igb_adapter *adapter) | |||
1801 | 1895 | ||
1802 | get_random_bytes(&random[0], 40); | 1896 | get_random_bytes(&random[0], 40); |
1803 | 1897 | ||
1804 | shift = 6; | 1898 | if (hw->mac.type >= e1000_82576) |
1899 | shift = 0; | ||
1900 | else | ||
1901 | shift = 6; | ||
1805 | for (j = 0; j < (32 * 4); j++) { | 1902 | for (j = 0; j < (32 * 4); j++) { |
1806 | reta.bytes[j & 3] = | 1903 | reta.bytes[j & 3] = |
1807 | (j % adapter->num_rx_queues) << shift; | 1904 | (j % adapter->num_rx_queues) << shift; |
@@ -2127,7 +2224,7 @@ static void igb_set_multi(struct net_device *netdev) | |||
2127 | 2224 | ||
2128 | if (!netdev->mc_count) { | 2225 | if (!netdev->mc_count) { |
2129 | /* nothing to program, so clear mc list */ | 2226 | /* nothing to program, so clear mc list */ |
2130 | igb_update_mc_addr_list(hw, NULL, 0, 1, | 2227 | igb_update_mc_addr_list_82575(hw, NULL, 0, 1, |
2131 | mac->rar_entry_count); | 2228 | mac->rar_entry_count); |
2132 | return; | 2229 | return; |
2133 | } | 2230 | } |
@@ -2145,7 +2242,8 @@ static void igb_set_multi(struct net_device *netdev) | |||
2145 | memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); | 2242 | memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); |
2146 | mc_ptr = mc_ptr->next; | 2243 | mc_ptr = mc_ptr->next; |
2147 | } | 2244 | } |
2148 | igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count); | 2245 | igb_update_mc_addr_list_82575(hw, mta_list, i, 1, |
2246 | mac->rar_entry_count); | ||
2149 | kfree(mta_list); | 2247 | kfree(mta_list); |
2150 | } | 2248 | } |
2151 | 2249 | ||
@@ -3211,8 +3309,14 @@ static void igb_update_rx_dca(struct igb_ring *rx_ring) | |||
3211 | 3309 | ||
3212 | if (rx_ring->cpu != cpu) { | 3310 | if (rx_ring->cpu != cpu) { |
3213 | dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | 3311 | dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); |
3214 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; | 3312 | if (hw->mac.type == e1000_82576) { |
3215 | dca_rxctrl |= dca_get_tag(cpu); | 3313 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; |
3314 | dca_rxctrl |= dca_get_tag(cpu) << | ||
3315 | E1000_DCA_RXCTRL_CPUID_SHIFT; | ||
3316 | } else { | ||
3317 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; | ||
3318 | dca_rxctrl |= dca_get_tag(cpu); | ||
3319 | } | ||
3216 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; | 3320 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; |
3217 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; | 3321 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; |
3218 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; | 3322 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; |
@@ -3232,8 +3336,14 @@ static void igb_update_tx_dca(struct igb_ring *tx_ring) | |||
3232 | 3336 | ||
3233 | if (tx_ring->cpu != cpu) { | 3337 | if (tx_ring->cpu != cpu) { |
3234 | dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); | 3338 | dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); |
3235 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | 3339 | if (hw->mac.type == e1000_82576) { |
3236 | dca_txctrl |= dca_get_tag(cpu); | 3340 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; |
3341 | dca_txctrl |= dca_get_tag(cpu) << | ||
3342 | E1000_DCA_TXCTRL_CPUID_SHIFT; | ||
3343 | } else { | ||
3344 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | ||
3345 | dca_txctrl |= dca_get_tag(cpu); | ||
3346 | } | ||
3237 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; | 3347 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; |
3238 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | 3348 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); |
3239 | tx_ring->cpu = cpu; | 3349 | tx_ring->cpu = cpu; |
@@ -3572,7 +3682,7 @@ done_cleaning: | |||
3572 | /* detected Tx unit hang */ | 3682 | /* detected Tx unit hang */ |
3573 | dev_err(&adapter->pdev->dev, | 3683 | dev_err(&adapter->pdev->dev, |
3574 | "Detected Tx Unit Hang\n" | 3684 | "Detected Tx Unit Hang\n" |
3575 | " Tx Queue <%lu>\n" | 3685 | " Tx Queue <%d>\n" |
3576 | " TDH <%x>\n" | 3686 | " TDH <%x>\n" |
3577 | " TDT <%x>\n" | 3687 | " TDT <%x>\n" |
3578 | " next_to_use <%x>\n" | 3688 | " next_to_use <%x>\n" |
@@ -3582,8 +3692,7 @@ done_cleaning: | |||
3582 | " time_stamp <%lx>\n" | 3692 | " time_stamp <%lx>\n" |
3583 | " jiffies <%lx>\n" | 3693 | " jiffies <%lx>\n" |
3584 | " desc.status <%x>\n", | 3694 | " desc.status <%x>\n", |
3585 | (unsigned long)((tx_ring - adapter->tx_ring) / | 3695 | tx_ring->queue_index, |
3586 | sizeof(struct igb_ring)), | ||
3587 | readl(adapter->hw.hw_addr + tx_ring->head), | 3696 | readl(adapter->hw.hw_addr + tx_ring->head), |
3588 | readl(adapter->hw.hw_addr + tx_ring->tail), | 3697 | readl(adapter->hw.hw_addr + tx_ring->tail), |
3589 | tx_ring->next_to_use, | 3698 | tx_ring->next_to_use, |
@@ -4098,7 +4207,7 @@ static int igb_suspend(struct pci_dev *pdev, pm_message_t state) | |||
4098 | struct net_device *netdev = pci_get_drvdata(pdev); | 4207 | struct net_device *netdev = pci_get_drvdata(pdev); |
4099 | struct igb_adapter *adapter = netdev_priv(netdev); | 4208 | struct igb_adapter *adapter = netdev_priv(netdev); |
4100 | struct e1000_hw *hw = &adapter->hw; | 4209 | struct e1000_hw *hw = &adapter->hw; |
4101 | u32 ctrl, ctrl_ext, rctl, status; | 4210 | u32 ctrl, rctl, status; |
4102 | u32 wufc = adapter->wol; | 4211 | u32 wufc = adapter->wol; |
4103 | #ifdef CONFIG_PM | 4212 | #ifdef CONFIG_PM |
4104 | int retval = 0; | 4213 | int retval = 0; |
@@ -4141,33 +4250,24 @@ static int igb_suspend(struct pci_dev *pdev, pm_message_t state) | |||
4141 | ctrl |= E1000_CTRL_ADVD3WUC; | 4250 | ctrl |= E1000_CTRL_ADVD3WUC; |
4142 | wr32(E1000_CTRL, ctrl); | 4251 | wr32(E1000_CTRL, ctrl); |
4143 | 4252 | ||
4144 | if (adapter->hw.phy.media_type == e1000_media_type_fiber || | ||
4145 | adapter->hw.phy.media_type == | ||
4146 | e1000_media_type_internal_serdes) { | ||
4147 | /* keep the laser running in D3 */ | ||
4148 | ctrl_ext = rd32(E1000_CTRL_EXT); | ||
4149 | ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA; | ||
4150 | wr32(E1000_CTRL_EXT, ctrl_ext); | ||
4151 | } | ||
4152 | |||
4153 | /* Allow time for pending master requests to run */ | 4253 | /* Allow time for pending master requests to run */ |
4154 | igb_disable_pcie_master(&adapter->hw); | 4254 | igb_disable_pcie_master(&adapter->hw); |
4155 | 4255 | ||
4156 | wr32(E1000_WUC, E1000_WUC_PME_EN); | 4256 | wr32(E1000_WUC, E1000_WUC_PME_EN); |
4157 | wr32(E1000_WUFC, wufc); | 4257 | wr32(E1000_WUFC, wufc); |
4158 | pci_enable_wake(pdev, PCI_D3hot, 1); | ||
4159 | pci_enable_wake(pdev, PCI_D3cold, 1); | ||
4160 | } else { | 4258 | } else { |
4161 | wr32(E1000_WUC, 0); | 4259 | wr32(E1000_WUC, 0); |
4162 | wr32(E1000_WUFC, 0); | 4260 | wr32(E1000_WUFC, 0); |
4163 | pci_enable_wake(pdev, PCI_D3hot, 0); | ||
4164 | pci_enable_wake(pdev, PCI_D3cold, 0); | ||
4165 | } | 4261 | } |
4166 | 4262 | ||
4167 | /* make sure adapter isn't asleep if manageability is enabled */ | 4263 | /* make sure adapter isn't asleep if manageability/wol is enabled */ |
4168 | if (adapter->en_mng_pt) { | 4264 | if (wufc || adapter->en_mng_pt) { |
4169 | pci_enable_wake(pdev, PCI_D3hot, 1); | 4265 | pci_enable_wake(pdev, PCI_D3hot, 1); |
4170 | pci_enable_wake(pdev, PCI_D3cold, 1); | 4266 | pci_enable_wake(pdev, PCI_D3cold, 1); |
4267 | } else { | ||
4268 | igb_shutdown_fiber_serdes_link_82575(hw); | ||
4269 | pci_enable_wake(pdev, PCI_D3hot, 0); | ||
4270 | pci_enable_wake(pdev, PCI_D3cold, 0); | ||
4171 | } | 4271 | } |
4172 | 4272 | ||
4173 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | 4273 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |