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authorAlexander Duyck <alexander.h.duyck@intel.com>2009-10-27 11:49:27 -0400
committerDavid S. Miller <davem@davemloft.net>2009-10-28 04:20:16 -0400
commit047e0030f1e601233ae5b03910602ec93c620bce (patch)
tree3d9cd1d339b150277fe424e7fc9f3aa2a9716665 /drivers/net/igb/igb.h
parent678b77e265f6d66f1e68f3d095841c44ba5ab112 (diff)
igb: add new data structure for handling interrupts and NAPI
Add a new igb_q_vector data structure to handle interrupts and NAPI. This helps to abstract the rings away from the adapter struct. In addition it allows for a bit of consolidation since a tx and rx ring can share a q_vector. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/igb.h')
-rw-r--r--drivers/net/igb/igb.h46
1 files changed, 29 insertions, 17 deletions
diff --git a/drivers/net/igb/igb.h b/drivers/net/igb/igb.h
index b805b1c63f80..86492c8957ec 100644
--- a/drivers/net/igb/igb.h
+++ b/drivers/net/igb/igb.h
@@ -55,6 +55,8 @@ struct igb_adapter;
55#define IGB_DEFAULT_ITR 3 /* dynamic */ 55#define IGB_DEFAULT_ITR 3 /* dynamic */
56#define IGB_MAX_ITR_USECS 10000 56#define IGB_MAX_ITR_USECS 10000
57#define IGB_MIN_ITR_USECS 10 57#define IGB_MIN_ITR_USECS 10
58#define NON_Q_VECTORS 1
59#define MAX_Q_VECTORS 8
58 60
59/* Transmit and receive queues */ 61/* Transmit and receive queues */
60#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? \ 62#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? \
@@ -149,25 +151,38 @@ struct igb_rx_queue_stats {
149 u64 drops; 151 u64 drops;
150}; 152};
151 153
152struct igb_ring { 154struct igb_q_vector {
153 struct igb_adapter *adapter; /* backlink */ 155 struct igb_adapter *adapter; /* backlink */
154 void *desc; /* descriptor ring memory */ 156 struct igb_ring *rx_ring;
155 dma_addr_t dma; /* phys address of the ring */ 157 struct igb_ring *tx_ring;
156 unsigned int size; /* length of desc. ring in bytes */ 158 struct napi_struct napi;
157 unsigned int count; /* number of desc. in the ring */ 159
160 u32 eims_value;
161 u16 cpu;
162
163 u16 itr_val;
164 u8 set_itr;
165 u8 itr_shift;
166 void __iomem *itr_register;
167
168 char name[IFNAMSIZ + 9];
169};
170
171struct igb_ring {
172 struct igb_q_vector *q_vector; /* backlink to q_vector */
173 void *desc; /* descriptor ring memory */
174 dma_addr_t dma; /* phys address of the ring */
175 unsigned int size; /* length of desc. ring in bytes */
176 unsigned int count; /* number of desc. in the ring */
158 u16 next_to_use; 177 u16 next_to_use;
159 u16 next_to_clean; 178 u16 next_to_clean;
160 u16 head; 179 u16 head;
161 u16 tail; 180 u16 tail;
162 struct igb_buffer *buffer_info; /* array of buffer info structs */ 181 struct igb_buffer *buffer_info; /* array of buffer info structs */
163 182
164 u32 eims_value; 183 u8 queue_index;
165 u32 itr_val; 184 u8 reg_idx;
166 u16 itr_register;
167 u16 cpu;
168 185
169 u16 queue_index;
170 u16 reg_idx;
171 unsigned int total_bytes; 186 unsigned int total_bytes;
172 unsigned int total_packets; 187 unsigned int total_packets;
173 188
@@ -181,13 +196,8 @@ struct igb_ring {
181 struct { 196 struct {
182 struct igb_rx_queue_stats rx_stats; 197 struct igb_rx_queue_stats rx_stats;
183 u64 rx_queue_drops; 198 u64 rx_queue_drops;
184 struct napi_struct napi;
185 int set_itr;
186 struct igb_ring *buddy;
187 }; 199 };
188 }; 200 };
189
190 char name[IFNAMSIZ + 5];
191}; 201};
192 202
193#define E1000_RX_DESC_ADV(R, i) \ 203#define E1000_RX_DESC_ADV(R, i) \
@@ -254,7 +264,6 @@ struct igb_adapter {
254 264
255 /* OS defined structs */ 265 /* OS defined structs */
256 struct net_device *netdev; 266 struct net_device *netdev;
257 struct napi_struct napi;
258 struct pci_dev *pdev; 267 struct pci_dev *pdev;
259 struct cyclecounter cycles; 268 struct cyclecounter cycles;
260 struct timecounter clock; 269 struct timecounter clock;
@@ -272,6 +281,9 @@ struct igb_adapter {
272 struct igb_ring test_rx_ring; 281 struct igb_ring test_rx_ring;
273 282
274 int msg_enable; 283 int msg_enable;
284
285 unsigned int num_q_vectors;
286 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
275 struct msix_entry *msix_entries; 287 struct msix_entry *msix_entries;
276 u32 eims_enable_mask; 288 u32 eims_enable_mask;
277 u32 eims_other; 289 u32 eims_other;