diff options
author | Alexander Duyck <alexander.h.duyck@intel.com> | 2009-02-16 02:59:44 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-16 02:59:44 -0500 |
commit | cbd347adfee2ba52a8ef85f92a46933d5840cc39 (patch) | |
tree | 6fe593287cc6486e78201da9419255530046fac1 /drivers/net/igb/e1000_regs.h | |
parent | bc1cbd3493c7a6b44fa6a1e6040ae3d9640d47c4 (diff) |
igb: remove unused defines
This patch removes all of the unused defines from the .h files contained in
igb. For some defines there was a use and so I plugged them into the correct
locations.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_regs.h')
-rw-r--r-- | drivers/net/igb/e1000_regs.h | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h index 1fb19ca081c6..95ed8ec15770 100644 --- a/drivers/net/igb/e1000_regs.h +++ b/drivers/net/igb/e1000_regs.h | |||
@@ -73,7 +73,6 @@ | |||
73 | #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ | 73 | #define E1000_TCPTIMER 0x0104C /* TCP Timer - RW */ |
74 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ | 74 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ |
75 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ | 75 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ |
76 | #define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) | ||
77 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ | 76 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ |
78 | 77 | ||
79 | /* IEEE 1588 TIMESYNCH */ | 78 | /* IEEE 1588 TIMESYNCH */ |
@@ -178,7 +177,6 @@ enum { | |||
178 | : (0x0E018 + ((_n) * 0x40))) | 177 | : (0x0E018 + ((_n) * 0x40))) |
179 | #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ | 178 | #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) \ |
180 | : (0x0E028 + ((_n) * 0x40))) | 179 | : (0x0E028 + ((_n) * 0x40))) |
181 | #define E1000_TARC(_n) (0x03840 + (_n << 8)) | ||
182 | #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) | 180 | #define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8)) |
183 | #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) | 181 | #define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8)) |
184 | #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ | 182 | #define E1000_TDWBAL(_n) ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) \ |
@@ -301,9 +299,7 @@ enum { | |||
301 | #define E1000_MANC 0x05820 /* Management Control - RW */ | 299 | #define E1000_MANC 0x05820 /* Management Control - RW */ |
302 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ | 300 | #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ |
303 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ | 301 | #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ |
304 | #define E1000_HOST_IF 0x08800 /* Host Interface */ | ||
305 | 302 | ||
306 | #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ | ||
307 | #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ | 303 | #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ |
308 | #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ | 304 | #define E1000_CCMCTL 0x05B48 /* CCM Control Register */ |
309 | #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ | 305 | #define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ |
@@ -311,9 +307,7 @@ enum { | |||
311 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ | 307 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ |
312 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ | 308 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ |
313 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ | 309 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ |
314 | #define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ | ||
315 | #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ | 310 | #define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ |
316 | #define E1000_HICR 0x08F00 /* Host Inteface Control */ | ||
317 | 311 | ||
318 | /* RSS registers */ | 312 | /* RSS registers */ |
319 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ | 313 | #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ |
@@ -322,14 +316,6 @@ enum { | |||
322 | #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ | 316 | #define E1000_IMIRVP 0x05AC0 /* Immediate Interrupt RX VLAN Priority - RW */ |
323 | /* MSI-X Allocation Register (_i) - RW */ | 317 | /* MSI-X Allocation Register (_i) - RW */ |
324 | #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) | 318 | #define E1000_MSIXBM(_i) (0x01600 + ((_i) * 4)) |
325 | /* MSI-X Table entry addr low reg 0 - RW */ | ||
326 | #define E1000_MSIXTADD(_i) (0x0C000 + ((_i) * 0x10)) | ||
327 | /* MSI-X Table entry addr upper reg 0 - RW */ | ||
328 | #define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) | ||
329 | /* MSI-X Table entry message reg 0 - RW */ | ||
330 | #define E1000_MSIXTMSG(_i) (0x0C008 + ((_i) * 0x10)) | ||
331 | /* MSI-X Table entry vector ctrl reg 0 - RW */ | ||
332 | #define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) | ||
333 | /* Redirection Table - RW Array */ | 319 | /* Redirection Table - RW Array */ |
334 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) | 320 | #define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) |
335 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ | 321 | #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ |