diff options
author | Alexander Duyck <alexander.h.duyck@intel.com> | 2009-10-27 19:46:01 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-10-28 06:25:33 -0400 |
commit | c5b9bd5e4f7caea10d113f610b85cc2093cc3179 (patch) | |
tree | 034d59e0788e5fd548b411be50aba0fd7228b049 /drivers/net/igb/e1000_regs.h | |
parent | 4fc82adfb01bdee79ec21e44557dc409ef31419a (diff) |
igb: cleanup some of the code related to hw timestamping
The code for the hw timestamping is a bit bulky and making some of the
functions difficult to read. In order to clean things up a bit I am moving
the timestamping operations into seperate functions.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_regs.h')
-rw-r--r-- | drivers/net/igb/e1000_regs.h | 65 |
1 files changed, 12 insertions, 53 deletions
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h index e06c3b706b15..24f2c24d0309 100644 --- a/drivers/net/igb/e1000_regs.h +++ b/drivers/net/igb/e1000_regs.h | |||
@@ -76,59 +76,18 @@ | |||
76 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ | 76 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ |
77 | 77 | ||
78 | /* IEEE 1588 TIMESYNCH */ | 78 | /* IEEE 1588 TIMESYNCH */ |
79 | #define E1000_TSYNCTXCTL 0x0B614 | 79 | #define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */ |
80 | #define E1000_TSYNCTXCTL_VALID (1<<0) | 80 | #define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */ |
81 | #define E1000_TSYNCTXCTL_ENABLED (1<<4) | 81 | #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */ |
82 | #define E1000_TSYNCRXCTL 0x0B620 | 82 | #define E1000_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */ |
83 | #define E1000_TSYNCRXCTL_VALID (1<<0) | 83 | #define E1000_RXSTMPH 0x0B628 /* Rx timestamp High - RO */ |
84 | #define E1000_TSYNCRXCTL_ENABLED (1<<4) | 84 | #define E1000_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */ |
85 | enum { | 85 | #define E1000_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */ |
86 | E1000_TSYNCRXCTL_TYPE_L2_V2 = 0, | 86 | #define E1000_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */ |
87 | E1000_TSYNCRXCTL_TYPE_L4_V1 = (1<<1), | 87 | #define E1000_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */ |
88 | E1000_TSYNCRXCTL_TYPE_L2_L4_V2 = (1<<2), | 88 | #define E1000_SYSTIML 0x0B600 /* System time register Low - RO */ |
89 | E1000_TSYNCRXCTL_TYPE_ALL = (1<<3), | 89 | #define E1000_SYSTIMH 0x0B604 /* System time register High - RO */ |
90 | E1000_TSYNCRXCTL_TYPE_EVENT_V2 = (1<<3) | (1<<1), | 90 | #define E1000_TIMINCA 0x0B608 /* Increment attributes register - RW */ |
91 | }; | ||
92 | #define E1000_TSYNCRXCFG 0x05F50 | ||
93 | enum { | ||
94 | E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE = 0<<0, | ||
95 | E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE = 1<<0, | ||
96 | E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE = 2<<0, | ||
97 | E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE = 3<<0, | ||
98 | E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE = 4<<0, | ||
99 | |||
100 | E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE = 0<<8, | ||
101 | E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE = 1<<8, | ||
102 | E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE = 2<<8, | ||
103 | E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE = 3<<8, | ||
104 | E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE = 8<<8, | ||
105 | E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE = 9<<8, | ||
106 | E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE = 0xA<<8, | ||
107 | E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE = 0xB<<8, | ||
108 | E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE = 0xC<<8, | ||
109 | E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE = 0xD<<8, | ||
110 | }; | ||
111 | #define E1000_SYSTIML 0x0B600 | ||
112 | #define E1000_SYSTIMH 0x0B604 | ||
113 | #define E1000_TIMINCA 0x0B608 | ||
114 | |||
115 | #define E1000_RXMTRL 0x0B634 | ||
116 | #define E1000_RXSTMPL 0x0B624 | ||
117 | #define E1000_RXSTMPH 0x0B628 | ||
118 | #define E1000_RXSATRL 0x0B62C | ||
119 | #define E1000_RXSATRH 0x0B630 | ||
120 | |||
121 | #define E1000_TXSTMPL 0x0B618 | ||
122 | #define E1000_TXSTMPH 0x0B61C | ||
123 | |||
124 | #define E1000_ETQF0 0x05CB0 | ||
125 | #define E1000_ETQF1 0x05CB4 | ||
126 | #define E1000_ETQF2 0x05CB8 | ||
127 | #define E1000_ETQF3 0x05CBC | ||
128 | #define E1000_ETQF4 0x05CC0 | ||
129 | #define E1000_ETQF5 0x05CC4 | ||
130 | #define E1000_ETQF6 0x05CC8 | ||
131 | #define E1000_ETQF7 0x05CCC | ||
132 | 91 | ||
133 | /* Filtering Registers */ | 92 | /* Filtering Registers */ |
134 | #define E1000_SAQF(_n) (0x5980 + 4 * (_n)) | 93 | #define E1000_SAQF(_n) (0x5980 + 4 * (_n)) |