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authorPatrick Ohly <patrick.ohly@intel.com>2009-02-12 00:03:43 -0500
committerDavid S. Miller <davem@davemloft.net>2009-02-16 02:13:27 -0500
commit33af6bcc005a826726b48e8775df5d58112bc10b (patch)
treef56d49b32b2183e076741b590bb7ebd797d53c99 /drivers/net/igb/e1000_regs.h
parentc6cb090ba7cd88aec03718dab76e4dad56862cae (diff)
igb: use timecompare to implement hardware time stamping
Both TX and RX hardware time stamping are implemented. Due to hardware limitations it is not possible to verify reliably which packet was time stamped when multiple were pending for sending; this could be solved by only allowing one packet marked for hardware time stamping into the queue (not implemented yet). RX time stamping relies on the flag in the packet descriptor which marks packets that were time stamped. In "all packet" mode this flag is not set. TODO: also support that mode (even though it'll suffer from race conditions). Signed-off-by: John Ronciak <john.ronciak@intel.com> Signed-off-by: Patrick Ohly <patrick.ohly@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_regs.h')
-rw-r--r--drivers/net/igb/e1000_regs.h40
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h
index 64d95cd71f2e..1fb19ca081c6 100644
--- a/drivers/net/igb/e1000_regs.h
+++ b/drivers/net/igb/e1000_regs.h
@@ -78,9 +78,37 @@
78 78
79/* IEEE 1588 TIMESYNCH */ 79/* IEEE 1588 TIMESYNCH */
80#define E1000_TSYNCTXCTL 0x0B614 80#define E1000_TSYNCTXCTL 0x0B614
81#define E1000_TSYNCTXCTL_VALID (1<<0)
82#define E1000_TSYNCTXCTL_ENABLED (1<<4)
81#define E1000_TSYNCRXCTL 0x0B620 83#define E1000_TSYNCRXCTL 0x0B620
84#define E1000_TSYNCRXCTL_VALID (1<<0)
85#define E1000_TSYNCRXCTL_ENABLED (1<<4)
86enum {
87 E1000_TSYNCRXCTL_TYPE_L2_V2 = 0,
88 E1000_TSYNCRXCTL_TYPE_L4_V1 = (1<<1),
89 E1000_TSYNCRXCTL_TYPE_L2_L4_V2 = (1<<2),
90 E1000_TSYNCRXCTL_TYPE_ALL = (1<<3),
91 E1000_TSYNCRXCTL_TYPE_EVENT_V2 = (1<<3) | (1<<1),
92};
82#define E1000_TSYNCRXCFG 0x05F50 93#define E1000_TSYNCRXCFG 0x05F50
94enum {
95 E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE = 0<<0,
96 E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE = 1<<0,
97 E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE = 2<<0,
98 E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE = 3<<0,
99 E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE = 4<<0,
83 100
101 E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE = 0<<8,
102 E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE = 1<<8,
103 E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE = 2<<8,
104 E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE = 3<<8,
105 E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE = 8<<8,
106 E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE = 9<<8,
107 E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE = 0xA<<8,
108 E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE = 0xB<<8,
109 E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE = 0xC<<8,
110 E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE = 0xD<<8,
111};
84#define E1000_SYSTIML 0x0B600 112#define E1000_SYSTIML 0x0B600
85#define E1000_SYSTIMH 0x0B604 113#define E1000_SYSTIMH 0x0B604
86#define E1000_TIMINCA 0x0B608 114#define E1000_TIMINCA 0x0B608
@@ -103,6 +131,18 @@
103#define E1000_ETQF6 0x05CC8 131#define E1000_ETQF6 0x05CC8
104#define E1000_ETQF7 0x05CCC 132#define E1000_ETQF7 0x05CCC
105 133
134/* Filtering Registers */
135#define E1000_SAQF(_n) (0x5980 + 4 * (_n))
136#define E1000_DAQF(_n) (0x59A0 + 4 * (_n))
137#define E1000_SPQF(_n) (0x59C0 + 4 * (_n))
138#define E1000_FTQF(_n) (0x59E0 + 4 * (_n))
139#define E1000_SAQF0 E1000_SAQF(0)
140#define E1000_DAQF0 E1000_DAQF(0)
141#define E1000_SPQF0 E1000_SPQF(0)
142#define E1000_FTQF0 E1000_FTQF(0)
143#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
144#define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
145
106/* Split and Replication RX Control - RW */ 146/* Split and Replication RX Control - RW */
107/* 147/*
108 * Convenience macros 148 * Convenience macros