diff options
author | Patrick Ohly <patrick.ohly@intel.com> | 2009-02-12 00:03:41 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-16 02:13:25 -0500 |
commit | 38c845c7648ee354fd1d2fb8a7fbc352f2d3dcc3 (patch) | |
tree | aa55b7d582dadb2735079f92f7fe246069647ae7 /drivers/net/igb/e1000_regs.h | |
parent | d24fff22d8dba13cc21034144f68f213415cb7c8 (diff) |
igb: access to NIC time
Adds the register definitions and code to read the time
register.
Signed-off-by: John Ronciak <john.ronciak@intel.com>
Signed-off-by: Patrick Ohly <patrick.ohly@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_regs.h')
-rw-r--r-- | drivers/net/igb/e1000_regs.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h index 5038b73c78e9..64d95cd71f2e 100644 --- a/drivers/net/igb/e1000_regs.h +++ b/drivers/net/igb/e1000_regs.h | |||
@@ -75,6 +75,34 @@ | |||
75 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ | 75 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ |
76 | #define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) | 76 | #define E1000_RDFPCQ(_n) (0x02430 + (0x4 * (_n))) |
77 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ | 77 | #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */ |
78 | |||
79 | /* IEEE 1588 TIMESYNCH */ | ||
80 | #define E1000_TSYNCTXCTL 0x0B614 | ||
81 | #define E1000_TSYNCRXCTL 0x0B620 | ||
82 | #define E1000_TSYNCRXCFG 0x05F50 | ||
83 | |||
84 | #define E1000_SYSTIML 0x0B600 | ||
85 | #define E1000_SYSTIMH 0x0B604 | ||
86 | #define E1000_TIMINCA 0x0B608 | ||
87 | |||
88 | #define E1000_RXMTRL 0x0B634 | ||
89 | #define E1000_RXSTMPL 0x0B624 | ||
90 | #define E1000_RXSTMPH 0x0B628 | ||
91 | #define E1000_RXSATRL 0x0B62C | ||
92 | #define E1000_RXSATRH 0x0B630 | ||
93 | |||
94 | #define E1000_TXSTMPL 0x0B618 | ||
95 | #define E1000_TXSTMPH 0x0B61C | ||
96 | |||
97 | #define E1000_ETQF0 0x05CB0 | ||
98 | #define E1000_ETQF1 0x05CB4 | ||
99 | #define E1000_ETQF2 0x05CB8 | ||
100 | #define E1000_ETQF3 0x05CBC | ||
101 | #define E1000_ETQF4 0x05CC0 | ||
102 | #define E1000_ETQF5 0x05CC4 | ||
103 | #define E1000_ETQF6 0x05CC8 | ||
104 | #define E1000_ETQF7 0x05CCC | ||
105 | |||
78 | /* Split and Replication RX Control - RW */ | 106 | /* Split and Replication RX Control - RW */ |
79 | /* | 107 | /* |
80 | * Convenience macros | 108 | * Convenience macros |