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authorAlexander Duyck <alexander.h.duyck@intel.com>2008-07-08 18:10:12 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-07-11 01:20:32 -0400
commit2d064c06fecadadcb81a452acd373af00dfb1fec (patch)
tree760bc30311966bd406a9f21725bc13cd34755de2 /drivers/net/igb/e1000_regs.h
parent0024fd00cd404b418b6e6a7408700814cfe7b3dd (diff)
igb: add 82576 MAC support
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/igb/e1000_regs.h')
-rw-r--r--drivers/net/igb/e1000_regs.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h
index d25e914df975..b95093d24c09 100644
--- a/drivers/net/igb/e1000_regs.h
+++ b/drivers/net/igb/e1000_regs.h
@@ -56,6 +56,9 @@
56#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 56#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
57#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 57#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
58#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 58#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
59#define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
60#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
61#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
59#define E1000_TCTL 0x00400 /* TX Control - RW */ 62#define E1000_TCTL 0x00400 /* TX Control - RW */
60#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 63#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
61#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 64#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
@@ -217,6 +220,7 @@
217#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 220#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
218#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 221#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
219#define E1000_RA 0x05400 /* Receive Address - RW Array */ 222#define E1000_RA 0x05400 /* Receive Address - RW Array */
223#define E1000_RA2 0x054E0 /* 2nd half of receive address array - RW Array */
220#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 224#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
221#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */ 225#define E1000_VMD_CTL 0x0581C /* VMDq Control - RW */
222#define E1000_WUC 0x05800 /* Wakeup Control - RW */ 226#define E1000_WUC 0x05800 /* Wakeup Control - RW */
@@ -258,7 +262,8 @@
258#define E1000_RETA(_i) (0x05C00 + ((_i) * 4)) 262#define E1000_RETA(_i) (0x05C00 + ((_i) * 4))
259#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */ 263#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW Array */
260 264
261#define E1000_REGISTER(a, reg) reg 265#define E1000_REGISTER(a, reg) (((a)->mac.type < e1000_82576) \
266 ? reg : e1000_translate_register_82576(reg))
262 267
263#define wr32(reg, value) (writel(value, hw->hw_addr + reg)) 268#define wr32(reg, value) (writel(value, hw->hw_addr + reg))
264#define rd32(reg) (readl(hw->hw_addr + reg)) 269#define rd32(reg) (readl(hw->hw_addr + reg))