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authorAuke Kok <auke-jan.h.kok@intel.com>2008-01-24 05:22:38 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:10:33 -0500
commit9d5c824399dea881779d78a6c147288bf2dccb6b (patch)
tree8c76b20c3cf1d81a63973e97578cea6a8a82a354 /drivers/net/igb/e1000_phy.c
parentb491edd5817f1618f4e06d67638739591a714bdb (diff)
igb: PCI-Express 82575 Gigabit Ethernet driver
We are pleased to announce a new Gigabit Ethernet product and its driver to the linux community. This product is the Intel(R) 82575 Gigabit Ethernet adapter family. Physical adapters will be available to the public soon. These adapters come in 2- and 4-port versions (copper PHY) currently. Other variants will be available later. The 82575 chipset supports significantly different features that warrant a new driver. The descriptor format is (just like the ixgbe driver) different. The device can use multiple MSI-X vectors and multiple queues for both send and receive. This allows us to optimize some of the driver code specifically as well compared to the e1000-supported devices. This version of the igb driver no lnger uses fake netdevices and incorporates napi_struct members for each ring to do the multi- queue polling. multi-queue is enabled by default and the driver supports NAPI mode only. All the namespace collisions should be gone in this version too. The register macro's have been condensed to improve readability. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_phy.c')
-rw-r--r--drivers/net/igb/e1000_phy.c1807
1 files changed, 1807 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_phy.c b/drivers/net/igb/e1000_phy.c
new file mode 100644
index 000000000000..08a86b107229
--- /dev/null
+++ b/drivers/net/igb/e1000_phy.c
@@ -0,0 +1,1807 @@
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/if_ether.h>
29#include <linux/delay.h>
30
31#include "e1000_mac.h"
32#include "e1000_phy.h"
33
34static s32 igb_get_phy_cfg_done(struct e1000_hw *hw);
35static void igb_release_phy(struct e1000_hw *hw);
36static s32 igb_acquire_phy(struct e1000_hw *hw);
37static s32 igb_phy_reset_dsp(struct e1000_hw *hw);
38static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
39static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
40 u16 *phy_ctrl);
41static s32 igb_wait_autoneg(struct e1000_hw *hw);
42
43/* Cable length tables */
44static const u16 e1000_m88_cable_length_table[] =
45 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
46#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
47 (sizeof(e1000_m88_cable_length_table) / \
48 sizeof(e1000_m88_cable_length_table[0]))
49
50static const u16 e1000_igp_2_cable_length_table[] =
51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
52 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
53 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
54 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
55 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
56 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
57 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
58 104, 109, 114, 118, 121, 124};
59#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 (sizeof(e1000_igp_2_cable_length_table) / \
61 sizeof(e1000_igp_2_cable_length_table[0]))
62
63/**
64 * e1000_check_reset_block - Check if PHY reset is blocked
65 * @hw: pointer to the HW structure
66 *
67 * Read the PHY management control register and check whether a PHY reset
68 * is blocked. If a reset is not blocked return 0, otherwise
69 * return E1000_BLK_PHY_RESET (12).
70 **/
71s32 igb_check_reset_block(struct e1000_hw *hw)
72{
73 u32 manc;
74
75 manc = rd32(E1000_MANC);
76
77 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
78 E1000_BLK_PHY_RESET : 0;
79}
80
81/**
82 * e1000_get_phy_id - Retrieve the PHY ID and revision
83 * @hw: pointer to the HW structure
84 *
85 * Reads the PHY registers and stores the PHY ID and possibly the PHY
86 * revision in the hardware structure.
87 **/
88s32 igb_get_phy_id(struct e1000_hw *hw)
89{
90 struct e1000_phy_info *phy = &hw->phy;
91 s32 ret_val = 0;
92 u16 phy_id;
93
94 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID1, &phy_id);
95 if (ret_val)
96 goto out;
97
98 phy->id = (u32)(phy_id << 16);
99 udelay(20);
100 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_ID2, &phy_id);
101 if (ret_val)
102 goto out;
103
104 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
105 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
106
107out:
108 return ret_val;
109}
110
111/**
112 * e1000_phy_reset_dsp - Reset PHY DSP
113 * @hw: pointer to the HW structure
114 *
115 * Reset the digital signal processor.
116 **/
117static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
118{
119 s32 ret_val;
120
121 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
122 if (ret_val)
123 goto out;
124
125 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
126
127out:
128 return ret_val;
129}
130
131/**
132 * e1000_read_phy_reg_mdic - Read MDI control register
133 * @hw: pointer to the HW structure
134 * @offset: register offset to be read
135 * @data: pointer to the read data
136 *
137 * Reads the MDI control regsiter in the PHY at offset and stores the
138 * information read to data.
139 **/
140static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
141{
142 struct e1000_phy_info *phy = &hw->phy;
143 u32 i, mdic = 0;
144 s32 ret_val = 0;
145
146 if (offset > MAX_PHY_REG_ADDRESS) {
147 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
148 ret_val = -E1000_ERR_PARAM;
149 goto out;
150 }
151
152 /*
153 * Set up Op-code, Phy Address, and register offset in the MDI
154 * Control register. The MAC will take care of interfacing with the
155 * PHY to retrieve the desired data.
156 */
157 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
158 (phy->addr << E1000_MDIC_PHY_SHIFT) |
159 (E1000_MDIC_OP_READ));
160
161 wr32(E1000_MDIC, mdic);
162
163 /*
164 * Poll the ready bit to see if the MDI read completed
165 * Increasing the time out as testing showed failures with
166 * the lower time out
167 */
168 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
169 udelay(50);
170 mdic = rd32(E1000_MDIC);
171 if (mdic & E1000_MDIC_READY)
172 break;
173 }
174 if (!(mdic & E1000_MDIC_READY)) {
175 hw_dbg(hw, "MDI Read did not complete\n");
176 ret_val = -E1000_ERR_PHY;
177 goto out;
178 }
179 if (mdic & E1000_MDIC_ERROR) {
180 hw_dbg(hw, "MDI Error\n");
181 ret_val = -E1000_ERR_PHY;
182 goto out;
183 }
184 *data = (u16) mdic;
185
186out:
187 return ret_val;
188}
189
190/**
191 * e1000_write_phy_reg_mdic - Write MDI control register
192 * @hw: pointer to the HW structure
193 * @offset: register offset to write to
194 * @data: data to write to register at offset
195 *
196 * Writes data to MDI control register in the PHY at offset.
197 **/
198static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
199{
200 struct e1000_phy_info *phy = &hw->phy;
201 u32 i, mdic = 0;
202 s32 ret_val = 0;
203
204 if (offset > MAX_PHY_REG_ADDRESS) {
205 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
206 ret_val = -E1000_ERR_PARAM;
207 goto out;
208 }
209
210 /*
211 * Set up Op-code, Phy Address, and register offset in the MDI
212 * Control register. The MAC will take care of interfacing with the
213 * PHY to retrieve the desired data.
214 */
215 mdic = (((u32)data) |
216 (offset << E1000_MDIC_REG_SHIFT) |
217 (phy->addr << E1000_MDIC_PHY_SHIFT) |
218 (E1000_MDIC_OP_WRITE));
219
220 wr32(E1000_MDIC, mdic);
221
222 /*
223 * Poll the ready bit to see if the MDI read completed
224 * Increasing the time out as testing showed failures with
225 * the lower time out
226 */
227 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
228 udelay(50);
229 mdic = rd32(E1000_MDIC);
230 if (mdic & E1000_MDIC_READY)
231 break;
232 }
233 if (!(mdic & E1000_MDIC_READY)) {
234 hw_dbg(hw, "MDI Write did not complete\n");
235 ret_val = -E1000_ERR_PHY;
236 goto out;
237 }
238 if (mdic & E1000_MDIC_ERROR) {
239 hw_dbg(hw, "MDI Error\n");
240 ret_val = -E1000_ERR_PHY;
241 goto out;
242 }
243
244out:
245 return ret_val;
246}
247
248/**
249 * e1000_read_phy_reg_igp - Read igp PHY register
250 * @hw: pointer to the HW structure
251 * @offset: register offset to be read
252 * @data: pointer to the read data
253 *
254 * Acquires semaphore, if necessary, then reads the PHY register at offset
255 * and storing the retrieved information in data. Release any acquired
256 * semaphores before exiting.
257 **/
258s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
259{
260 s32 ret_val;
261
262 ret_val = igb_acquire_phy(hw);
263 if (ret_val)
264 goto out;
265
266 if (offset > MAX_PHY_MULTI_PAGE_REG) {
267 ret_val = igb_write_phy_reg_mdic(hw,
268 IGP01E1000_PHY_PAGE_SELECT,
269 (u16)offset);
270 if (ret_val) {
271 igb_release_phy(hw);
272 goto out;
273 }
274 }
275
276 ret_val = igb_read_phy_reg_mdic(hw,
277 MAX_PHY_REG_ADDRESS & offset,
278 data);
279
280 igb_release_phy(hw);
281
282out:
283 return ret_val;
284}
285
286/**
287 * e1000_write_phy_reg_igp - Write igp PHY register
288 * @hw: pointer to the HW structure
289 * @offset: register offset to write to
290 * @data: data to write at register offset
291 *
292 * Acquires semaphore, if necessary, then writes the data to PHY register
293 * at the offset. Release any acquired semaphores before exiting.
294 **/
295s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
296{
297 s32 ret_val;
298
299 ret_val = igb_acquire_phy(hw);
300 if (ret_val)
301 goto out;
302
303 if (offset > MAX_PHY_MULTI_PAGE_REG) {
304 ret_val = igb_write_phy_reg_mdic(hw,
305 IGP01E1000_PHY_PAGE_SELECT,
306 (u16)offset);
307 if (ret_val) {
308 igb_release_phy(hw);
309 goto out;
310 }
311 }
312
313 ret_val = igb_write_phy_reg_mdic(hw,
314 MAX_PHY_REG_ADDRESS & offset,
315 data);
316
317 igb_release_phy(hw);
318
319out:
320 return ret_val;
321}
322
323/**
324 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
325 * @hw: pointer to the HW structure
326 *
327 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
328 * and downshift values are set also.
329 **/
330s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
331{
332 struct e1000_phy_info *phy = &hw->phy;
333 s32 ret_val;
334 u16 phy_data;
335
336 if (phy->reset_disable) {
337 ret_val = 0;
338 goto out;
339 }
340
341 /* Enable CRS on TX. This must be set for half-duplex operation. */
342 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
343 &phy_data);
344 if (ret_val)
345 goto out;
346
347 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
348
349 /*
350 * Options:
351 * MDI/MDI-X = 0 (default)
352 * 0 - Auto for all speeds
353 * 1 - MDI mode
354 * 2 - MDI-X mode
355 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
356 */
357 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
358
359 switch (phy->mdix) {
360 case 1:
361 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
362 break;
363 case 2:
364 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
365 break;
366 case 3:
367 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
368 break;
369 case 0:
370 default:
371 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
372 break;
373 }
374
375 /*
376 * Options:
377 * disable_polarity_correction = 0 (default)
378 * Automatic Correction for Reversed Cable Polarity
379 * 0 - Disabled
380 * 1 - Enabled
381 */
382 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
383 if (phy->disable_polarity_correction == 1)
384 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
385
386 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
387 phy_data);
388 if (ret_val)
389 goto out;
390
391 if (phy->revision < E1000_REVISION_4) {
392 /*
393 * Force TX_CLK in the Extended PHY Specific Control Register
394 * to 25MHz clock.
395 */
396 ret_val = hw->phy.ops.read_phy_reg(hw,
397 M88E1000_EXT_PHY_SPEC_CTRL,
398 &phy_data);
399 if (ret_val)
400 goto out;
401
402 phy_data |= M88E1000_EPSCR_TX_CLK_25;
403
404 if ((phy->revision == E1000_REVISION_2) &&
405 (phy->id == M88E1111_I_PHY_ID)) {
406 /* 82573L PHY - set the downshift counter to 5x. */
407 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
408 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
409 } else {
410 /* Configure Master and Slave downshift values */
411 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
412 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
413 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
414 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
415 }
416 ret_val = hw->phy.ops.write_phy_reg(hw,
417 M88E1000_EXT_PHY_SPEC_CTRL,
418 phy_data);
419 if (ret_val)
420 goto out;
421 }
422
423 /* Commit the changes. */
424 ret_val = igb_phy_sw_reset(hw);
425 if (ret_val) {
426 hw_dbg(hw, "Error committing the PHY changes\n");
427 goto out;
428 }
429
430out:
431 return ret_val;
432}
433
434/**
435 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
436 * @hw: pointer to the HW structure
437 *
438 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
439 * igp PHY's.
440 **/
441s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
442{
443 struct e1000_phy_info *phy = &hw->phy;
444 s32 ret_val;
445 u16 data;
446
447 if (phy->reset_disable) {
448 ret_val = 0;
449 goto out;
450 }
451
452 ret_val = hw->phy.ops.reset_phy(hw);
453 if (ret_val) {
454 hw_dbg(hw, "Error resetting the PHY.\n");
455 goto out;
456 }
457
458 /* Wait 15ms for MAC to configure PHY from NVM settings. */
459 msleep(15);
460
461 /*
462 * The NVM settings will configure LPLU in D3 for
463 * non-IGP1 PHYs.
464 */
465 if (phy->type == e1000_phy_igp) {
466 /* disable lplu d3 during driver init */
467 if (hw->phy.ops.set_d3_lplu_state)
468 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
469 if (ret_val) {
470 hw_dbg(hw, "Error Disabling LPLU D3\n");
471 goto out;
472 }
473 }
474
475 /* disable lplu d0 during driver init */
476 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
477 if (ret_val) {
478 hw_dbg(hw, "Error Disabling LPLU D0\n");
479 goto out;
480 }
481 /* Configure mdi-mdix settings */
482 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
483 if (ret_val)
484 goto out;
485
486 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
487
488 switch (phy->mdix) {
489 case 1:
490 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
491 break;
492 case 2:
493 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
494 break;
495 case 0:
496 default:
497 data |= IGP01E1000_PSCR_AUTO_MDIX;
498 break;
499 }
500 ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
501 if (ret_val)
502 goto out;
503
504 /* set auto-master slave resolution settings */
505 if (hw->mac.autoneg) {
506 /*
507 * when autonegotiation advertisement is only 1000Mbps then we
508 * should disable SmartSpeed and enable Auto MasterSlave
509 * resolution as hardware default.
510 */
511 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
512 /* Disable SmartSpeed */
513 ret_val = hw->phy.ops.read_phy_reg(hw,
514 IGP01E1000_PHY_PORT_CONFIG,
515 &data);
516 if (ret_val)
517 goto out;
518
519 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
520 ret_val = hw->phy.ops.write_phy_reg(hw,
521 IGP01E1000_PHY_PORT_CONFIG,
522 data);
523 if (ret_val)
524 goto out;
525
526 /* Set auto Master/Slave resolution process */
527 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL,
528 &data);
529 if (ret_val)
530 goto out;
531
532 data &= ~CR_1000T_MS_ENABLE;
533 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL,
534 data);
535 if (ret_val)
536 goto out;
537 }
538
539 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_CTRL, &data);
540 if (ret_val)
541 goto out;
542
543 /* load defaults for future use */
544 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
545 ((data & CR_1000T_MS_VALUE) ?
546 e1000_ms_force_master :
547 e1000_ms_force_slave) :
548 e1000_ms_auto;
549
550 switch (phy->ms_type) {
551 case e1000_ms_force_master:
552 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
553 break;
554 case e1000_ms_force_slave:
555 data |= CR_1000T_MS_ENABLE;
556 data &= ~(CR_1000T_MS_VALUE);
557 break;
558 case e1000_ms_auto:
559 data &= ~CR_1000T_MS_ENABLE;
560 default:
561 break;
562 }
563 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_1000T_CTRL, data);
564 if (ret_val)
565 goto out;
566 }
567
568out:
569 return ret_val;
570}
571
572/**
573 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
574 * @hw: pointer to the HW structure
575 *
576 * Performs initial bounds checking on autoneg advertisement parameter, then
577 * configure to advertise the full capability. Setup the PHY to autoneg
578 * and restart the negotiation process between the link partner. If
579 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
580 **/
581s32 igb_copper_link_autoneg(struct e1000_hw *hw)
582{
583 struct e1000_phy_info *phy = &hw->phy;
584 s32 ret_val;
585 u16 phy_ctrl;
586
587 /*
588 * Perform some bounds checking on the autoneg advertisement
589 * parameter.
590 */
591 phy->autoneg_advertised &= phy->autoneg_mask;
592
593 /*
594 * If autoneg_advertised is zero, we assume it was not defaulted
595 * by the calling code so we set to advertise full capability.
596 */
597 if (phy->autoneg_advertised == 0)
598 phy->autoneg_advertised = phy->autoneg_mask;
599
600 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
601 ret_val = igb_phy_setup_autoneg(hw);
602 if (ret_val) {
603 hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
604 goto out;
605 }
606 hw_dbg(hw, "Restarting Auto-Neg\n");
607
608 /*
609 * Restart auto-negotiation by setting the Auto Neg Enable bit and
610 * the Auto Neg Restart bit in the PHY control register.
611 */
612 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
613 if (ret_val)
614 goto out;
615
616 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
617 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
618 if (ret_val)
619 goto out;
620
621 /*
622 * Does the user want to wait for Auto-Neg to complete here, or
623 * check at a later time (for example, callback routine).
624 */
625 if (phy->autoneg_wait_to_complete) {
626 ret_val = igb_wait_autoneg(hw);
627 if (ret_val) {
628 hw_dbg(hw, "Error while waiting for "
629 "autoneg to complete\n");
630 goto out;
631 }
632 }
633
634 hw->mac.get_link_status = true;
635
636out:
637 return ret_val;
638}
639
640/**
641 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
642 * @hw: pointer to the HW structure
643 *
644 * Reads the MII auto-neg advertisement register and/or the 1000T control
645 * register and if the PHY is already setup for auto-negotiation, then
646 * return successful. Otherwise, setup advertisement and flow control to
647 * the appropriate values for the wanted auto-negotiation.
648 **/
649static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
650{
651 struct e1000_phy_info *phy = &hw->phy;
652 s32 ret_val;
653 u16 mii_autoneg_adv_reg;
654 u16 mii_1000t_ctrl_reg = 0;
655
656 phy->autoneg_advertised &= phy->autoneg_mask;
657
658 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
659 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_AUTONEG_ADV,
660 &mii_autoneg_adv_reg);
661 if (ret_val)
662 goto out;
663
664 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
665 /* Read the MII 1000Base-T Control Register (Address 9). */
666 ret_val = hw->phy.ops.read_phy_reg(hw,
667 PHY_1000T_CTRL,
668 &mii_1000t_ctrl_reg);
669 if (ret_val)
670 goto out;
671 }
672
673 /*
674 * Need to parse both autoneg_advertised and fc and set up
675 * the appropriate PHY registers. First we will parse for
676 * autoneg_advertised software override. Since we can advertise
677 * a plethora of combinations, we need to check each bit
678 * individually.
679 */
680
681 /*
682 * First we clear all the 10/100 mb speed bits in the Auto-Neg
683 * Advertisement Register (Address 4) and the 1000 mb speed bits in
684 * the 1000Base-T Control Register (Address 9).
685 */
686 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
687 NWAY_AR_100TX_HD_CAPS |
688 NWAY_AR_10T_FD_CAPS |
689 NWAY_AR_10T_HD_CAPS);
690 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
691
692 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
693
694 /* Do we want to advertise 10 Mb Half Duplex? */
695 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
696 hw_dbg(hw, "Advertise 10mb Half duplex\n");
697 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
698 }
699
700 /* Do we want to advertise 10 Mb Full Duplex? */
701 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
702 hw_dbg(hw, "Advertise 10mb Full duplex\n");
703 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
704 }
705
706 /* Do we want to advertise 100 Mb Half Duplex? */
707 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
708 hw_dbg(hw, "Advertise 100mb Half duplex\n");
709 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
710 }
711
712 /* Do we want to advertise 100 Mb Full Duplex? */
713 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
714 hw_dbg(hw, "Advertise 100mb Full duplex\n");
715 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
716 }
717
718 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
719 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
720 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
721
722 /* Do we want to advertise 1000 Mb Full Duplex? */
723 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
724 hw_dbg(hw, "Advertise 1000mb Full duplex\n");
725 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
726 }
727
728 /*
729 * Check for a software override of the flow control settings, and
730 * setup the PHY advertisement registers accordingly. If
731 * auto-negotiation is enabled, then software will have to set the
732 * "PAUSE" bits to the correct value in the Auto-Negotiation
733 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
734 * negotiation.
735 *
736 * The possible values of the "fc" parameter are:
737 * 0: Flow control is completely disabled
738 * 1: Rx flow control is enabled (we can receive pause frames
739 * but not send pause frames).
740 * 2: Tx flow control is enabled (we can send pause frames
741 * but we do not support receiving pause frames).
742 * 3: Both Rx and TX flow control (symmetric) are enabled.
743 * other: No software override. The flow control configuration
744 * in the EEPROM is used.
745 */
746 switch (hw->fc.type) {
747 case e1000_fc_none:
748 /*
749 * Flow control (RX & TX) is completely disabled by a
750 * software over-ride.
751 */
752 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
753 break;
754 case e1000_fc_rx_pause:
755 /*
756 * RX Flow control is enabled, and TX Flow control is
757 * disabled, by a software over-ride.
758 *
759 * Since there really isn't a way to advertise that we are
760 * capable of RX Pause ONLY, we will advertise that we
761 * support both symmetric and asymmetric RX PAUSE. Later
762 * (in e1000_config_fc_after_link_up) we will disable the
763 * hw's ability to send PAUSE frames.
764 */
765 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
766 break;
767 case e1000_fc_tx_pause:
768 /*
769 * TX Flow control is enabled, and RX Flow control is
770 * disabled, by a software over-ride.
771 */
772 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
773 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
774 break;
775 case e1000_fc_full:
776 /*
777 * Flow control (both RX and TX) is enabled by a software
778 * over-ride.
779 */
780 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
781 break;
782 default:
783 hw_dbg(hw, "Flow control param set incorrectly\n");
784 ret_val = -E1000_ERR_CONFIG;
785 goto out;
786 }
787
788 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_AUTONEG_ADV,
789 mii_autoneg_adv_reg);
790 if (ret_val)
791 goto out;
792
793 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
794
795 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
796 ret_val = hw->phy.ops.write_phy_reg(hw,
797 PHY_1000T_CTRL,
798 mii_1000t_ctrl_reg);
799 if (ret_val)
800 goto out;
801 }
802
803out:
804 return ret_val;
805}
806
807/**
808 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
809 * @hw: pointer to the HW structure
810 *
811 * Calls the PHY setup function to force speed and duplex. Clears the
812 * auto-crossover to force MDI manually. Waits for link and returns
813 * successful if link up is successful, else -E1000_ERR_PHY (-2).
814 **/
815s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
816{
817 struct e1000_phy_info *phy = &hw->phy;
818 s32 ret_val;
819 u16 phy_data;
820 bool link;
821
822 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
823 if (ret_val)
824 goto out;
825
826 igb_phy_force_speed_duplex_setup(hw, &phy_data);
827
828 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
829 if (ret_val)
830 goto out;
831
832 /*
833 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
834 * forced whenever speed and duplex are forced.
835 */
836 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
837 &phy_data);
838 if (ret_val)
839 goto out;
840
841 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
842 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
843
844 ret_val = hw->phy.ops.write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
845 phy_data);
846 if (ret_val)
847 goto out;
848
849 hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
850
851 udelay(1);
852
853 if (phy->autoneg_wait_to_complete) {
854 hw_dbg(hw,
855 "Waiting for forced speed/duplex link on IGP phy.\n");
856
857 ret_val = igb_phy_has_link(hw,
858 PHY_FORCE_LIMIT,
859 100000,
860 &link);
861 if (ret_val)
862 goto out;
863
864 if (!link)
865 hw_dbg(hw, "Link taking longer than expected.\n");
866
867 /* Try once more */
868 ret_val = igb_phy_has_link(hw,
869 PHY_FORCE_LIMIT,
870 100000,
871 &link);
872 if (ret_val)
873 goto out;
874 }
875
876out:
877 return ret_val;
878}
879
880/**
881 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
882 * @hw: pointer to the HW structure
883 *
884 * Calls the PHY setup function to force speed and duplex. Clears the
885 * auto-crossover to force MDI manually. Resets the PHY to commit the
886 * changes. If time expires while waiting for link up, we reset the DSP.
887 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
888 * successful completion, else return corresponding error code.
889 **/
890s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
891{
892 struct e1000_phy_info *phy = &hw->phy;
893 s32 ret_val;
894 u16 phy_data;
895 bool link;
896
897 /*
898 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
899 * forced whenever speed and duplex are forced.
900 */
901 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
902 &phy_data);
903 if (ret_val)
904 goto out;
905
906 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
907 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
908 phy_data);
909 if (ret_val)
910 goto out;
911
912 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
913
914 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_data);
915 if (ret_val)
916 goto out;
917
918 igb_phy_force_speed_duplex_setup(hw, &phy_data);
919
920 /* Reset the phy to commit changes. */
921 phy_data |= MII_CR_RESET;
922
923 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_data);
924 if (ret_val)
925 goto out;
926
927 udelay(1);
928
929 if (phy->autoneg_wait_to_complete) {
930 hw_dbg(hw,
931 "Waiting for forced speed/duplex link on M88 phy.\n");
932
933 ret_val = igb_phy_has_link(hw,
934 PHY_FORCE_LIMIT,
935 100000,
936 &link);
937 if (ret_val)
938 goto out;
939
940 if (!link) {
941 /*
942 * We didn't get link.
943 * Reset the DSP and cross our fingers.
944 */
945 ret_val = hw->phy.ops.write_phy_reg(hw,
946 M88E1000_PHY_PAGE_SELECT,
947 0x001d);
948 if (ret_val)
949 goto out;
950 ret_val = igb_phy_reset_dsp(hw);
951 if (ret_val)
952 goto out;
953 }
954
955 /* Try once more */
956 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
957 100000, &link);
958 if (ret_val)
959 goto out;
960 }
961
962 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
963 &phy_data);
964 if (ret_val)
965 goto out;
966
967 /*
968 * Resetting the phy means we need to re-force TX_CLK in the
969 * Extended PHY Specific Control Register to 25MHz clock from
970 * the reset value of 2.5MHz.
971 */
972 phy_data |= M88E1000_EPSCR_TX_CLK_25;
973 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
974 phy_data);
975 if (ret_val)
976 goto out;
977
978 /*
979 * In addition, we must re-enable CRS on Tx for both half and full
980 * duplex.
981 */
982 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
983 &phy_data);
984 if (ret_val)
985 goto out;
986
987 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
988 ret_val = hw->phy.ops.write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
989 phy_data);
990
991out:
992 return ret_val;
993}
994
995/**
996 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
997 * @hw: pointer to the HW structure
998 * @phy_ctrl: pointer to current value of PHY_CONTROL
999 *
1000 * Forces speed and duplex on the PHY by doing the following: disable flow
1001 * control, force speed/duplex on the MAC, disable auto speed detection,
1002 * disable auto-negotiation, configure duplex, configure speed, configure
1003 * the collision distance, write configuration to CTRL register. The
1004 * caller must write to the PHY_CONTROL register for these settings to
1005 * take affect.
1006 **/
1007static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1008 u16 *phy_ctrl)
1009{
1010 struct e1000_mac_info *mac = &hw->mac;
1011 u32 ctrl;
1012
1013 /* Turn off flow control when forcing speed/duplex */
1014 hw->fc.type = e1000_fc_none;
1015
1016 /* Force speed/duplex on the mac */
1017 ctrl = rd32(E1000_CTRL);
1018 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1019 ctrl &= ~E1000_CTRL_SPD_SEL;
1020
1021 /* Disable Auto Speed Detection */
1022 ctrl &= ~E1000_CTRL_ASDE;
1023
1024 /* Disable autoneg on the phy */
1025 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1026
1027 /* Forcing Full or Half Duplex? */
1028 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1029 ctrl &= ~E1000_CTRL_FD;
1030 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1031 hw_dbg(hw, "Half Duplex\n");
1032 } else {
1033 ctrl |= E1000_CTRL_FD;
1034 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1035 hw_dbg(hw, "Full Duplex\n");
1036 }
1037
1038 /* Forcing 10mb or 100mb? */
1039 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1040 ctrl |= E1000_CTRL_SPD_100;
1041 *phy_ctrl |= MII_CR_SPEED_100;
1042 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1043 hw_dbg(hw, "Forcing 100mb\n");
1044 } else {
1045 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1046 *phy_ctrl |= MII_CR_SPEED_10;
1047 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1048 hw_dbg(hw, "Forcing 10mb\n");
1049 }
1050
1051 igb_config_collision_dist(hw);
1052
1053 wr32(E1000_CTRL, ctrl);
1054}
1055
1056/**
1057 * e1000_set_d3_lplu_state - Sets low power link up state for D3
1058 * @hw: pointer to the HW structure
1059 * @active: boolean used to enable/disable lplu
1060 *
1061 * Success returns 0, Failure returns 1
1062 *
1063 * The low power link up (lplu) state is set to the power management level D3
1064 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1065 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1066 * is used during Dx states where the power conservation is most important.
1067 * During driver activity, SmartSpeed should be enabled so performance is
1068 * maintained.
1069 **/
1070s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1071{
1072 struct e1000_phy_info *phy = &hw->phy;
1073 s32 ret_val;
1074 u16 data;
1075
1076 ret_val = hw->phy.ops.read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1077 &data);
1078 if (ret_val)
1079 goto out;
1080
1081 if (!active) {
1082 data &= ~IGP02E1000_PM_D3_LPLU;
1083 ret_val = hw->phy.ops.write_phy_reg(hw,
1084 IGP02E1000_PHY_POWER_MGMT,
1085 data);
1086 if (ret_val)
1087 goto out;
1088 /*
1089 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1090 * during Dx states where the power conservation is most
1091 * important. During driver activity we should enable
1092 * SmartSpeed, so performance is maintained.
1093 */
1094 if (phy->smart_speed == e1000_smart_speed_on) {
1095 ret_val = hw->phy.ops.read_phy_reg(hw,
1096 IGP01E1000_PHY_PORT_CONFIG,
1097 &data);
1098 if (ret_val)
1099 goto out;
1100
1101 data |= IGP01E1000_PSCFR_SMART_SPEED;
1102 ret_val = hw->phy.ops.write_phy_reg(hw,
1103 IGP01E1000_PHY_PORT_CONFIG,
1104 data);
1105 if (ret_val)
1106 goto out;
1107 } else if (phy->smart_speed == e1000_smart_speed_off) {
1108 ret_val = hw->phy.ops.read_phy_reg(hw,
1109 IGP01E1000_PHY_PORT_CONFIG,
1110 &data);
1111 if (ret_val)
1112 goto out;
1113
1114 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1115 ret_val = hw->phy.ops.write_phy_reg(hw,
1116 IGP01E1000_PHY_PORT_CONFIG,
1117 data);
1118 if (ret_val)
1119 goto out;
1120 }
1121 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1122 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1123 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1124 data |= IGP02E1000_PM_D3_LPLU;
1125 ret_val = hw->phy.ops.write_phy_reg(hw,
1126 IGP02E1000_PHY_POWER_MGMT,
1127 data);
1128 if (ret_val)
1129 goto out;
1130
1131 /* When LPLU is enabled, we should disable SmartSpeed */
1132 ret_val = hw->phy.ops.read_phy_reg(hw,
1133 IGP01E1000_PHY_PORT_CONFIG,
1134 &data);
1135 if (ret_val)
1136 goto out;
1137
1138 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1139 ret_val = hw->phy.ops.write_phy_reg(hw,
1140 IGP01E1000_PHY_PORT_CONFIG,
1141 data);
1142 }
1143
1144out:
1145 return ret_val;
1146}
1147
1148/**
1149 * e1000_check_downshift - Checks whether a downshift in speed occured
1150 * @hw: pointer to the HW structure
1151 *
1152 * Success returns 0, Failure returns 1
1153 *
1154 * A downshift is detected by querying the PHY link health.
1155 **/
1156s32 igb_check_downshift(struct e1000_hw *hw)
1157{
1158 struct e1000_phy_info *phy = &hw->phy;
1159 s32 ret_val;
1160 u16 phy_data, offset, mask;
1161
1162 switch (phy->type) {
1163 case e1000_phy_m88:
1164 case e1000_phy_gg82563:
1165 offset = M88E1000_PHY_SPEC_STATUS;
1166 mask = M88E1000_PSSR_DOWNSHIFT;
1167 break;
1168 case e1000_phy_igp_2:
1169 case e1000_phy_igp:
1170 case e1000_phy_igp_3:
1171 offset = IGP01E1000_PHY_LINK_HEALTH;
1172 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1173 break;
1174 default:
1175 /* speed downshift not supported */
1176 phy->speed_downgraded = false;
1177 ret_val = 0;
1178 goto out;
1179 }
1180
1181 ret_val = hw->phy.ops.read_phy_reg(hw, offset, &phy_data);
1182
1183 if (!ret_val)
1184 phy->speed_downgraded = (phy_data & mask) ? true : false;
1185
1186out:
1187 return ret_val;
1188}
1189
1190/**
1191 * e1000_check_polarity_m88 - Checks the polarity.
1192 * @hw: pointer to the HW structure
1193 *
1194 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1195 *
1196 * Polarity is determined based on the PHY specific status register.
1197 **/
1198static s32 igb_check_polarity_m88(struct e1000_hw *hw)
1199{
1200 struct e1000_phy_info *phy = &hw->phy;
1201 s32 ret_val;
1202 u16 data;
1203
1204 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1205
1206 if (!ret_val)
1207 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1208 ? e1000_rev_polarity_reversed
1209 : e1000_rev_polarity_normal;
1210
1211 return ret_val;
1212}
1213
1214/**
1215 * e1000_check_polarity_igp - Checks the polarity.
1216 * @hw: pointer to the HW structure
1217 *
1218 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1219 *
1220 * Polarity is determined based on the PHY port status register, and the
1221 * current speed (since there is no polarity at 100Mbps).
1222 **/
1223static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1224{
1225 struct e1000_phy_info *phy = &hw->phy;
1226 s32 ret_val;
1227 u16 data, offset, mask;
1228
1229 /*
1230 * Polarity is determined based on the speed of
1231 * our connection.
1232 */
1233 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1234 &data);
1235 if (ret_val)
1236 goto out;
1237
1238 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1239 IGP01E1000_PSSR_SPEED_1000MBPS) {
1240 offset = IGP01E1000_PHY_PCS_INIT_REG;
1241 mask = IGP01E1000_PHY_POLARITY_MASK;
1242 } else {
1243 /*
1244 * This really only applies to 10Mbps since
1245 * there is no polarity for 100Mbps (always 0).
1246 */
1247 offset = IGP01E1000_PHY_PORT_STATUS;
1248 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1249 }
1250
1251 ret_val = hw->phy.ops.read_phy_reg(hw, offset, &data);
1252
1253 if (!ret_val)
1254 phy->cable_polarity = (data & mask)
1255 ? e1000_rev_polarity_reversed
1256 : e1000_rev_polarity_normal;
1257
1258out:
1259 return ret_val;
1260}
1261
1262/**
1263 * e1000_wait_autoneg - Wait for auto-neg compeletion
1264 * @hw: pointer to the HW structure
1265 *
1266 * Waits for auto-negotiation to complete or for the auto-negotiation time
1267 * limit to expire, which ever happens first.
1268 **/
1269static s32 igb_wait_autoneg(struct e1000_hw *hw)
1270{
1271 s32 ret_val = 0;
1272 u16 i, phy_status;
1273
1274 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1275 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1276 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1277 if (ret_val)
1278 break;
1279 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1280 if (ret_val)
1281 break;
1282 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1283 break;
1284 msleep(100);
1285 }
1286
1287 /*
1288 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1289 * has completed.
1290 */
1291 return ret_val;
1292}
1293
1294/**
1295 * e1000_phy_has_link - Polls PHY for link
1296 * @hw: pointer to the HW structure
1297 * @iterations: number of times to poll for link
1298 * @usec_interval: delay between polling attempts
1299 * @success: pointer to whether polling was successful or not
1300 *
1301 * Polls the PHY status register for link, 'iterations' number of times.
1302 **/
1303s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1304 u32 usec_interval, bool *success)
1305{
1306 s32 ret_val = 0;
1307 u16 i, phy_status;
1308
1309 for (i = 0; i < iterations; i++) {
1310 /*
1311 * Some PHYs require the PHY_STATUS register to be read
1312 * twice due to the link bit being sticky. No harm doing
1313 * it across the board.
1314 */
1315 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1316 if (ret_val)
1317 break;
1318 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_STATUS, &phy_status);
1319 if (ret_val)
1320 break;
1321 if (phy_status & MII_SR_LINK_STATUS)
1322 break;
1323 if (usec_interval >= 1000)
1324 mdelay(usec_interval/1000);
1325 else
1326 udelay(usec_interval);
1327 }
1328
1329 *success = (i < iterations) ? true : false;
1330
1331 return ret_val;
1332}
1333
1334/**
1335 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
1336 * @hw: pointer to the HW structure
1337 *
1338 * Reads the PHY specific status register to retrieve the cable length
1339 * information. The cable length is determined by averaging the minimum and
1340 * maximum values to get the "average" cable length. The m88 PHY has four
1341 * possible cable length values, which are:
1342 * Register Value Cable Length
1343 * 0 < 50 meters
1344 * 1 50 - 80 meters
1345 * 2 80 - 110 meters
1346 * 3 110 - 140 meters
1347 * 4 > 140 meters
1348 **/
1349s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1350{
1351 struct e1000_phy_info *phy = &hw->phy;
1352 s32 ret_val;
1353 u16 phy_data, index;
1354
1355 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1356 &phy_data);
1357 if (ret_val)
1358 goto out;
1359
1360 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1361 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1362 phy->min_cable_length = e1000_m88_cable_length_table[index];
1363 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1364
1365 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1366
1367out:
1368 return ret_val;
1369}
1370
1371/**
1372 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1373 * @hw: pointer to the HW structure
1374 *
1375 * The automatic gain control (agc) normalizes the amplitude of the
1376 * received signal, adjusting for the attenuation produced by the
1377 * cable. By reading the AGC registers, which reperesent the
1378 * cobination of course and fine gain value, the value can be put
1379 * into a lookup table to obtain the approximate cable length
1380 * for each channel.
1381 **/
1382s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1383{
1384 struct e1000_phy_info *phy = &hw->phy;
1385 s32 ret_val = 0;
1386 u16 phy_data, i, agc_value = 0;
1387 u16 cur_agc_index, max_agc_index = 0;
1388 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1389 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1390 {IGP02E1000_PHY_AGC_A,
1391 IGP02E1000_PHY_AGC_B,
1392 IGP02E1000_PHY_AGC_C,
1393 IGP02E1000_PHY_AGC_D};
1394
1395 /* Read the AGC registers for all channels */
1396 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1397 ret_val = hw->phy.ops.read_phy_reg(hw, agc_reg_array[i],
1398 &phy_data);
1399 if (ret_val)
1400 goto out;
1401
1402 /*
1403 * Getting bits 15:9, which represent the combination of
1404 * course and fine gain values. The result is a number
1405 * that can be put into the lookup table to obtain the
1406 * approximate cable length.
1407 */
1408 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1409 IGP02E1000_AGC_LENGTH_MASK;
1410
1411 /* Array index bound check. */
1412 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1413 (cur_agc_index == 0)) {
1414 ret_val = -E1000_ERR_PHY;
1415 goto out;
1416 }
1417
1418 /* Remove min & max AGC values from calculation. */
1419 if (e1000_igp_2_cable_length_table[min_agc_index] >
1420 e1000_igp_2_cable_length_table[cur_agc_index])
1421 min_agc_index = cur_agc_index;
1422 if (e1000_igp_2_cable_length_table[max_agc_index] <
1423 e1000_igp_2_cable_length_table[cur_agc_index])
1424 max_agc_index = cur_agc_index;
1425
1426 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1427 }
1428
1429 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1430 e1000_igp_2_cable_length_table[max_agc_index]);
1431 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1432
1433 /* Calculate cable length with the error range of +/- 10 meters. */
1434 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1435 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1436 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1437
1438 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1439
1440out:
1441 return ret_val;
1442}
1443
1444/**
1445 * e1000_get_phy_info_m88 - Retrieve PHY information
1446 * @hw: pointer to the HW structure
1447 *
1448 * Valid for only copper links. Read the PHY status register (sticky read)
1449 * to verify that link is up. Read the PHY special control register to
1450 * determine the polarity and 10base-T extended distance. Read the PHY
1451 * special status register to determine MDI/MDIx and current speed. If
1452 * speed is 1000, then determine cable length, local and remote receiver.
1453 **/
1454s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1455{
1456 struct e1000_phy_info *phy = &hw->phy;
1457 s32 ret_val;
1458 u16 phy_data;
1459 bool link;
1460
1461 if (hw->phy.media_type != e1000_media_type_copper) {
1462 hw_dbg(hw, "Phy info is only valid for copper media\n");
1463 ret_val = -E1000_ERR_CONFIG;
1464 goto out;
1465 }
1466
1467 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1468 if (ret_val)
1469 goto out;
1470
1471 if (!link) {
1472 hw_dbg(hw, "Phy info is only valid if link is up\n");
1473 ret_val = -E1000_ERR_CONFIG;
1474 goto out;
1475 }
1476
1477 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1478 &phy_data);
1479 if (ret_val)
1480 goto out;
1481
1482 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1483 ? true
1484 : false;
1485
1486 ret_val = igb_check_polarity_m88(hw);
1487 if (ret_val)
1488 goto out;
1489
1490 ret_val = hw->phy.ops.read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1491 &phy_data);
1492 if (ret_val)
1493 goto out;
1494
1495 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1496
1497 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1498 ret_val = hw->phy.ops.get_cable_length(hw);
1499 if (ret_val)
1500 goto out;
1501
1502 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
1503 &phy_data);
1504 if (ret_val)
1505 goto out;
1506
1507 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1508 ? e1000_1000t_rx_status_ok
1509 : e1000_1000t_rx_status_not_ok;
1510
1511 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1512 ? e1000_1000t_rx_status_ok
1513 : e1000_1000t_rx_status_not_ok;
1514 } else {
1515 /* Set values to "undefined" */
1516 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1517 phy->local_rx = e1000_1000t_rx_status_undefined;
1518 phy->remote_rx = e1000_1000t_rx_status_undefined;
1519 }
1520
1521out:
1522 return ret_val;
1523}
1524
1525/**
1526 * e1000_get_phy_info_igp - Retrieve igp PHY information
1527 * @hw: pointer to the HW structure
1528 *
1529 * Read PHY status to determine if link is up. If link is up, then
1530 * set/determine 10base-T extended distance and polarity correction. Read
1531 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1532 * determine on the cable length, local and remote receiver.
1533 **/
1534s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1535{
1536 struct e1000_phy_info *phy = &hw->phy;
1537 s32 ret_val;
1538 u16 data;
1539 bool link;
1540
1541 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1542 if (ret_val)
1543 goto out;
1544
1545 if (!link) {
1546 hw_dbg(hw, "Phy info is only valid if link is up\n");
1547 ret_val = -E1000_ERR_CONFIG;
1548 goto out;
1549 }
1550
1551 phy->polarity_correction = true;
1552
1553 ret_val = igb_check_polarity_igp(hw);
1554 if (ret_val)
1555 goto out;
1556
1557 ret_val = hw->phy.ops.read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1558 &data);
1559 if (ret_val)
1560 goto out;
1561
1562 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
1563
1564 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1565 IGP01E1000_PSSR_SPEED_1000MBPS) {
1566 ret_val = hw->phy.ops.get_cable_length(hw);
1567 if (ret_val)
1568 goto out;
1569
1570 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
1571 &data);
1572 if (ret_val)
1573 goto out;
1574
1575 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1576 ? e1000_1000t_rx_status_ok
1577 : e1000_1000t_rx_status_not_ok;
1578
1579 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1580 ? e1000_1000t_rx_status_ok
1581 : e1000_1000t_rx_status_not_ok;
1582 } else {
1583 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1584 phy->local_rx = e1000_1000t_rx_status_undefined;
1585 phy->remote_rx = e1000_1000t_rx_status_undefined;
1586 }
1587
1588out:
1589 return ret_val;
1590}
1591
1592/**
1593 * e1000_phy_sw_reset - PHY software reset
1594 * @hw: pointer to the HW structure
1595 *
1596 * Does a software reset of the PHY by reading the PHY control register and
1597 * setting/write the control register reset bit to the PHY.
1598 **/
1599s32 igb_phy_sw_reset(struct e1000_hw *hw)
1600{
1601 s32 ret_val;
1602 u16 phy_ctrl;
1603
1604 ret_val = hw->phy.ops.read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
1605 if (ret_val)
1606 goto out;
1607
1608 phy_ctrl |= MII_CR_RESET;
1609 ret_val = hw->phy.ops.write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
1610 if (ret_val)
1611 goto out;
1612
1613 udelay(1);
1614
1615out:
1616 return ret_val;
1617}
1618
1619/**
1620 * e1000_phy_hw_reset - PHY hardware reset
1621 * @hw: pointer to the HW structure
1622 *
1623 * Verify the reset block is not blocking us from resetting. Acquire
1624 * semaphore (if necessary) and read/set/write the device control reset
1625 * bit in the PHY. Wait the appropriate delay time for the device to
1626 * reset and relase the semaphore (if necessary).
1627 **/
1628s32 igb_phy_hw_reset(struct e1000_hw *hw)
1629{
1630 struct e1000_phy_info *phy = &hw->phy;
1631 s32 ret_val;
1632 u32 ctrl;
1633
1634 ret_val = igb_check_reset_block(hw);
1635 if (ret_val) {
1636 ret_val = 0;
1637 goto out;
1638 }
1639
1640 ret_val = igb_acquire_phy(hw);
1641 if (ret_val)
1642 goto out;
1643
1644 ctrl = rd32(E1000_CTRL);
1645 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
1646 wrfl();
1647
1648 udelay(phy->reset_delay_us);
1649
1650 wr32(E1000_CTRL, ctrl);
1651 wrfl();
1652
1653 udelay(150);
1654
1655 igb_release_phy(hw);
1656
1657 ret_val = igb_get_phy_cfg_done(hw);
1658
1659out:
1660 return ret_val;
1661}
1662
1663/* Internal function pointers */
1664
1665/**
1666 * e1000_get_phy_cfg_done - Generic PHY configuration done
1667 * @hw: pointer to the HW structure
1668 *
1669 * Return success if silicon family did not implement a family specific
1670 * get_cfg_done function.
1671 **/
1672static s32 igb_get_phy_cfg_done(struct e1000_hw *hw)
1673{
1674 if (hw->phy.ops.get_cfg_done)
1675 return hw->phy.ops.get_cfg_done(hw);
1676
1677 return 0;
1678}
1679
1680/**
1681 * e1000_release_phy - Generic release PHY
1682 * @hw: pointer to the HW structure
1683 *
1684 * Return if silicon family does not require a semaphore when accessing the
1685 * PHY.
1686 **/
1687static void igb_release_phy(struct e1000_hw *hw)
1688{
1689 if (hw->phy.ops.release_phy)
1690 hw->phy.ops.release_phy(hw);
1691}
1692
1693/**
1694 * e1000_acquire_phy - Generic acquire PHY
1695 * @hw: pointer to the HW structure
1696 *
1697 * Return success if silicon family does not require a semaphore when
1698 * accessing the PHY.
1699 **/
1700static s32 igb_acquire_phy(struct e1000_hw *hw)
1701{
1702 if (hw->phy.ops.acquire_phy)
1703 return hw->phy.ops.acquire_phy(hw);
1704
1705 return 0;
1706}
1707
1708/**
1709 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1710 * @hw: pointer to the HW structure
1711 *
1712 * When the silicon family has not implemented a forced speed/duplex
1713 * function for the PHY, simply return 0.
1714 **/
1715s32 igb_phy_force_speed_duplex(struct e1000_hw *hw)
1716{
1717 if (hw->phy.ops.force_speed_duplex)
1718 return hw->phy.ops.force_speed_duplex(hw);
1719
1720 return 0;
1721}
1722
1723/**
1724 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
1725 * @hw: pointer to the HW structure
1726 *
1727 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1728 **/
1729s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
1730{
1731 hw_dbg(hw, "Running IGP 3 PHY init script\n");
1732
1733 /* PHY init IGP 3 */
1734 /* Enable rise/fall, 10-mode work in class-A */
1735 hw->phy.ops.write_phy_reg(hw, 0x2F5B, 0x9018);
1736 /* Remove all caps from Replica path filter */
1737 hw->phy.ops.write_phy_reg(hw, 0x2F52, 0x0000);
1738 /* Bias trimming for ADC, AFE and Driver (Default) */
1739 hw->phy.ops.write_phy_reg(hw, 0x2FB1, 0x8B24);
1740 /* Increase Hybrid poly bias */
1741 hw->phy.ops.write_phy_reg(hw, 0x2FB2, 0xF8F0);
1742 /* Add 4% to TX amplitude in Giga mode */
1743 hw->phy.ops.write_phy_reg(hw, 0x2010, 0x10B0);
1744 /* Disable trimming (TTT) */
1745 hw->phy.ops.write_phy_reg(hw, 0x2011, 0x0000);
1746 /* Poly DC correction to 94.6% + 2% for all channels */
1747 hw->phy.ops.write_phy_reg(hw, 0x20DD, 0x249A);
1748 /* ABS DC correction to 95.9% */
1749 hw->phy.ops.write_phy_reg(hw, 0x20DE, 0x00D3);
1750 /* BG temp curve trim */
1751 hw->phy.ops.write_phy_reg(hw, 0x28B4, 0x04CE);
1752 /* Increasing ADC OPAMP stage 1 currents to max */
1753 hw->phy.ops.write_phy_reg(hw, 0x2F70, 0x29E4);
1754 /* Force 1000 ( required for enabling PHY regs configuration) */
1755 hw->phy.ops.write_phy_reg(hw, 0x0000, 0x0140);
1756 /* Set upd_freq to 6 */
1757 hw->phy.ops.write_phy_reg(hw, 0x1F30, 0x1606);
1758 /* Disable NPDFE */
1759 hw->phy.ops.write_phy_reg(hw, 0x1F31, 0xB814);
1760 /* Disable adaptive fixed FFE (Default) */
1761 hw->phy.ops.write_phy_reg(hw, 0x1F35, 0x002A);
1762 /* Enable FFE hysteresis */
1763 hw->phy.ops.write_phy_reg(hw, 0x1F3E, 0x0067);
1764 /* Fixed FFE for short cable lengths */
1765 hw->phy.ops.write_phy_reg(hw, 0x1F54, 0x0065);
1766 /* Fixed FFE for medium cable lengths */
1767 hw->phy.ops.write_phy_reg(hw, 0x1F55, 0x002A);
1768 /* Fixed FFE for long cable lengths */
1769 hw->phy.ops.write_phy_reg(hw, 0x1F56, 0x002A);
1770 /* Enable Adaptive Clip Threshold */
1771 hw->phy.ops.write_phy_reg(hw, 0x1F72, 0x3FB0);
1772 /* AHT reset limit to 1 */
1773 hw->phy.ops.write_phy_reg(hw, 0x1F76, 0xC0FF);
1774 /* Set AHT master delay to 127 msec */
1775 hw->phy.ops.write_phy_reg(hw, 0x1F77, 0x1DEC);
1776 /* Set scan bits for AHT */
1777 hw->phy.ops.write_phy_reg(hw, 0x1F78, 0xF9EF);
1778 /* Set AHT Preset bits */
1779 hw->phy.ops.write_phy_reg(hw, 0x1F79, 0x0210);
1780 /* Change integ_factor of channel A to 3 */
1781 hw->phy.ops.write_phy_reg(hw, 0x1895, 0x0003);
1782 /* Change prop_factor of channels BCD to 8 */
1783 hw->phy.ops.write_phy_reg(hw, 0x1796, 0x0008);
1784 /* Change cg_icount + enable integbp for channels BCD */
1785 hw->phy.ops.write_phy_reg(hw, 0x1798, 0xD008);
1786 /*
1787 * Change cg_icount + enable integbp + change prop_factor_master
1788 * to 8 for channel A
1789 */
1790 hw->phy.ops.write_phy_reg(hw, 0x1898, 0xD918);
1791 /* Disable AHT in Slave mode on channel A */
1792 hw->phy.ops.write_phy_reg(hw, 0x187A, 0x0800);
1793 /*
1794 * Enable LPLU and disable AN to 1000 in non-D0a states,
1795 * Enable SPD+B2B
1796 */
1797 hw->phy.ops.write_phy_reg(hw, 0x0019, 0x008D);
1798 /* Enable restart AN on an1000_dis change */
1799 hw->phy.ops.write_phy_reg(hw, 0x001B, 0x2080);
1800 /* Enable wh_fifo read clock in 10/100 modes */
1801 hw->phy.ops.write_phy_reg(hw, 0x0014, 0x0045);
1802 /* Restart AN, Speed selection is 1000 */
1803 hw->phy.ops.write_phy_reg(hw, 0x0000, 0x1340);
1804
1805 return 0;
1806}
1807
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 15:10:23 -0500