diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-20 20:43:29 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-20 20:43:29 -0400 |
commit | db6d8c7a4027b48d797b369a53f8470aaeed7063 (patch) | |
tree | e140c104a89abc2154e1f41a7db8ebecbb6fa0b4 /drivers/net/igb/e1000_defines.h | |
parent | 3a533374283aea50eab3976d8a6d30532175f009 (diff) | |
parent | fb65a7c091529bfffb1262515252c0d0f6241c5c (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (1232 commits)
iucv: Fix bad merging.
net_sched: Add size table for qdiscs
net_sched: Add accessor function for packet length for qdiscs
net_sched: Add qdisc_enqueue wrapper
highmem: Export totalhigh_pages.
ipv6 mcast: Omit redundant address family checks in ip6_mc_source().
net: Use standard structures for generic socket address structures.
ipv6 netns: Make several "global" sysctl variables namespace aware.
netns: Use net_eq() to compare net-namespaces for optimization.
ipv6: remove unused macros from net/ipv6.h
ipv6: remove unused parameter from ip6_ra_control
tcp: fix kernel panic with listening_get_next
tcp: Remove redundant checks when setting eff_sacks
tcp: options clean up
tcp: Fix MD5 signatures for non-linear skbs
sctp: Update sctp global memory limit allocations.
sctp: remove unnecessary byteshifting, calculate directly in big-endian
sctp: Allow only 1 listening socket with SO_REUSEADDR
sctp: Do not leak memory on multiple listen() calls
sctp: Support ipv6only AF_INET6 sockets.
...
Diffstat (limited to 'drivers/net/igb/e1000_defines.h')
-rw-r--r-- | drivers/net/igb/e1000_defines.h | 38 |
1 files changed, 18 insertions, 20 deletions
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h index 8da9ffedc425..afdba3c9073c 100644 --- a/drivers/net/igb/e1000_defines.h +++ b/drivers/net/igb/e1000_defines.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | 3 | Intel(R) Gigabit Ethernet Linux driver |
4 | Copyright(c) 2007 Intel Corporation. | 4 | Copyright(c) 2007 - 2008 Intel Corporation. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms and conditions of the GNU General Public License, | 7 | under the terms and conditions of the GNU General Public License, |
@@ -90,13 +90,18 @@ | |||
90 | #define E1000_I2CCMD_ERROR 0x80000000 | 90 | #define E1000_I2CCMD_ERROR 0x80000000 |
91 | #define E1000_MAX_SGMII_PHY_REG_ADDR 255 | 91 | #define E1000_MAX_SGMII_PHY_REG_ADDR 255 |
92 | #define E1000_I2CCMD_PHY_TIMEOUT 200 | 92 | #define E1000_I2CCMD_PHY_TIMEOUT 200 |
93 | #define E1000_IVAR_VALID 0x80 | ||
94 | #define E1000_GPIE_NSICR 0x00000001 | ||
95 | #define E1000_GPIE_MSIX_MODE 0x00000010 | ||
96 | #define E1000_GPIE_EIAME 0x40000000 | ||
97 | #define E1000_GPIE_PBA 0x80000000 | ||
93 | 98 | ||
94 | /* Receive Decriptor bit definitions */ | 99 | /* Receive Descriptor bit definitions */ |
95 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | 100 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
96 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | 101 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ |
97 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | 102 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ |
98 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | 103 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
99 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ | 104 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
100 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | 105 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
101 | #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ | 106 | #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ |
102 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | 107 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ |
@@ -213,6 +218,7 @@ | |||
213 | /* Device Control */ | 218 | /* Device Control */ |
214 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | 219 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ |
215 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ | 220 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ |
221 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ | ||
216 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ | 222 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ |
217 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ | 223 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ |
218 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ | 224 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ |
@@ -244,6 +250,7 @@ | |||
244 | */ | 250 | */ |
245 | 251 | ||
246 | #define E1000_CONNSW_ENRGSRC 0x4 | 252 | #define E1000_CONNSW_ENRGSRC 0x4 |
253 | #define E1000_PCS_CFG_PCS_EN 8 | ||
247 | #define E1000_PCS_LCTL_FLV_LINK_UP 1 | 254 | #define E1000_PCS_LCTL_FLV_LINK_UP 1 |
248 | #define E1000_PCS_LCTL_FSV_100 2 | 255 | #define E1000_PCS_LCTL_FSV_100 2 |
249 | #define E1000_PCS_LCTL_FSV_1000 4 | 256 | #define E1000_PCS_LCTL_FSV_1000 4 |
@@ -253,6 +260,7 @@ | |||
253 | #define E1000_PCS_LCTL_AN_ENABLE 0x10000 | 260 | #define E1000_PCS_LCTL_AN_ENABLE 0x10000 |
254 | #define E1000_PCS_LCTL_AN_RESTART 0x20000 | 261 | #define E1000_PCS_LCTL_AN_RESTART 0x20000 |
255 | #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 | 262 | #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 |
263 | #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 | ||
256 | 264 | ||
257 | #define E1000_PCS_LSTS_LINK_OK 1 | 265 | #define E1000_PCS_LSTS_LINK_OK 1 |
258 | #define E1000_PCS_LSTS_SPEED_100 2 | 266 | #define E1000_PCS_LSTS_SPEED_100 2 |
@@ -340,6 +348,7 @@ | |||
340 | #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ | 348 | #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ |
341 | 349 | ||
342 | /* Header split receive */ | 350 | /* Header split receive */ |
351 | #define E1000_RFCTL_LEF 0x00040000 | ||
343 | 352 | ||
344 | /* Collision related configuration parameters */ | 353 | /* Collision related configuration parameters */ |
345 | #define E1000_COLLISION_THRESHOLD 15 | 354 | #define E1000_COLLISION_THRESHOLD 15 |
@@ -359,6 +368,7 @@ | |||
359 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ | 368 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ |
360 | #define E1000_PBA_24K 0x0018 | 369 | #define E1000_PBA_24K 0x0018 |
361 | #define E1000_PBA_34K 0x0022 | 370 | #define E1000_PBA_34K 0x0022 |
371 | #define E1000_PBA_64K 0x0040 /* 64KB */ | ||
362 | 372 | ||
363 | #define IFS_MAX 80 | 373 | #define IFS_MAX 80 |
364 | #define IFS_MIN 40 | 374 | #define IFS_MIN 40 |
@@ -379,7 +389,7 @@ | |||
379 | #define E1000_ICR_RXO 0x00000040 /* rx overrun */ | 389 | #define E1000_ICR_RXO 0x00000040 /* rx overrun */ |
380 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ | 390 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ |
381 | #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ | 391 | #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ |
382 | #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ | 392 | #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ |
383 | #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ | 393 | #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ |
384 | #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ | 394 | #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ |
385 | #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ | 395 | #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ |
@@ -443,12 +453,6 @@ | |||
443 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | 453 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
444 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | 454 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
445 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | 455 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ |
446 | /* queue 0 Rx descriptor FIFO parity error */ | ||
447 | /* queue 0 Tx descriptor FIFO parity error */ | ||
448 | /* host arb read buffer parity error */ | ||
449 | /* packet buffer parity error */ | ||
450 | /* queue 1 Rx descriptor FIFO parity error */ | ||
451 | /* queue 1 Tx descriptor FIFO parity error */ | ||
452 | 456 | ||
453 | /* Extended Interrupt Mask Set */ | 457 | /* Extended Interrupt Mask Set */ |
454 | #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ | 458 | #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ |
@@ -457,12 +461,6 @@ | |||
457 | /* Interrupt Cause Set */ | 461 | /* Interrupt Cause Set */ |
458 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | 462 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ |
459 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | 463 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
460 | /* queue 0 Rx descriptor FIFO parity error */ | ||
461 | /* queue 0 Tx descriptor FIFO parity error */ | ||
462 | /* host arb read buffer parity error */ | ||
463 | /* packet buffer parity error */ | ||
464 | /* queue 1 Rx descriptor FIFO parity error */ | ||
465 | /* queue 1 Tx descriptor FIFO parity error */ | ||
466 | 464 | ||
467 | /* Extended Interrupt Cause Set */ | 465 | /* Extended Interrupt Cause Set */ |
468 | 466 | ||
@@ -539,6 +537,7 @@ | |||
539 | /* PHY Control Register */ | 537 | /* PHY Control Register */ |
540 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | 538 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ |
541 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | 539 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ |
540 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ | ||
542 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ | 541 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
543 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | 542 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ |
544 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | 543 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ |
@@ -567,7 +566,6 @@ | |||
567 | /* 1000BASE-T Control Register */ | 566 | /* 1000BASE-T Control Register */ |
568 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | 567 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ |
569 | #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ | 568 | #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ |
570 | /* 0=DTE device */ | ||
571 | #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ | 569 | #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ |
572 | /* 0=Configure PHY as Slave */ | 570 | /* 0=Configure PHY as Slave */ |
573 | #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ | 571 | #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ |
@@ -581,7 +579,7 @@ | |||
581 | /* PHY 1000 MII Register/Bit Definitions */ | 579 | /* PHY 1000 MII Register/Bit Definitions */ |
582 | /* PHY Registers defined by IEEE */ | 580 | /* PHY Registers defined by IEEE */ |
583 | #define PHY_CONTROL 0x00 /* Control Register */ | 581 | #define PHY_CONTROL 0x00 /* Control Register */ |
584 | #define PHY_STATUS 0x01 /* Status Regiser */ | 582 | #define PHY_STATUS 0x01 /* Status Register */ |
585 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ | 583 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ |
586 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ | 584 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ |
587 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ | 585 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ |
@@ -708,8 +706,8 @@ | |||
708 | /* Auto crossover enabled all speeds */ | 706 | /* Auto crossover enabled all speeds */ |
709 | #define M88E1000_PSCR_AUTO_X_MODE 0x0060 | 707 | #define M88E1000_PSCR_AUTO_X_MODE 0x0060 |
710 | /* | 708 | /* |
711 | * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold | 709 | * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold |
712 | * 0=Normal 10BASE-T RX Threshold | 710 | * 0=Normal 10BASE-T Rx Threshold |
713 | */ | 711 | */ |
714 | /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ | 712 | /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ |
715 | #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ | 713 | #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ |