diff options
author | Alexander Duyck <alexander.h.duyck@intel.com> | 2009-02-06 18:19:08 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-07 05:43:08 -0500 |
commit | dda0e0834c839c0e4b1717cbe9c22c35ca935809 (patch) | |
tree | 55be9a788e8b9815fe4fb40871cda0883c596431 /drivers/net/igb/e1000_defines.h | |
parent | 2753f4cebf034a53f87b24679f394854275dcacb (diff) |
igb: add counter for dma out of sync errors
Add a counter for dma out of sync errors reported via interrupt.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_defines.h')
-rw-r--r-- | drivers/net/igb/e1000_defines.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h index 54a148923386..bff62dd84312 100644 --- a/drivers/net/igb/e1000_defines.h +++ b/drivers/net/igb/e1000_defines.h | |||
@@ -413,6 +413,7 @@ | |||
413 | /* LAN connected device generates an interrupt */ | 413 | /* LAN connected device generates an interrupt */ |
414 | #define E1000_ICR_PHYINT 0x00001000 | 414 | #define E1000_ICR_PHYINT 0x00001000 |
415 | #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ | 415 | #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ |
416 | #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ | ||
416 | 417 | ||
417 | /* Extended Interrupt Cause Read */ | 418 | /* Extended Interrupt Cause Read */ |
418 | #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ | 419 | #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ |
@@ -441,7 +442,8 @@ | |||
441 | E1000_IMS_TXDW | \ | 442 | E1000_IMS_TXDW | \ |
442 | E1000_IMS_RXDMT0 | \ | 443 | E1000_IMS_RXDMT0 | \ |
443 | E1000_IMS_RXSEQ | \ | 444 | E1000_IMS_RXSEQ | \ |
444 | E1000_IMS_LSC) | 445 | E1000_IMS_LSC | \ |
446 | E1000_IMS_DOUTSYNC) | ||
445 | 447 | ||
446 | /* Interrupt Mask Set */ | 448 | /* Interrupt Mask Set */ |
447 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | 449 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
@@ -449,6 +451,7 @@ | |||
449 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ | 451 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
450 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | 452 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
451 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | 453 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ |
454 | #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ | ||
452 | 455 | ||
453 | /* Extended Interrupt Mask Set */ | 456 | /* Extended Interrupt Mask Set */ |
454 | #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ | 457 | #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ |
@@ -457,6 +460,7 @@ | |||
457 | /* Interrupt Cause Set */ | 460 | /* Interrupt Cause Set */ |
458 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | 461 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ |
459 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | 462 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ |
463 | #define E1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ | ||
460 | 464 | ||
461 | /* Extended Interrupt Cause Set */ | 465 | /* Extended Interrupt Cause Set */ |
462 | 466 | ||