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authorAlexander Duyck <alexander.h.duyck@intel.com>2009-02-19 23:40:07 -0500
committerDavid S. Miller <davem@davemloft.net>2009-02-20 03:22:54 -0500
commit4ae196dfd61d06b061c069edcdd7c73121e60a21 (patch)
tree68111629e73751b6200cc9bdd8b769246fe0d540 /drivers/net/igb/e1000_defines.h
parente173952257d7a3d3c64de3039d9fc02d1fbf49c3 (diff)
igb: Add support for enabling VFs to PF driver.
This patch adds the support to handle requests from the VF to perform operations such as completing resets, setting/reading mac address, adding vlans, adding multicast addresses, setting rlpml, and general communications between the PF and all VFs. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_defines.h')
-rw-r--r--drivers/net/igb/e1000_defines.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index d7613db78000..62e378b64611 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -45,6 +45,8 @@
45 45
46/* Extended Device Control */ 46/* Extended Device Control */
47#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 47#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
48/* Physical Func Reset Done Indication */
49#define E1000_CTRL_EXT_PFRSTD 0x00004000
48#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 50#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
49#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 51#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
50#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 52#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
@@ -325,6 +327,7 @@
325#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 327#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
326#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 328#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
327#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 329#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
330#define E1000_ICR_VMMB 0x00000100 /* VM MB event */
328/* If this bit asserted, the driver should claim the interrupt */ 331/* If this bit asserted, the driver should claim the interrupt */
329#define E1000_ICR_INT_ASSERTED 0x80000000 332#define E1000_ICR_INT_ASSERTED 0x80000000
330/* LAN connected device generates an interrupt */ 333/* LAN connected device generates an interrupt */
@@ -362,6 +365,7 @@
362/* Interrupt Mask Set */ 365/* Interrupt Mask Set */
363#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 366#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
364#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 367#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
368#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
365#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 369#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
366#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 370#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
367#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 371#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
@@ -413,6 +417,7 @@
413#define E1000_BLK_PHY_RESET 12 417#define E1000_BLK_PHY_RESET 12
414#define E1000_ERR_SWFW_SYNC 13 418#define E1000_ERR_SWFW_SYNC 13
415#define E1000_NOT_IMPLEMENTED 14 419#define E1000_NOT_IMPLEMENTED 14
420#define E1000_ERR_MBX 15
416 421
417/* Loop limit on how long we wait for auto-negotiation to complete */ 422/* Loop limit on how long we wait for auto-negotiation to complete */
418#define COPPER_LINK_UP_LIMIT 10 423#define COPPER_LINK_UP_LIMIT 10
@@ -659,4 +664,8 @@
659#define E1000_GEN_CTL_ADDRESS_SHIFT 8 664#define E1000_GEN_CTL_ADDRESS_SHIFT 8
660#define E1000_GEN_POLL_TIMEOUT 640 665#define E1000_GEN_POLL_TIMEOUT 640
661 666
667#define E1000_VFTA_ENTRY_SHIFT 5
668#define E1000_VFTA_ENTRY_MASK 0x7F
669#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
670
662#endif 671#endif