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authorJeb Cramer <cramerj@intel.com>2008-07-08 18:07:55 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-07-11 01:20:31 -0400
commitfe4506b6a2f9716ef62583020581ae2032573fed (patch)
tree560ae7093af7a852111cde72cf848f64cf9e8687 /drivers/net/igb/e1000_82575.h
parente21ed3538f1946ea623caf28f1c44ede50224275 (diff)
igb: add DCA support
Add DCA support in the similar method that it was added to the ixgbe driver recently. DCA allows the network device to put data in the CPU cache and notify the chipset of that event. This reduces cache misses during receives. Signed-off-by: Jeb Cramer <cramerj@intel.com> Signed-off-by: Mitch Williams <mitch.a.williams@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/igb/e1000_82575.h')
-rw-r--r--drivers/net/igb/e1000_82575.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h
index d78ad33d32bf..02e57a8447cb 100644
--- a/drivers/net/igb/e1000_82575.h
+++ b/drivers/net/igb/e1000_82575.h
@@ -144,9 +144,20 @@ struct e1000_adv_tx_context_desc {
144#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 144#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
145 145
146/* Direct Cache Access (DCA) definitions */ 146/* Direct Cache Access (DCA) definitions */
147#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
148#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
147 149
150#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
151#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
148 152
153#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
154#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
155#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
156#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
149 157
158#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
159#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
150#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 160#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
151 161
162
152#endif 163#endif