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authorEugene Surovegin <ebs@ebshome.net>2005-10-10 19:58:14 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-10-28 16:42:01 -0400
commit37448f7d39717db7c1098c1a88b9074694c69797 (patch)
tree18e019dd740c12a3af6e603aaefff985f0faea59 /drivers/net/ibm_emac/ibm_emac.h
parentb71b95efa5abca33e1bfb85d55162c7f99f54c23 (diff)
[PATCH] New PowerPC 4xx on-chip ethernet controller driver
This patch replaces current PowerPC 4xx EMAC driver with new, re-written from the scratch version. This patch is quite big (~234K) because there is virtualy 0% of common code between old and new version. New driver uses NAPI, it solves stability problems under heavy packet load and low memory, corrects chip register access and fixes numerous small bugs I don't even remember now. This patch has been tested on all supported in 2.6 PPC 4xx boards. It's been used in production for almost a year now on custom 4xx hardware. PPC32 specific parts are already upstream. Patch was acked by the current EMAC driver maintainer (Matt Porter). I will be maintaining this new version. Signed-off-by: Eugene Surovegin <ebs@ebshome.net> -- Kconfig | 72 ibm_emac/Makefile | 13 ibm_emac/ibm_emac.h | 418 +++-- ibm_emac/ibm_emac_core.c | 3414 ++++++++++++++++++++++++---------------------- ibm_emac/ibm_emac_core.h | 313 ++-- ibm_emac/ibm_emac_debug.c | 377 ++--- ibm_emac/ibm_emac_debug.h | 63 ibm_emac/ibm_emac_mal.c | 674 +++++---- ibm_emac/ibm_emac_mal.h | 336 +++- ibm_emac/ibm_emac_phy.c | 335 ++-- ibm_emac/ibm_emac_phy.h | 105 - ibm_emac/ibm_emac_rgmii.c | 201 ++ ibm_emac/ibm_emac_rgmii.h | 68 ibm_emac/ibm_emac_tah.c | 111 + ibm_emac/ibm_emac_tah.h | 96 - ibm_emac/ibm_emac_zmii.c | 255 +++ ibm_emac/ibm_emac_zmii.h | 114 - 17 files changed, 4114 insertions(+), 2851 deletions(-) Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/ibm_emac/ibm_emac.h')
-rw-r--r--drivers/net/ibm_emac/ibm_emac.h408
1 files changed, 225 insertions, 183 deletions
diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h
index 15d5a0e82862..28c476f28c20 100644
--- a/drivers/net/ibm_emac/ibm_emac.h
+++ b/drivers/net/ibm_emac/ibm_emac.h
@@ -1,110 +1,142 @@
1/* 1/*
2 * ibm_emac.h 2 * drivers/net/ibm_emac/ibm_emac.h
3 * 3 *
4 * Register definitions for PowerPC 4xx on-chip ethernet contoller
4 * 5 *
5 * Armin Kuster akuster@mvista.com 6 * Copyright (c) 2004, 2005 Zultys Technologies.
6 * June, 2002 7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
7 * 8 *
8 * Copyright 2002 MontaVista Softare Inc. 9 * Based on original work by
10 * Matt Porter <mporter@kernel.crashing.org>
11 * Armin Kuster <akuster@mvista.com>
12 * Copyright 2002-2004 MontaVista Software Inc.
9 * 13 *
10 * This program is free software; you can redistribute it and/or modify it 14 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 15 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your 16 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version. 17 * option) any later version.
18 *
14 */ 19 */
20#ifndef __IBM_EMAC_H_
21#define __IBM_EMAC_H_
22
23#include <linux/config.h>
24#include <linux/types.h>
25
26/* This is a simple check to prevent use of this driver on non-tested SoCs */
27#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
28 !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
29 !defined(CONFIG_440EP) && !defined(CONFIG_NP405H)
30#error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
31#endif
32
33/* EMAC registers Write Access rules */
34struct emac_regs {
35 u32 mr0; /* special */
36 u32 mr1; /* Reset */
37 u32 tmr0; /* special */
38 u32 tmr1; /* special */
39 u32 rmr; /* Reset */
40 u32 isr; /* Always */
41 u32 iser; /* Reset */
42 u32 iahr; /* Reset, R, T */
43 u32 ialr; /* Reset, R, T */
44 u32 vtpid; /* Reset, R, T */
45 u32 vtci; /* Reset, R, T */
46 u32 ptr; /* Reset, T */
47 u32 iaht1; /* Reset, R */
48 u32 iaht2; /* Reset, R */
49 u32 iaht3; /* Reset, R */
50 u32 iaht4; /* Reset, R */
51 u32 gaht1; /* Reset, R */
52 u32 gaht2; /* Reset, R */
53 u32 gaht3; /* Reset, R */
54 u32 gaht4; /* Reset, R */
55 u32 lsah;
56 u32 lsal;
57 u32 ipgvr; /* Reset, T */
58 u32 stacr; /* special */
59 u32 trtr; /* special */
60 u32 rwmr; /* Reset */
61 u32 octx;
62 u32 ocrx;
63 u32 ipcr;
64};
65
66#if !defined(CONFIG_IBM_EMAC4)
67#define EMAC_ETHTOOL_REGS_VER 0
68#define EMAC_ETHTOOL_REGS_SIZE (sizeof(struct emac_regs) - sizeof(u32))
69#else
70#define EMAC_ETHTOOL_REGS_VER 1
71#define EMAC_ETHTOOL_REGS_SIZE sizeof(struct emac_regs)
72#endif
15 73
16#ifndef _IBM_EMAC_H_ 74/* EMACx_MR0 */
17#define _IBM_EMAC_H_ 75#define EMAC_MR0_RXI 0x80000000
18/* General defines needed for the driver */ 76#define EMAC_MR0_TXI 0x40000000
77#define EMAC_MR0_SRST 0x20000000
78#define EMAC_MR0_TXE 0x10000000
79#define EMAC_MR0_RXE 0x08000000
80#define EMAC_MR0_WKE 0x04000000
19 81
20/* Emac */ 82/* EMACx_MR1 */
21typedef struct emac_regs { 83#define EMAC_MR1_FDE 0x80000000
22 u32 em0mr0; 84#define EMAC_MR1_ILE 0x40000000
23 u32 em0mr1; 85#define EMAC_MR1_VLE 0x20000000
24 u32 em0tmr0; 86#define EMAC_MR1_EIFC 0x10000000
25 u32 em0tmr1; 87#define EMAC_MR1_APP 0x08000000
26 u32 em0rmr; 88#define EMAC_MR1_IST 0x01000000
27 u32 em0isr;
28 u32 em0iser;
29 u32 em0iahr;
30 u32 em0ialr;
31 u32 em0vtpid;
32 u32 em0vtci;
33 u32 em0ptr;
34 u32 em0iaht1;
35 u32 em0iaht2;
36 u32 em0iaht3;
37 u32 em0iaht4;
38 u32 em0gaht1;
39 u32 em0gaht2;
40 u32 em0gaht3;
41 u32 em0gaht4;
42 u32 em0lsah;
43 u32 em0lsal;
44 u32 em0ipgvr;
45 u32 em0stacr;
46 u32 em0trtr;
47 u32 em0rwmr;
48} emac_t;
49 89
50/* MODE REG 0 */ 90#define EMAC_MR1_MF_MASK 0x00c00000
51#define EMAC_M0_RXI 0x80000000 91#define EMAC_MR1_MF_10 0x00000000
52#define EMAC_M0_TXI 0x40000000 92#define EMAC_MR1_MF_100 0x00400000
53#define EMAC_M0_SRST 0x20000000 93#if !defined(CONFIG_IBM_EMAC4)
54#define EMAC_M0_TXE 0x10000000 94#define EMAC_MR1_MF_1000 0x00000000
55#define EMAC_M0_RXE 0x08000000 95#define EMAC_MR1_MF_1000GPCS 0x00000000
56#define EMAC_M0_WKE 0x04000000 96#define EMAC_MR1_MF_IPPA(id) 0x00000000
97#else
98#define EMAC_MR1_MF_1000 0x00800000
99#define EMAC_MR1_MF_1000GPCS 0x00c00000
100#define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6)
101#endif
57 102
58/* MODE Reg 1 */ 103#define EMAC_TX_FIFO_SIZE 2048
59#define EMAC_M1_FDE 0x80000000
60#define EMAC_M1_ILE 0x40000000
61#define EMAC_M1_VLE 0x20000000
62#define EMAC_M1_EIFC 0x10000000
63#define EMAC_M1_APP 0x08000000
64#define EMAC_M1_AEMI 0x02000000
65#define EMAC_M1_IST 0x01000000
66#define EMAC_M1_MF_1000GPCS 0x00c00000 /* Internal GPCS */
67#define EMAC_M1_MF_1000MBPS 0x00800000 /* External GPCS */
68#define EMAC_M1_MF_100MBPS 0x00400000
69#define EMAC_M1_RFS_16K 0x00280000 /* 000 for 512 byte */
70#define EMAC_M1_TR 0x00008000
71#ifdef CONFIG_IBM_EMAC4
72#define EMAC_M1_RFS_8K 0x00200000
73#define EMAC_M1_RFS_4K 0x00180000
74#define EMAC_M1_RFS_2K 0x00100000
75#define EMAC_M1_RFS_1K 0x00080000
76#define EMAC_M1_TX_FIFO_16K 0x00050000 /* 0's for 512 byte */
77#define EMAC_M1_TX_FIFO_8K 0x00040000
78#define EMAC_M1_TX_FIFO_4K 0x00030000
79#define EMAC_M1_TX_FIFO_2K 0x00020000
80#define EMAC_M1_TX_FIFO_1K 0x00010000
81#define EMAC_M1_TX_TR 0x00008000
82#define EMAC_M1_TX_MWSW 0x00001000 /* 0 wait for status */
83#define EMAC_M1_JUMBO_ENABLE 0x00000800 /* Upt to 9Kr status */
84#define EMAC_M1_OPB_CLK_66 0x00000008 /* 66Mhz */
85#define EMAC_M1_OPB_CLK_83 0x00000010 /* 83Mhz */
86#define EMAC_M1_OPB_CLK_100 0x00000018 /* 100Mhz */
87#define EMAC_M1_OPB_CLK_100P 0x00000020 /* 100Mhz+ */
88#else /* CONFIG_IBM_EMAC4 */
89#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
90#define EMAC_M1_RFS_2K 0x00200000
91#define EMAC_M1_RFS_1K 0x00100000
92#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
93#define EMAC_M1_TX_FIFO_1K 0x00040000
94#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
95#define EMAC_M1_TR1_DEPEND 0x00004000
96#define EMAC_M1_TR1_MULTI 0x00002000
97#define EMAC_M1_JUMBO_ENABLE 0x00001000
98#endif /* CONFIG_IBM_EMAC4 */
99#define EMAC_M1_BASE (EMAC_M1_TX_FIFO_2K | \
100 EMAC_M1_APP | \
101 EMAC_M1_TR | EMAC_M1_VLE)
102 104
103/* Transmit Mode Register 0 */ 105#if !defined(CONFIG_IBM_EMAC4)
104#define EMAC_TMR0_GNP0 0x80000000 106#define EMAC_MR1_RFS_4K 0x00300000
105#define EMAC_TMR0_GNP1 0x40000000 107#define EMAC_MR1_RFS_16K 0x00000000
106#define EMAC_TMR0_GNPD 0x20000000 108#define EMAC_RX_FIFO_SIZE(gige) 4096
107#define EMAC_TMR0_FC 0x10000000 109#define EMAC_MR1_TFS_2K 0x00080000
110#define EMAC_MR1_TR0_MULT 0x00008000
111#define EMAC_MR1_JPSM 0x00000000
112#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
113#else
114#define EMAC_MR1_RFS_4K 0x00180000
115#define EMAC_MR1_RFS_16K 0x00280000
116#define EMAC_RX_FIFO_SIZE(gige) ((gige) ? 16384 : 4096)
117#define EMAC_MR1_TFS_2K 0x00020000
118#define EMAC_MR1_TR 0x00008000
119#define EMAC_MR1_MWSW_001 0x00001000
120#define EMAC_MR1_JPSM 0x00000800
121#define EMAC_MR1_OBCI_MASK 0x00000038
122#define EMAC_MR1_OBCI_50 0x00000000
123#define EMAC_MR1_OBCI_66 0x00000008
124#define EMAC_MR1_OBCI_83 0x00000010
125#define EMAC_MR1_OBCI_100 0x00000018
126#define EMAC_MR1_OBCI_100P 0x00000020
127#define EMAC_MR1_OBCI(freq) ((freq) <= 50 ? EMAC_MR1_OBCI_50 : \
128 (freq) <= 66 ? EMAC_MR1_OBCI_66 : \
129 (freq) <= 83 ? EMAC_MR1_OBCI_83 : \
130 (freq) <= 100 ? EMAC_MR1_OBCI_100 : EMAC_MR1_OBCI_100P)
131#define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR | \
132 EMAC_MR1_MWSW_001 | EMAC_MR1_OBCI(opb))
133#endif
134
135/* EMACx_TMR0 */
136#define EMAC_TMR0_GNP 0x80000000
137#if !defined(CONFIG_IBM_EMAC4)
138#define EMAC_TMR0_DEFAULT 0x00000000
139#else
108#define EMAC_TMR0_TFAE_2_32 0x00000001 140#define EMAC_TMR0_TFAE_2_32 0x00000001
109#define EMAC_TMR0_TFAE_4_64 0x00000002 141#define EMAC_TMR0_TFAE_4_64 0x00000002
110#define EMAC_TMR0_TFAE_8_128 0x00000003 142#define EMAC_TMR0_TFAE_8_128 0x00000003
@@ -112,14 +144,36 @@ typedef struct emac_regs {
112#define EMAC_TMR0_TFAE_32_512 0x00000005 144#define EMAC_TMR0_TFAE_32_512 0x00000005
113#define EMAC_TMR0_TFAE_64_1024 0x00000006 145#define EMAC_TMR0_TFAE_64_1024 0x00000006
114#define EMAC_TMR0_TFAE_128_2048 0x00000007 146#define EMAC_TMR0_TFAE_128_2048 0x00000007
147#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_2_32
148#endif
149#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
150
151/* EMACx_TMR1 */
152
153/* IBM manuals are not very clear here.
154 * This is my interpretation of how things are. --ebs
155 */
156#if defined(CONFIG_40x)
157#define EMAC_FIFO_ENTRY_SIZE 8
158#define EMAC_MAL_BURST_SIZE (16 * 4)
159#else
160#define EMAC_FIFO_ENTRY_SIZE 16
161#define EMAC_MAL_BURST_SIZE (64 * 4)
162#endif
163
164#if !defined(CONFIG_IBM_EMAC4)
165#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0xff) << 16))
166#else
167#define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0x3ff) << 14))
168#endif
115 169
116/* Receive Mode Register */ 170/* EMACx_RMR */
117#define EMAC_RMR_SP 0x80000000 171#define EMAC_RMR_SP 0x80000000
118#define EMAC_RMR_SFCS 0x40000000 172#define EMAC_RMR_SFCS 0x40000000
119#define EMAC_RMR_ARRP 0x20000000 173#define EMAC_RMR_RRP 0x20000000
120#define EMAC_RMR_ARP 0x10000000 174#define EMAC_RMR_RFP 0x10000000
121#define EMAC_RMR_AROP 0x08000000 175#define EMAC_RMR_ROP 0x08000000
122#define EMAC_RMR_ARPI 0x04000000 176#define EMAC_RMR_RPIR 0x04000000
123#define EMAC_RMR_PPP 0x02000000 177#define EMAC_RMR_PPP 0x02000000
124#define EMAC_RMR_PME 0x01000000 178#define EMAC_RMR_PME 0x01000000
125#define EMAC_RMR_PMME 0x00800000 179#define EMAC_RMR_PMME 0x00800000
@@ -127,6 +181,9 @@ typedef struct emac_regs {
127#define EMAC_RMR_MIAE 0x00200000 181#define EMAC_RMR_MIAE 0x00200000
128#define EMAC_RMR_BAE 0x00100000 182#define EMAC_RMR_BAE 0x00100000
129#define EMAC_RMR_MAE 0x00080000 183#define EMAC_RMR_MAE 0x00080000
184#if !defined(CONFIG_IBM_EMAC4)
185#define EMAC_RMR_BASE 0x00000000
186#else
130#define EMAC_RMR_RFAF_2_32 0x00000001 187#define EMAC_RMR_RFAF_2_32 0x00000001
131#define EMAC_RMR_RFAF_4_64 0x00000002 188#define EMAC_RMR_RFAF_4_64 0x00000002
132#define EMAC_RMR_RFAF_8_128 0x00000003 189#define EMAC_RMR_RFAF_8_128 0x00000003
@@ -134,9 +191,21 @@ typedef struct emac_regs {
134#define EMAC_RMR_RFAF_32_512 0x00000005 191#define EMAC_RMR_RFAF_32_512 0x00000005
135#define EMAC_RMR_RFAF_64_1024 0x00000006 192#define EMAC_RMR_RFAF_64_1024 0x00000006
136#define EMAC_RMR_RFAF_128_2048 0x00000007 193#define EMAC_RMR_RFAF_128_2048 0x00000007
137#define EMAC_RMR_BASE (EMAC_RMR_IAE | EMAC_RMR_BAE) 194#define EMAC_RMR_BASE EMAC_RMR_RFAF_128_2048
195#endif
138 196
139/* Interrupt Status & enable Regs */ 197/* EMACx_ISR & EMACx_ISER */
198#if !defined(CONFIG_IBM_EMAC4)
199#define EMAC_ISR_TXPE 0x00000000
200#define EMAC_ISR_RXPE 0x00000000
201#define EMAC_ISR_TXUE 0x00000000
202#define EMAC_ISR_RXOE 0x00000000
203#else
204#define EMAC_ISR_TXPE 0x20000000
205#define EMAC_ISR_RXPE 0x10000000
206#define EMAC_ISR_TXUE 0x08000000
207#define EMAC_ISR_RXOE 0x04000000
208#endif
140#define EMAC_ISR_OVR 0x02000000 209#define EMAC_ISR_OVR 0x02000000
141#define EMAC_ISR_PP 0x01000000 210#define EMAC_ISR_PP 0x01000000
142#define EMAC_ISR_BP 0x00800000 211#define EMAC_ISR_BP 0x00800000
@@ -147,53 +216,62 @@ typedef struct emac_regs {
147#define EMAC_ISR_PTLE 0x00040000 216#define EMAC_ISR_PTLE 0x00040000
148#define EMAC_ISR_ORE 0x00020000 217#define EMAC_ISR_ORE 0x00020000
149#define EMAC_ISR_IRE 0x00010000 218#define EMAC_ISR_IRE 0x00010000
150#define EMAC_ISR_DBDM 0x00000200 219#define EMAC_ISR_SQE 0x00000080
151#define EMAC_ISR_DB0 0x00000100 220#define EMAC_ISR_TE 0x00000040
152#define EMAC_ISR_SE0 0x00000080
153#define EMAC_ISR_TE0 0x00000040
154#define EMAC_ISR_DB1 0x00000020
155#define EMAC_ISR_SE1 0x00000010
156#define EMAC_ISR_TE1 0x00000008
157#define EMAC_ISR_MOS 0x00000002 221#define EMAC_ISR_MOS 0x00000002
158#define EMAC_ISR_MOF 0x00000001 222#define EMAC_ISR_MOF 0x00000001
159 223
160/* STA CONTROL REG */ 224/* EMACx_STACR */
225#define EMAC_STACR_PHYD_MASK 0xffff
226#define EMAC_STACR_PHYD_SHIFT 16
161#define EMAC_STACR_OC 0x00008000 227#define EMAC_STACR_OC 0x00008000
162#define EMAC_STACR_PHYE 0x00004000 228#define EMAC_STACR_PHYE 0x00004000
163#define EMAC_STACR_WRITE 0x00002000 229#define EMAC_STACR_STAC_MASK 0x00003000
164#define EMAC_STACR_READ 0x00001000 230#define EMAC_STACR_STAC_READ 0x00001000
165#define EMAC_STACR_CLK_83MHZ 0x00000800 /* 0's for 50Mhz */ 231#define EMAC_STACR_STAC_WRITE 0x00002000
166#define EMAC_STACR_CLK_66MHZ 0x00000400 232#if !defined(CONFIG_IBM_EMAC4)
167#define EMAC_STACR_CLK_100MHZ 0x00000C00 233#define EMAC_STACR_OPBC_MASK 0x00000C00
234#define EMAC_STACR_OPBC_50 0x00000000
235#define EMAC_STACR_OPBC_66 0x00000400
236#define EMAC_STACR_OPBC_83 0x00000800
237#define EMAC_STACR_OPBC_100 0x00000C00
238#define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
239 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
240 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
241#define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb)
242#else
243#define EMAC_STACR_BASE(opb) 0x00000000
244#endif
245#define EMAC_STACR_PCDA_MASK 0x1f
246#define EMAC_STACR_PCDA_SHIFT 5
247#define EMAC_STACR_PRA_MASK 0x1f
248
249/* EMACx_TRTR */
250#if !defined(CONFIG_IBM_EMAC4)
251#define EMAC_TRTR_SHIFT 27
252#else
253#define EMAC_TRTR_SHIFT 24
254#endif
255#define EMAC_TRTR(size) ((((size) >> 6) - 1) << EMAC_TRTR_SHIFT)
168 256
169/* Transmit Request Threshold Register */ 257/* EMACx_RWMR */
170#define EMAC_TRTR_1600 0x18000000 /* 0's for 64 Bytes */ 258#if !defined(CONFIG_IBM_EMAC4)
171#define EMAC_TRTR_1024 0x0f000000 259#define EMAC_RWMR(l,h) (((l) << 23) | ( ((h) & 0x1ff) << 7))
172#define EMAC_TRTR_512 0x07000000 260#else
173#define EMAC_TRTR_256 0x03000000 261#define EMAC_RWMR(l,h) (((l) << 22) | ( ((h) & 0x3ff) << 6))
174#define EMAC_TRTR_192 0x10000000 262#endif
175#define EMAC_TRTR_128 0x01000000
176 263
264/* EMAC specific TX descriptor control fields (write access) */
177#define EMAC_TX_CTRL_GFCS 0x0200 265#define EMAC_TX_CTRL_GFCS 0x0200
178#define EMAC_TX_CTRL_GP 0x0100 266#define EMAC_TX_CTRL_GP 0x0100
179#define EMAC_TX_CTRL_ISA 0x0080 267#define EMAC_TX_CTRL_ISA 0x0080
180#define EMAC_TX_CTRL_RSA 0x0040 268#define EMAC_TX_CTRL_RSA 0x0040
181#define EMAC_TX_CTRL_IVT 0x0020 269#define EMAC_TX_CTRL_IVT 0x0020
182#define EMAC_TX_CTRL_RVT 0x0010 270#define EMAC_TX_CTRL_RVT 0x0010
183#define EMAC_TX_CTRL_TAH_CSUM 0x000e /* TAH only */ 271#define EMAC_TX_CTRL_TAH_CSUM 0x000e
184#define EMAC_TX_CTRL_TAH_SEG4 0x000a /* TAH only */
185#define EMAC_TX_CTRL_TAH_SEG3 0x0008 /* TAH only */
186#define EMAC_TX_CTRL_TAH_SEG2 0x0006 /* TAH only */
187#define EMAC_TX_CTRL_TAH_SEG1 0x0004 /* TAH only */
188#define EMAC_TX_CTRL_TAH_SEG0 0x0002 /* TAH only */
189#define EMAC_TX_CTRL_TAH_DIS 0x0000 /* TAH only */
190 272
191#define EMAC_TX_CTRL_DFLT ( \ 273/* EMAC specific TX descriptor status fields (read access) */
192 MAL_TX_CTRL_INTR | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP )
193
194/* madmal transmit status / Control bits */
195#define EMAC_TX_ST_BFCS 0x0200 274#define EMAC_TX_ST_BFCS 0x0200
196#define EMAC_TX_ST_BPP 0x0100
197#define EMAC_TX_ST_LCS 0x0080 275#define EMAC_TX_ST_LCS 0x0080
198#define EMAC_TX_ST_ED 0x0040 276#define EMAC_TX_ST_ED 0x0040
199#define EMAC_TX_ST_EC 0x0020 277#define EMAC_TX_ST_EC 0x0020
@@ -202,8 +280,16 @@ typedef struct emac_regs {
202#define EMAC_TX_ST_SC 0x0004 280#define EMAC_TX_ST_SC 0x0004
203#define EMAC_TX_ST_UR 0x0002 281#define EMAC_TX_ST_UR 0x0002
204#define EMAC_TX_ST_SQE 0x0001 282#define EMAC_TX_ST_SQE 0x0001
283#if !defined(CONFIG_IBM_EMAC_TAH)
284#define EMAC_IS_BAD_TX(v) ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
285 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
286 EMAC_TX_ST_MC | EMAC_TX_ST_UR))
287#else
288#define EMAC_IS_BAD_TX(v) ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
289 EMAC_TX_ST_EC | EMAC_TX_ST_LC))
290#endif
205 291
206/* madmal receive status / Control bits */ 292/* EMAC specific RX descriptor status fields (read access) */
207#define EMAC_RX_ST_OE 0x0200 293#define EMAC_RX_ST_OE 0x0200
208#define EMAC_RX_ST_PP 0x0100 294#define EMAC_RX_ST_PP 0x0100
209#define EMAC_RX_ST_BP 0x0080 295#define EMAC_RX_ST_BP 0x0080
@@ -214,54 +300,10 @@ typedef struct emac_regs {
214#define EMAC_RX_ST_PTL 0x0004 300#define EMAC_RX_ST_PTL 0x0004
215#define EMAC_RX_ST_ORE 0x0002 301#define EMAC_RX_ST_ORE 0x0002
216#define EMAC_RX_ST_IRE 0x0001 302#define EMAC_RX_ST_IRE 0x0001
217#define EMAC_BAD_RX_PACKET 0x02ff 303#define EMAC_RX_TAH_BAD_CSUM 0x0003
218#define EMAC_CSUM_VER_ERROR 0x0003 304#define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
219 305 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
220/* identify a bad rx packet dependent on emac features */ 306 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
221#ifdef CONFIG_IBM_EMAC4 307 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
222#define EMAC_IS_BAD_RX_PACKET(desc) \ 308 EMAC_RX_ST_IRE )
223 (((desc & (EMAC_BAD_RX_PACKET & ~EMAC_CSUM_VER_ERROR)) || \ 309#endif /* __IBM_EMAC_H_ */
224 ((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_ORE) || \
225 ((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_IRE)))
226#else
227#define EMAC_IS_BAD_RX_PACKET(desc) \
228 (desc & EMAC_BAD_RX_PACKET)
229#endif
230
231/* SoC implementation specific EMAC register defaults */
232#if defined(CONFIG_440GP)
233#define EMAC_RWMR_DEFAULT 0x80009000
234#define EMAC_TMR0_DEFAULT 0x00000000
235#define EMAC_TMR1_DEFAULT 0xf8640000
236#elif defined(CONFIG_440GX)
237#define EMAC_RWMR_DEFAULT 0x1000a200
238#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_2_32
239#define EMAC_TMR1_DEFAULT 0xa00f0000
240#elif defined(CONFIG_440SP)
241#define EMAC_RWMR_DEFAULT 0x08002000
242#define EMAC_TMR0_DEFAULT EMAC_TMR0_TFAE_128_2048
243#define EMAC_TMR1_DEFAULT 0xf8200000
244#else
245#define EMAC_RWMR_DEFAULT 0x0f002000
246#define EMAC_TMR0_DEFAULT 0x00000000
247#define EMAC_TMR1_DEFAULT 0x380f0000
248#endif /* CONFIG_440GP */
249
250/* Revision specific EMAC register defaults */
251#ifdef CONFIG_IBM_EMAC4
252#define EMAC_M1_DEFAULT (EMAC_M1_BASE | \
253 EMAC_M1_OPB_CLK_83 | \
254 EMAC_M1_TX_MWSW)
255#define EMAC_RMR_DEFAULT (EMAC_RMR_BASE | \
256 EMAC_RMR_RFAF_128_2048)
257#define EMAC_TMR0_XMIT (EMAC_TMR0_GNP0 | \
258 EMAC_TMR0_DEFAULT)
259#define EMAC_TRTR_DEFAULT EMAC_TRTR_1024
260#else /* !CONFIG_IBM_EMAC4 */
261#define EMAC_M1_DEFAULT EMAC_M1_BASE
262#define EMAC_RMR_DEFAULT EMAC_RMR_BASE
263#define EMAC_TMR0_XMIT EMAC_TMR0_GNP0
264#define EMAC_TRTR_DEFAULT EMAC_TRTR_1600
265#endif /* CONFIG_IBM_EMAC4 */
266
267#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-20 16:39:16 -0500