diff options
author | Andy Fleming <afleming@freescale.com> | 2005-11-11 13:38:59 -0500 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-11-18 13:31:26 -0500 |
commit | 7f7f53168dbee6d6a462acea666fddd18aad4f08 (patch) | |
tree | 9c59f9b4b7c06f70b48197408f37398e54b4771e /drivers/net/gianfar.h | |
parent | fed5eccdcf542742786701b2514b5cb7ab282b93 (diff) |
[PATCH] Gianfar update and sysfs support
This seems to have gotten lost, so I'll resend.
Signed-off-by: Andy Fleming <afleming@freescale.com>
* Added sysfs support to gianfar for modifying FIFO and stashing parameters
* Updated driver to support 10 Mbit, full duplex operation
* Improved comments throughout
* Cleaned up and optimized offloading code
* Fixed a bug where rx buffers were being improperly mapped and unmapped
* (only manifested if cache-coherency was off)
* Added support for using the eTSEC exact-match MAC registers
* Bumped the version to 1.3
* Added support for distinguishing between reduced 100 and 10 Mbit modes
* Modified default coalescing values to lower latency
* Added documentation
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/gianfar.h')
-rw-r--r-- | drivers/net/gianfar.h | 69 |
1 files changed, 38 insertions, 31 deletions
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h index 5065ba82cb76..94a91da84fbb 100644 --- a/drivers/net/gianfar.h +++ b/drivers/net/gianfar.h | |||
@@ -90,12 +90,26 @@ extern const char gfar_driver_version[]; | |||
90 | #define GFAR_RX_MAX_RING_SIZE 256 | 90 | #define GFAR_RX_MAX_RING_SIZE 256 |
91 | #define GFAR_TX_MAX_RING_SIZE 256 | 91 | #define GFAR_TX_MAX_RING_SIZE 256 |
92 | 92 | ||
93 | #define GFAR_MAX_FIFO_THRESHOLD 511 | ||
94 | #define GFAR_MAX_FIFO_STARVE 511 | ||
95 | #define GFAR_MAX_FIFO_STARVE_OFF 511 | ||
96 | |||
93 | #define DEFAULT_RX_BUFFER_SIZE 1536 | 97 | #define DEFAULT_RX_BUFFER_SIZE 1536 |
94 | #define TX_RING_MOD_MASK(size) (size-1) | 98 | #define TX_RING_MOD_MASK(size) (size-1) |
95 | #define RX_RING_MOD_MASK(size) (size-1) | 99 | #define RX_RING_MOD_MASK(size) (size-1) |
96 | #define JUMBO_BUFFER_SIZE 9728 | 100 | #define JUMBO_BUFFER_SIZE 9728 |
97 | #define JUMBO_FRAME_SIZE 9600 | 101 | #define JUMBO_FRAME_SIZE 9600 |
98 | 102 | ||
103 | #define DEFAULT_FIFO_TX_THR 0x100 | ||
104 | #define DEFAULT_FIFO_TX_STARVE 0x40 | ||
105 | #define DEFAULT_FIFO_TX_STARVE_OFF 0x80 | ||
106 | #define DEFAULT_BD_STASH 1 | ||
107 | #define DEFAULT_STASH_LENGTH 64 | ||
108 | #define DEFAULT_STASH_INDEX 0 | ||
109 | |||
110 | /* The number of Exact Match registers */ | ||
111 | #define GFAR_EM_NUM 15 | ||
112 | |||
99 | /* Latency of interface clock in nanoseconds */ | 113 | /* Latency of interface clock in nanoseconds */ |
100 | /* Interface clock latency , in this case, means the | 114 | /* Interface clock latency , in this case, means the |
101 | * time described by a value of 1 in the interrupt | 115 | * time described by a value of 1 in the interrupt |
@@ -112,11 +126,11 @@ extern const char gfar_driver_version[]; | |||
112 | 126 | ||
113 | #define DEFAULT_TX_COALESCE 1 | 127 | #define DEFAULT_TX_COALESCE 1 |
114 | #define DEFAULT_TXCOUNT 16 | 128 | #define DEFAULT_TXCOUNT 16 |
115 | #define DEFAULT_TXTIME 400 | 129 | #define DEFAULT_TXTIME 4 |
116 | 130 | ||
117 | #define DEFAULT_RX_COALESCE 1 | 131 | #define DEFAULT_RX_COALESCE 1 |
118 | #define DEFAULT_RXCOUNT 16 | 132 | #define DEFAULT_RXCOUNT 16 |
119 | #define DEFAULT_RXTIME 400 | 133 | #define DEFAULT_RXTIME 4 |
120 | 134 | ||
121 | #define TBIPA_VALUE 0x1f | 135 | #define TBIPA_VALUE 0x1f |
122 | #define MIIMCFG_INIT_VALUE 0x00000007 | 136 | #define MIIMCFG_INIT_VALUE 0x00000007 |
@@ -147,6 +161,7 @@ extern const char gfar_driver_version[]; | |||
147 | 161 | ||
148 | #define ECNTRL_INIT_SETTINGS 0x00001000 | 162 | #define ECNTRL_INIT_SETTINGS 0x00001000 |
149 | #define ECNTRL_TBI_MODE 0x00000020 | 163 | #define ECNTRL_TBI_MODE 0x00000020 |
164 | #define ECNTRL_R100 0x00000008 | ||
150 | 165 | ||
151 | #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE | 166 | #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE |
152 | 167 | ||
@@ -181,10 +196,12 @@ extern const char gfar_driver_version[]; | |||
181 | #define RCTRL_PRSDEP_MASK 0x000000c0 | 196 | #define RCTRL_PRSDEP_MASK 0x000000c0 |
182 | #define RCTRL_PRSDEP_INIT 0x000000c0 | 197 | #define RCTRL_PRSDEP_INIT 0x000000c0 |
183 | #define RCTRL_PROM 0x00000008 | 198 | #define RCTRL_PROM 0x00000008 |
199 | #define RCTRL_EMEN 0x00000002 | ||
184 | #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \ | 200 | #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \ |
185 | | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT) | 201 | | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT) |
186 | #define RCTRL_EXTHASH (RCTRL_GHTX) | 202 | #define RCTRL_EXTHASH (RCTRL_GHTX) |
187 | #define RCTRL_VLAN (RCTRL_PRSDEP_INIT) | 203 | #define RCTRL_VLAN (RCTRL_PRSDEP_INIT) |
204 | #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) | ||
188 | 205 | ||
189 | 206 | ||
190 | #define RSTAT_CLEAR_RHALT 0x00800000 | 207 | #define RSTAT_CLEAR_RHALT 0x00800000 |
@@ -251,28 +268,26 @@ extern const char gfar_driver_version[]; | |||
251 | IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ | 268 | IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ |
252 | | IMASK_PERR) | 269 | | IMASK_PERR) |
253 | 270 | ||
271 | /* Fifo management */ | ||
272 | #define FIFO_TX_THR_MASK 0x01ff | ||
273 | #define FIFO_TX_STARVE_MASK 0x01ff | ||
274 | #define FIFO_TX_STARVE_OFF_MASK 0x01ff | ||
254 | 275 | ||
255 | /* Attribute fields */ | 276 | /* Attribute fields */ |
256 | 277 | ||
257 | /* This enables rx snooping for buffers and descriptors */ | 278 | /* This enables rx snooping for buffers and descriptors */ |
258 | #ifdef CONFIG_GFAR_BDSTASH | ||
259 | #define ATTR_BDSTASH 0x00000800 | 279 | #define ATTR_BDSTASH 0x00000800 |
260 | #else | ||
261 | #define ATTR_BDSTASH 0x00000000 | ||
262 | #endif | ||
263 | 280 | ||
264 | #ifdef CONFIG_GFAR_BUFSTASH | ||
265 | #define ATTR_BUFSTASH 0x00004000 | 281 | #define ATTR_BUFSTASH 0x00004000 |
266 | #define STASH_LENGTH 64 | ||
267 | #else | ||
268 | #define ATTR_BUFSTASH 0x00000000 | ||
269 | #endif | ||
270 | 282 | ||
271 | #define ATTR_SNOOPING 0x000000c0 | 283 | #define ATTR_SNOOPING 0x000000c0 |
272 | #define ATTR_INIT_SETTINGS (ATTR_SNOOPING \ | 284 | #define ATTR_INIT_SETTINGS ATTR_SNOOPING |
273 | | ATTR_BDSTASH | ATTR_BUFSTASH) | ||
274 | 285 | ||
275 | #define ATTRELI_INIT_SETTINGS 0x0 | 286 | #define ATTRELI_INIT_SETTINGS 0x0 |
287 | #define ATTRELI_EL_MASK 0x3fff0000 | ||
288 | #define ATTRELI_EL(x) (x << 16) | ||
289 | #define ATTRELI_EI_MASK 0x00003fff | ||
290 | #define ATTRELI_EI(x) (x) | ||
276 | 291 | ||
277 | 292 | ||
278 | /* TxBD status field bits */ | 293 | /* TxBD status field bits */ |
@@ -328,6 +343,7 @@ extern const char gfar_driver_version[]; | |||
328 | #define RXFCB_CTU 0x0400 | 343 | #define RXFCB_CTU 0x0400 |
329 | #define RXFCB_EIP 0x0200 | 344 | #define RXFCB_EIP 0x0200 |
330 | #define RXFCB_ETU 0x0100 | 345 | #define RXFCB_ETU 0x0100 |
346 | #define RXFCB_CSUM_MASK 0x0f00 | ||
331 | #define RXFCB_PERR_MASK 0x000c | 347 | #define RXFCB_PERR_MASK 0x000c |
332 | #define RXFCB_PERR_BADL3 0x0008 | 348 | #define RXFCB_PERR_BADL3 0x0008 |
333 | 349 | ||
@@ -339,14 +355,7 @@ struct txbd8 | |||
339 | }; | 355 | }; |
340 | 356 | ||
341 | struct txfcb { | 357 | struct txfcb { |
342 | u8 vln:1, | 358 | u8 flags; |
343 | ip:1, | ||
344 | ip6:1, | ||
345 | tup:1, | ||
346 | udp:1, | ||
347 | cip:1, | ||
348 | ctu:1, | ||
349 | nph:1; | ||
350 | u8 reserved; | 359 | u8 reserved; |
351 | u8 l4os; /* Level 4 Header Offset */ | 360 | u8 l4os; /* Level 4 Header Offset */ |
352 | u8 l3os; /* Level 3 Header Offset */ | 361 | u8 l3os; /* Level 3 Header Offset */ |
@@ -362,14 +371,7 @@ struct rxbd8 | |||
362 | }; | 371 | }; |
363 | 372 | ||
364 | struct rxfcb { | 373 | struct rxfcb { |
365 | u16 vln:1, | 374 | u16 flags; |
366 | ip:1, | ||
367 | ip6:1, | ||
368 | tup:1, | ||
369 | cip:1, | ||
370 | ctu:1, | ||
371 | eip:1, | ||
372 | etu:1; | ||
373 | u8 rq; /* Receive Queue index */ | 375 | u8 rq; /* Receive Queue index */ |
374 | u8 pro; /* Layer 4 Protocol */ | 376 | u8 pro; /* Layer 4 Protocol */ |
375 | u16 reserved; | 377 | u16 reserved; |
@@ -688,12 +690,17 @@ struct gfar_private { | |||
688 | spinlock_t lock; | 690 | spinlock_t lock; |
689 | unsigned int rx_buffer_size; | 691 | unsigned int rx_buffer_size; |
690 | unsigned int rx_stash_size; | 692 | unsigned int rx_stash_size; |
693 | unsigned int rx_stash_index; | ||
691 | unsigned int tx_ring_size; | 694 | unsigned int tx_ring_size; |
692 | unsigned int rx_ring_size; | 695 | unsigned int rx_ring_size; |
696 | unsigned int fifo_threshold; | ||
697 | unsigned int fifo_starve; | ||
698 | unsigned int fifo_starve_off; | ||
693 | 699 | ||
694 | unsigned char vlan_enable:1, | 700 | unsigned char vlan_enable:1, |
695 | rx_csum_enable:1, | 701 | rx_csum_enable:1, |
696 | extended_hash:1; | 702 | extended_hash:1, |
703 | bd_stash_en:1; | ||
697 | unsigned short padding; | 704 | unsigned short padding; |
698 | struct vlan_group *vlgrp; | 705 | struct vlan_group *vlgrp; |
699 | /* Info structure initialized by board setup code */ | 706 | /* Info structure initialized by board setup code */ |
@@ -731,6 +738,6 @@ extern void stop_gfar(struct net_device *dev); | |||
731 | extern void gfar_halt(struct net_device *dev); | 738 | extern void gfar_halt(struct net_device *dev); |
732 | extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, | 739 | extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, |
733 | int enable, u32 regnum, u32 read); | 740 | int enable, u32 regnum, u32 read); |
734 | void gfar_setup_stashing(struct net_device *dev); | 741 | void gfar_init_sysfs(struct net_device *dev); |
735 | 742 | ||
736 | #endif /* __GIANFAR_H */ | 743 | #endif /* __GIANFAR_H */ |