diff options
author | Sandeep Gopalpet <Sandeep.Kumar@freescale.com> | 2009-11-02 02:03:28 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-11-03 02:40:58 -0500 |
commit | 2e0246c72fa2e2b61865a2d5aaff1cc9155b9447 (patch) | |
tree | 9e1fc6ec6d3ab7a52d37a6ce6a39200dc296dafd /drivers/net/gianfar.h | |
parent | 1d2397d742b7a2b39b2f09dd9da3b9d1463f55e9 (diff) |
gianfar: Add support etsec2.0 registers.
This patch adds support for etsec2.0 regsiters
Signed-off-by: Sandeep Gopalpet <Sandeep.Kumar@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/gianfar.h')
-rw-r--r-- | drivers/net/gianfar.h | 55 |
1 files changed, 44 insertions, 11 deletions
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h index 5ae769df1d81..08518c205035 100644 --- a/drivers/net/gianfar.h +++ b/drivers/net/gianfar.h | |||
@@ -566,25 +566,32 @@ struct gfar_stats { | |||
566 | 566 | ||
567 | struct gfar { | 567 | struct gfar { |
568 | u32 tsec_id; /* 0x.000 - Controller ID register */ | 568 | u32 tsec_id; /* 0x.000 - Controller ID register */ |
569 | u8 res1[12]; | 569 | u32 tsec_id2; /* 0x.004 - Controller ID2 register */ |
570 | u8 res1[8]; | ||
570 | u32 ievent; /* 0x.010 - Interrupt Event Register */ | 571 | u32 ievent; /* 0x.010 - Interrupt Event Register */ |
571 | u32 imask; /* 0x.014 - Interrupt Mask Register */ | 572 | u32 imask; /* 0x.014 - Interrupt Mask Register */ |
572 | u32 edis; /* 0x.018 - Error Disabled Register */ | 573 | u32 edis; /* 0x.018 - Error Disabled Register */ |
573 | u8 res2[4]; | 574 | u32 emapg; /* 0x.01c - Group Error mapping register */ |
574 | u32 ecntrl; /* 0x.020 - Ethernet Control Register */ | 575 | u32 ecntrl; /* 0x.020 - Ethernet Control Register */ |
575 | u32 minflr; /* 0x.024 - Minimum Frame Length Register */ | 576 | u32 minflr; /* 0x.024 - Minimum Frame Length Register */ |
576 | u32 ptv; /* 0x.028 - Pause Time Value Register */ | 577 | u32 ptv; /* 0x.028 - Pause Time Value Register */ |
577 | u32 dmactrl; /* 0x.02c - DMA Control Register */ | 578 | u32 dmactrl; /* 0x.02c - DMA Control Register */ |
578 | u32 tbipa; /* 0x.030 - TBI PHY Address Register */ | 579 | u32 tbipa; /* 0x.030 - TBI PHY Address Register */ |
579 | u8 res3[88]; | 580 | u8 res2[28]; |
581 | u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold | ||
582 | register */ | ||
583 | u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff | ||
584 | register */ | ||
585 | u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold | ||
586 | register */ | ||
587 | u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve | ||
588 | shutoff register */ | ||
589 | u8 res3[44]; | ||
580 | u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ | 590 | u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ |
581 | u8 res4[8]; | 591 | u8 res4[8]; |
582 | u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ | 592 | u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ |
583 | u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ | 593 | u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ |
584 | u8 res5[4]; | 594 | u8 res5[96]; |
585 | u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */ | ||
586 | u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */ | ||
587 | u8 res6[84]; | ||
588 | u32 tctrl; /* 0x.100 - Transmit Control Register */ | 595 | u32 tctrl; /* 0x.100 - Transmit Control Register */ |
589 | u32 tstat; /* 0x.104 - Transmit Status Register */ | 596 | u32 tstat; /* 0x.104 - Transmit Status Register */ |
590 | u32 dfvlan; /* 0x.108 - Default VLAN Control word */ | 597 | u32 dfvlan; /* 0x.108 - Default VLAN Control word */ |
@@ -635,7 +642,11 @@ struct gfar { | |||
635 | u8 res12[8]; | 642 | u8 res12[8]; |
636 | u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ | 643 | u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ |
637 | u32 rqueue; /* 0x.314 - Receive queue control register */ | 644 | u32 rqueue; /* 0x.314 - Receive queue control register */ |
638 | u8 res13[24]; | 645 | u32 rir0; /* 0x.318 - Ring mapping register 0 */ |
646 | u32 rir1; /* 0x.31c - Ring mapping register 1 */ | ||
647 | u32 rir2; /* 0x.320 - Ring mapping register 2 */ | ||
648 | u32 rir3; /* 0x.324 - Ring mapping register 3 */ | ||
649 | u8 res13[8]; | ||
639 | u32 rbifx; /* 0x.330 - Receive bit field extract control register */ | 650 | u32 rbifx; /* 0x.330 - Receive bit field extract control register */ |
640 | u32 rqfar; /* 0x.334 - Receive queue filing table address register */ | 651 | u32 rqfar; /* 0x.334 - Receive queue filing table address register */ |
641 | u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ | 652 | u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ |
@@ -684,7 +695,7 @@ struct gfar { | |||
684 | u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ | 695 | u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ |
685 | u8 res18[12]; | 696 | u8 res18[12]; |
686 | u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ | 697 | u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ |
687 | u8 res19[4]; | 698 | u32 ifctrl; /* 0x.538 - Interface control register */ |
688 | u32 ifstat; /* 0x.53c - Interface Status Register */ | 699 | u32 ifstat; /* 0x.53c - Interface Status Register */ |
689 | u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ | 700 | u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ |
690 | u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ | 701 | u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ |
@@ -745,8 +756,30 @@ struct gfar { | |||
745 | u8 res23c[248]; | 756 | u8 res23c[248]; |
746 | u32 attr; /* 0x.bf8 - Attributes Register */ | 757 | u32 attr; /* 0x.bf8 - Attributes Register */ |
747 | u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ | 758 | u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ |
748 | u8 res24[1024]; | 759 | u8 res24[688]; |
749 | 760 | u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */ | |
761 | u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */ | ||
762 | u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */ | ||
763 | u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */ | ||
764 | u8 res25[16]; | ||
765 | u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */ | ||
766 | u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */ | ||
767 | u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */ | ||
768 | u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */ | ||
769 | u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */ | ||
770 | u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */ | ||
771 | u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */ | ||
772 | u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */ | ||
773 | u8 res26[32]; | ||
774 | u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */ | ||
775 | u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */ | ||
776 | u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */ | ||
777 | u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */ | ||
778 | u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */ | ||
779 | u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */ | ||
780 | u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */ | ||
781 | u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */ | ||
782 | u8 res27[208]; | ||
750 | }; | 783 | }; |
751 | 784 | ||
752 | /* Flags related to gianfar device features */ | 785 | /* Flags related to gianfar device features */ |