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authorKapil Juneja <Kapil.Juneja@freescale.com>2007-05-11 19:25:11 -0400
committerJeff Garzik <jeff@garzik.org>2007-07-08 22:16:38 -0400
commitd3c12873c36005263286cf5660663c8c10f9d2b5 (patch)
tree8b51ae1aec834ece23271e6b569d7c4189422ad5 /drivers/net/gianfar.h
parent0cefeebaf3da39d768bffcf62460fe2088e824ef (diff)
gianfar: add support for SGMII
Add code for initialising and configuring TBI interface and programming it for connecting to on-chip SERDES (Lynx PHY) in case of SGMII mode selected through HRCW at reset. also add defines for TBI register configuration. TBI interface is programmed towards the SERDES. refactored mdio read/write functions to differentiate programming local interface MII regs (e.g., for TBI) from always programming the mdio master (TSEC1, for programming the PHYs). Signed-off-by: Kapil Juneja <Kapil.Juneja@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/gianfar.h')
-rw-r--r--drivers/net/gianfar.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h
index 39e9e321fcbc..d8e779c102fa 100644
--- a/drivers/net/gianfar.h
+++ b/drivers/net/gianfar.h
@@ -136,6 +136,12 @@ extern const char gfar_driver_version[];
136#define MIIMCFG_RESET 0x80000000 136#define MIIMCFG_RESET 0x80000000
137#define MIIMIND_BUSY 0x00000001 137#define MIIMIND_BUSY 0x00000001
138 138
139/* TBI register addresses */
140#define MII_TBICON 0x11
141
142/* TBICON register bit fields */
143#define TBICON_CLK_SELECT 0x0020
144
139/* MAC register bits */ 145/* MAC register bits */
140#define MACCFG1_SOFT_RESET 0x80000000 146#define MACCFG1_SOFT_RESET 0x80000000
141#define MACCFG1_RESET_RX_MC 0x00080000 147#define MACCFG1_RESET_RX_MC 0x00080000