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authorAndy Fleming <afleming@freescale.com>2009-02-04 19:38:05 -0500
committerDavid S. Miller <davem@davemloft.net>2009-02-04 19:38:05 -0500
commitb98ac702f49042ab0c382b839465b95a2bd0cd65 (patch)
tree344e61f5798864cdcab11e071842578765c9ba55 /drivers/net/gianfar.c
parent1fbe49328f7442090439addddf441fb5b3186e71 (diff)
gianfar: Fix potential soft reset race
SOFT_RESET must be asserted for at least 3 TX clocks in order for it to work properly. The syncs in the gfar_write() commands have been hiding this, but we need to guarantee it. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/gianfar.c')
-rw-r--r--drivers/net/gianfar.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index 3f7eab42aef1..acae2d8cd688 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -351,6 +351,9 @@ static int gfar_probe(struct of_device *ofdev,
351 /* Reset MAC layer */ 351 /* Reset MAC layer */
352 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); 352 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
353 353
354 /* We need to delay at least 3 TX clocks */
355 udelay(2);
356
354 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); 357 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
355 gfar_write(&priv->regs->maccfg1, tempval); 358 gfar_write(&priv->regs->maccfg1, tempval);
356 359