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authorAndy Fleming <afleming@freescale.com>2009-02-04 19:42:12 -0500
committerDavid S. Miller <davem@davemloft.net>2009-02-04 19:42:35 -0500
commit1577ecef766650a57fceb171acee2b13cbfaf1d3 (patch)
treeb66df11d8815f95f815e65c3c3ffd32df81b8d43 /drivers/net/fsl_pq_mdio.h
parent9c46f6d42f1b5627c49a5906cb5b315ad8716ff0 (diff)
netdev: Merge UCC and gianfar MDIO bus drivers
The MDIO bus drivers for the UCC and gianfar ethernet controllers are essentially the same. There's no reason to duplicate that much code. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/fsl_pq_mdio.h')
-rw-r--r--drivers/net/fsl_pq_mdio.h45
1 files changed, 45 insertions, 0 deletions
diff --git a/drivers/net/fsl_pq_mdio.h b/drivers/net/fsl_pq_mdio.h
new file mode 100644
index 000000000000..36dad527410b
--- /dev/null
+++ b/drivers/net/fsl_pq_mdio.h
@@ -0,0 +1,45 @@
1/*
2 * Freescale PowerQUICC MDIO Driver -- MII Management Bus Implementation
3 * Driver for the MDIO bus controller on Freescale PowerQUICC processors
4 *
5 * Author: Andy Fleming
6 *
7 * Copyright (c) 2002-2004,2008 Freescale Semiconductor, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15#ifndef __FSL_PQ_MDIO_H
16#define __FSL_PQ_MDIO_H
17
18#define MIIMIND_BUSY 0x00000001
19#define MIIMIND_NOTVALID 0x00000004
20#define MIIMCFG_INIT_VALUE 0x00000007
21#define MIIMCFG_RESET 0x80000000
22
23#define MII_READ_COMMAND 0x00000001
24
25struct fsl_pq_mdio {
26 u32 miimcfg; /* MII management configuration reg */
27 u32 miimcom; /* MII management command reg */
28 u32 miimadd; /* MII management address reg */
29 u32 miimcon; /* MII management control reg */
30 u32 miimstat; /* MII management status reg */
31 u32 miimind; /* MII management indication reg */
32 u8 reserved[28]; /* Space holder */
33 u32 utbipar; /* TBI phy address reg (only on UCC) */
34} __attribute__ ((packed));
35
36
37int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum);
38int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
39int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
40 int regnum, u16 value);
41int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs, int mii_id, int regnum);
42int __init fsl_pq_mdio_init(void);
43void fsl_pq_mdio_exit(void);
44void fsl_pq_mdio_bus_name(char *name, struct device_node *np);
45#endif /* FSL_PQ_MDIO_H */